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Merge: arm64: Add additional CPUs into the Spectre BHB safe/affected lists
MR: https://gitlab.com/redhat/centos-stream/src/kernel/centos-stream-9/-/merge_requests/7463 JIRA: https://issues.redhat.com/browse/RHEL-119900 MR: https://gitlab.com/redhat/centos-stream/src/kernel/centos-stream-9/-/merge_requests/7463 Omitted-fix: 14ec8ce ("tools headers: Sync arm64 headers with the kernel source") The commit e403e85 ("arm64: errata: Assume that unknown CPUs are vulnerable to Spectre BHB") was backported to RHEL 9.7/10.1 as part of the x86/arm64 Training Solo CPU vulnerability mitigation. This change the behavior of Spectre BHB bug detection from "assuming not vulnerable unless explicitly listed as vulnerable" to "assuming vulnerable unless explicitly listed as safe". This is probably the more appropriate action but it has impact on KVM guests migration refuses to propagate the "unaffected" state to a machine that is either vulnerable or mitigated. RHEL should align with upstream, but it is missing some patches that include additional arm64 CPUs into the safe and affected lists. This MR backports those missing patches to make sure Spectre BHB lists are up-to-date. Signed-off-by: Waiman Long <longman@redhat.com> Approved-by: Sebastian Ott <sebott@redhat.com> Approved-by: Gavin Shan <gshan@redhat.com> Approved-by: CKI KWF Bot <cki-ci-bot+kwf-gitlab-com@redhat.com> Merged-by: CKI GitLab Kmaint Pipeline Bot <26919896-cki-kmaint-pipeline-bot@users.noreply.gitlab.com>
2 parents 2bad3d9 + 6f3bf60 commit 286279d

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‎arch/arm64/include/asm/cputype.h‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -75,6 +75,7 @@
7575
#define ARM_CPU_PART_CORTEX_A76 0xD0B
7676
#define ARM_CPU_PART_NEOVERSE_N1 0xD0C
7777
#define ARM_CPU_PART_CORTEX_A77 0xD0D
78+
#define ARM_CPU_PART_CORTEX_A76AE 0xD0E
7879
#define ARM_CPU_PART_NEOVERSE_V1 0xD40
7980
#define ARM_CPU_PART_CORTEX_A78 0xD41
8081
#define ARM_CPU_PART_CORTEX_A78AE 0xD42
@@ -95,6 +96,7 @@
9596
#define ARM_CPU_PART_NEOVERSE_V3 0xD84
9697
#define ARM_CPU_PART_CORTEX_X925 0xD85
9798
#define ARM_CPU_PART_CORTEX_A725 0xD87
99+
#define ARM_CPU_PART_CORTEX_A720AE 0xD89
98100
#define ARM_CPU_PART_NEOVERSE_N3 0xD8E
99101

100102
#define APM_CPU_PART_XGENE 0x000
@@ -130,6 +132,7 @@
130132
#define FUJITSU_CPU_PART_A64FX 0x001
131133

132134
#define HISI_CPU_PART_TSV110 0xD01
135+
#define HISI_CPU_PART_HIP09 0xD02
133136

134137
#define APPLE_CPU_PART_M1_ICESTORM 0x022
135138
#define APPLE_CPU_PART_M1_FIRESTORM 0x023
@@ -159,6 +162,7 @@
159162
#define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
160163
#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
161164
#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
165+
#define MIDR_CORTEX_A76AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76AE)
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#define MIDR_NEOVERSE_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V1)
163167
#define MIDR_CORTEX_A78 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78)
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#define MIDR_CORTEX_A78AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78AE)
@@ -179,6 +183,7 @@
179183
#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
180184
#define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
181185
#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
186+
#define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE)
182187
#define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
183188
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
184189
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
@@ -204,6 +209,7 @@
204209
#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
205210
#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
206211
#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
212+
#define MIDR_HISI_HIP09 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP09)
207213
#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
208214
#define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
209215
#define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO)

‎arch/arm64/kernel/cpu_errata.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -441,6 +441,7 @@ static const struct midr_range erratum_spec_ssbs_list[] = {
441441
MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
442442
MIDR_ALL_VERSIONS(MIDR_CORTEX_A715),
443443
MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),
444+
MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE),
444445
MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),
446447
MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C),

‎arch/arm64/kernel/proton-pack.c‎

Lines changed: 21 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -854,6 +854,9 @@ static bool is_spectre_bhb_safe(int scope)
854854
MIDR_ALL_VERSIONS(MIDR_CORTEX_A510),
855855
MIDR_ALL_VERSIONS(MIDR_CORTEX_A520),
856856
MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
857+
MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
858+
MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
859+
MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
857860
{},
858861
};
859862
static bool all_safe = true;
@@ -873,6 +876,17 @@ static u8 spectre_bhb_loop_affected(void)
873876
{
874877
u8 k = 0;
875878

879+
static const struct midr_range spectre_bhb_k132_list[] = {
880+
MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),
881+
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),
882+
{},
883+
};
884+
static const struct midr_range spectre_bhb_k38_list[] = {
885+
MIDR_ALL_VERSIONS(MIDR_CORTEX_A715),
886+
MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),
887+
MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE),
888+
{},
889+
};
876890
static const struct midr_range spectre_bhb_k32_list[] = {
877891
MIDR_ALL_VERSIONS(MIDR_CORTEX_A78),
878892
MIDR_ALL_VERSIONS(MIDR_CORTEX_A78AE),
@@ -887,9 +901,11 @@ static u8 spectre_bhb_loop_affected(void)
887901
};
888902
static const struct midr_range spectre_bhb_k24_list[] = {
889903
MIDR_ALL_VERSIONS(MIDR_CORTEX_A76),
904+
MIDR_ALL_VERSIONS(MIDR_CORTEX_A76AE),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A77),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
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MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_GOLD),
908+
MIDR_ALL_VERSIONS(MIDR_HISI_HIP09),
893909
{},
894910
};
895911
static const struct midr_range spectre_bhb_k11_list[] = {
@@ -902,7 +918,11 @@ static u8 spectre_bhb_loop_affected(void)
902918
{},
903919
};
904920

905-
if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k32_list))
921+
if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k132_list))
922+
k = 132;
923+
else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k38_list))
924+
k = 38;
925+
else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k32_list))
906926
k = 32;
907927
else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k24_list))
908928
k = 24;

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