Merge: KVM: x86: Advertise support for AMD's PREFETCHI

MR: https://gitlab.com/redhat/centos-stream/src/kernel/centos-stream-9/-/merge_requests/7461

# Merge Request Required Information

## Summary of Changes

Latest AMD Platforms introduce a new instruction, PREFETCHI, that loads a cache line from a specified memory address into the indicated data or instruction cache level, based on locality reference hints.

Advertise support for the instruction to the user space

## Approved Development Ticket(s)

```
JIRA: https://issues.redhat.com/browse/RHEL-98696
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
```

<details><summary>Click for formatting instructions</summary>
Please follow the CentOS Stream [contribution documentation](https://docs.centos.org/en-US/stream-contrib/quickstart/) for how to file this ticket and have it approved.

List tickets each on their own line of this description using the format "Resolves: RHEL-76229", "Related: RHEL-76229" or "Reverts: RHEL-76229", as appropriate.
</details>

Approved-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Approved-by: Bandan Das <bsd@redhat.com>
Approved-by: Steve Best <sbest@redhat.com>
Approved-by: CKI KWF Bot <cki-ci-bot+kwf-gitlab-com@redhat.com>

Merged-by: CKI GitLab Kmaint Pipeline Bot <26919896-cki-kmaint-pipeline-bot@users.noreply.gitlab.com>

Author: CKI KWF Bot

arch/x86/include/asm/cpufeatures.h

@@ -464,6 +464,7 @@
 #define X86_FEATURE_AUTOIBRS		(20*32+ 8) /* Automatic IBRS */
 #define X86_FEATURE_NO_SMM_CTL_MSR	(20*32+ 9) /* SMM_CTL MSR is not present */
 
+#define X86_FEATURE_PREFETCHI		(20*32+20) /* Prefetch Data/Instruction to Cache Level */
 #define X86_FEATURE_SBPB		(20*32+27) /* Selective Branch Prediction Barrier */
 #define X86_FEATURE_IBPB_BRTYPE		(20*32+28) /* MSR_PRED_CMD[IBPB] flushes all branch type predictions */
 #define X86_FEATURE_SRSO_NO		(20*32+29) /* CPU is not affected by SRSO */

arch/x86/kvm/cpuid.c

@@ -837,6 +837,8 @@ void kvm_set_cpu_caps(void)
 	kvm_cpu_cap_check_and_set(X86_FEATURE_TSA_SQ_NO);
 	kvm_cpu_cap_check_and_set(X86_FEATURE_TSA_L1_NO);
 
+	kvm_cpu_cap_check_and_set(X86_FEATURE_PREFETCHI);
+
 	kvm_cpu_cap_init_kvm_defined(CPUID_8000_0022_EAX,
 		F(PERFMON_V2)
 	);