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Merge: crypto: octeontx2: update octeontx2 crypto driver to v6.17
MR: https://gitlab.com/redhat/centos-stream/src/kernel/centos-stream-9/-/merge_requests/7501 ``` JIRA: https://issues.redhat.com/browse/RHEL-122025 Upstream Status: 11 commits are merged into the linux.git Bring in the latest OcteonTX2 driver bugfixes and updates. Almost all the commits apply cleanly. One commit has a partial scope limited to the OcteonTX2 driver only. One commit requires a small edit due to a missing tree-wide upstream commit. Signed-off-by: Vladis Dronov <vdronov@redhat.com> ``` Approved-by: Tony Camuso <tcamuso@redhat.com> Approved-by: Herbert Xu <zxu@redhat.com> Approved-by: CKI KWF Bot <cki-ci-bot+kwf-gitlab-com@redhat.com> Merged-by: CKI GitLab Kmaint Pipeline Bot <26919896-cki-kmaint-pipeline-bot@users.noreply.gitlab.com>
2 parents bb3f889 + 310e31b commit 039d7c3

16 files changed

+323
-132
lines changed

‎MAINTAINERS‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11647,6 +11647,7 @@ F: include/uapi/drm/armada_drm.h
1164711647

1164811648
MARVELL CRYPTO DRIVER
1164911649
M: Srujana Challa <schalla@marvell.com>
11650+
M: Bharat Bhushan <bbhushan2@marvell.com>
1165011651
L: linux-crypto@vger.kernel.org
1165111652
S: Maintained
1165211653
F: drivers/crypto/marvell/

‎drivers/crypto/marvell/Kconfig‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ config CRYPTO_DEV_OCTEONTX_CPT
2424
tristate "Support for Marvell OcteonTX CPT driver"
2525
depends on ARCH_THUNDER || COMPILE_TEST
2626
depends on PCI_MSI && 64BIT
27-
depends on CRYPTO_LIB_AES
27+
select CRYPTO_LIB_AES
2828
select CRYPTO_SKCIPHER
2929
select CRYPTO_HASH
3030
select CRYPTO_AEAD
@@ -40,10 +40,10 @@ config CRYPTO_DEV_OCTEONTX2_CPT
4040
tristate "Marvell OcteonTX2 CPT driver"
4141
depends on ARCH_THUNDER2 || COMPILE_TEST
4242
depends on PCI_MSI && 64BIT
43-
depends on CRYPTO_LIB_AES
4443
depends on NET_VENDOR_MARVELL
4544
select OCTEONTX2_MBOX
4645
select CRYPTO_DEV_MARVELL
46+
select CRYPTO_LIB_AES
4747
select CRYPTO_SKCIPHER
4848
select CRYPTO_HASH
4949
select CRYPTO_AEAD

‎drivers/crypto/marvell/octeontx2/cn10k_cpt.c‎

Lines changed: 66 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
#include "otx2_cptvf.h"
77
#include "otx2_cptlf.h"
88
#include "cn10k_cpt.h"
9+
#include "otx2_cpt_common.h"
910

1011
static void cn10k_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, u32 insts_num,
1112
struct otx2_cptlf_info *lf);
@@ -27,7 +28,7 @@ static struct cpt_hw_ops cn10k_hw_ops = {
2728
static void cn10k_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, u32 insts_num,
2829
struct otx2_cptlf_info *lf)
2930
{
30-
void __iomem *lmtline = lf->lmtline;
31+
void *lmtline = lf->lfs->lmt_info.base + (lf->slot * LMTLINE_SIZE);
3132
u64 val = (lf->slot & 0x7FF);
3233
u64 tar_addr = 0;
3334

@@ -41,34 +42,69 @@ static void cn10k_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, u32 insts_num,
4142
dma_wmb();
4243

4344
/* Copy CPT command to LMTLINE */
44-
memcpy_toio(lmtline, cptinst, insts_num * OTX2_CPT_INST_SIZE);
45+
memcpy(lmtline, cptinst, insts_num * OTX2_CPT_INST_SIZE);
4546
cn10k_lmt_flush(val, tar_addr);
4647
}
4748

49+
void cn10k_cpt_lmtst_free(struct pci_dev *pdev, struct otx2_cptlfs_info *lfs)
50+
{
51+
struct otx2_lmt_info *lmt_info = &lfs->lmt_info;
52+
53+
if (!lmt_info->base)
54+
return;
55+
56+
dma_free_attrs(&pdev->dev, lmt_info->size,
57+
lmt_info->base - lmt_info->align,
58+
lmt_info->iova - lmt_info->align,
59+
DMA_ATTR_FORCE_CONTIGUOUS);
60+
}
61+
EXPORT_SYMBOL_NS_GPL(cn10k_cpt_lmtst_free, CRYPTO_DEV_OCTEONTX2_CPT);
62+
63+
static int cn10k_cpt_lmtst_alloc(struct pci_dev *pdev,
64+
struct otx2_cptlfs_info *lfs, u32 size)
65+
{
66+
struct otx2_lmt_info *lmt_info = &lfs->lmt_info;
67+
dma_addr_t align_iova;
68+
dma_addr_t iova;
69+
70+
lmt_info->base = dma_alloc_attrs(&pdev->dev, size, &iova, GFP_KERNEL,
71+
DMA_ATTR_FORCE_CONTIGUOUS);
72+
if (!lmt_info->base)
73+
return -ENOMEM;
74+
75+
align_iova = ALIGN((u64)iova, LMTLINE_ALIGN);
76+
lmt_info->iova = align_iova;
77+
lmt_info->align = align_iova - iova;
78+
lmt_info->size = size;
79+
lmt_info->base += lmt_info->align;
80+
return 0;
81+
}
82+
4883
int cn10k_cptpf_lmtst_init(struct otx2_cptpf_dev *cptpf)
4984
{
5085
struct pci_dev *pdev = cptpf->pdev;
51-
resource_size_t size;
52-
u64 lmt_base;
86+
u32 size;
87+
int ret;
5388

5489
if (!test_bit(CN10K_LMTST, &cptpf->cap_flag)) {
5590
cptpf->lfs.ops = &otx2_hw_ops;
5691
return 0;
5792
}
5893

5994
cptpf->lfs.ops = &cn10k_hw_ops;
60-
lmt_base = readq(cptpf->reg_base + RVU_PF_LMTLINE_ADDR);
61-
if (!lmt_base) {
62-
dev_err(&pdev->dev, "PF LMTLINE address not configured\n");
63-
return -ENOMEM;
95+
size = OTX2_CPT_MAX_VFS_NUM * LMTLINE_SIZE + LMTLINE_ALIGN;
96+
ret = cn10k_cpt_lmtst_alloc(pdev, &cptpf->lfs, size);
97+
if (ret) {
98+
dev_err(&pdev->dev, "PF-%d LMTLINE memory allocation failed\n",
99+
cptpf->pf_id);
100+
return ret;
64101
}
65-
size = pci_resource_len(pdev, PCI_MBOX_BAR_NUM);
66-
size -= ((1 + cptpf->max_vfs) * MBOX_SIZE);
67-
cptpf->lfs.lmt_base = devm_ioremap_wc(&pdev->dev, lmt_base, size);
68-
if (!cptpf->lfs.lmt_base) {
69-
dev_err(&pdev->dev,
70-
"Mapping of PF LMTLINE address failed\n");
71-
return -ENOMEM;
102+
103+
ret = otx2_cpt_lmtst_tbl_setup_msg(&cptpf->lfs);
104+
if (ret) {
105+
dev_err(&pdev->dev, "PF-%d: LMTST Table setup failed\n",
106+
cptpf->pf_id);
107+
cn10k_cpt_lmtst_free(pdev, &cptpf->lfs);
72108
}
73109

74110
return 0;
@@ -78,18 +114,25 @@ EXPORT_SYMBOL_NS_GPL(cn10k_cptpf_lmtst_init, CRYPTO_DEV_OCTEONTX2_CPT);
78114
int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf)
79115
{
80116
struct pci_dev *pdev = cptvf->pdev;
81-
resource_size_t offset, size;
117+
u32 size;
118+
int ret;
82119

83120
if (!test_bit(CN10K_LMTST, &cptvf->cap_flag))
84121
return 0;
85122

86-
offset = pci_resource_start(pdev, PCI_MBOX_BAR_NUM);
87-
size = pci_resource_len(pdev, PCI_MBOX_BAR_NUM);
88-
/* Map VF LMILINE region */
89-
cptvf->lfs.lmt_base = devm_ioremap_wc(&pdev->dev, offset, size);
90-
if (!cptvf->lfs.lmt_base) {
91-
dev_err(&pdev->dev, "Unable to map BAR4\n");
92-
return -ENOMEM;
123+
size = cptvf->lfs.lfs_num * LMTLINE_SIZE + LMTLINE_ALIGN;
124+
ret = cn10k_cpt_lmtst_alloc(pdev, &cptvf->lfs, size);
125+
if (ret) {
126+
dev_err(&pdev->dev, "VF-%d LMTLINE memory allocation failed\n",
127+
cptvf->vf_id);
128+
return ret;
129+
}
130+
131+
ret = otx2_cpt_lmtst_tbl_setup_msg(&cptvf->lfs);
132+
if (ret) {
133+
dev_err(&pdev->dev, "VF-%d: LMTST Table setup failed\n",
134+
cptvf->vf_id);
135+
cn10k_cpt_lmtst_free(pdev, &cptvf->lfs);
93136
}
94137

95138
return 0;

‎drivers/crypto/marvell/octeontx2/cn10k_cpt.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,7 @@ static inline u8 otx2_cpt_get_uc_compcode(union otx2_cpt_res_s *result)
5050

5151
int cn10k_cptpf_lmtst_init(struct otx2_cptpf_dev *cptpf);
5252
int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf);
53+
void cn10k_cpt_lmtst_free(struct pci_dev *pdev, struct otx2_cptlfs_info *lfs);
5354
void cn10k_cpt_ctx_flush(struct pci_dev *pdev, u64 cptr, bool inval);
5455
int cn10k_cpt_hw_ctx_init(struct pci_dev *pdev,
5556
struct cn10k_cpt_errata_ctx *er_ctx);

‎drivers/crypto/marvell/octeontx2/otx2_cpt_common.h‎

Lines changed: 11 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -145,11 +145,8 @@ static inline u64 otx2_cpt_read64(void __iomem *reg_base, u64 blk, u64 slot,
145145

146146
static inline bool is_dev_otx2(struct pci_dev *pdev)
147147
{
148-
if (pdev->device == OTX2_CPT_PCI_PF_DEVICE_ID ||
149-
pdev->device == OTX2_CPT_PCI_VF_DEVICE_ID)
150-
return true;
151-
152-
return false;
148+
return pdev->device == OTX2_CPT_PCI_PF_DEVICE_ID ||
149+
pdev->device == OTX2_CPT_PCI_VF_DEVICE_ID;
153150
}
154151

155152
static inline bool is_dev_cn10ka(struct pci_dev *pdev)
@@ -159,12 +156,10 @@ static inline bool is_dev_cn10ka(struct pci_dev *pdev)
159156

160157
static inline bool is_dev_cn10ka_ax(struct pci_dev *pdev)
161158
{
162-
if (pdev->subsystem_device == CPT_PCI_SUBSYS_DEVID_CN10K_A &&
163-
((pdev->revision & 0xFF) == 4 || (pdev->revision & 0xFF) == 0x50 ||
164-
(pdev->revision & 0xff) == 0x51))
165-
return true;
166-
167-
return false;
159+
return pdev->subsystem_device == CPT_PCI_SUBSYS_DEVID_CN10K_A &&
160+
((pdev->revision & 0xFF) == 4 ||
161+
(pdev->revision & 0xFF) == 0x50 ||
162+
(pdev->revision & 0xFF) == 0x51);
168163
}
169164

170165
static inline bool is_dev_cn10kb(struct pci_dev *pdev)
@@ -174,11 +169,8 @@ static inline bool is_dev_cn10kb(struct pci_dev *pdev)
174169

175170
static inline bool is_dev_cn10ka_b0(struct pci_dev *pdev)
176171
{
177-
if (pdev->subsystem_device == CPT_PCI_SUBSYS_DEVID_CN10K_A &&
178-
(pdev->revision & 0xFF) == 0x54)
179-
return true;
180-
181-
return false;
172+
return pdev->subsystem_device == CPT_PCI_SUBSYS_DEVID_CN10K_A &&
173+
(pdev->revision & 0xFF) == 0x54;
182174
}
183175

184176
static inline void otx2_cpt_set_hw_caps(struct pci_dev *pdev,
@@ -192,18 +184,12 @@ static inline void otx2_cpt_set_hw_caps(struct pci_dev *pdev,
192184

193185
static inline bool cpt_is_errata_38550_exists(struct pci_dev *pdev)
194186
{
195-
if (is_dev_otx2(pdev) || is_dev_cn10ka_ax(pdev))
196-
return true;
197-
198-
return false;
187+
return is_dev_otx2(pdev) || is_dev_cn10ka_ax(pdev);
199188
}
200189

201190
static inline bool cpt_feature_sgv2(struct pci_dev *pdev)
202191
{
203-
if (!is_dev_otx2(pdev) && !is_dev_cn10ka_ax(pdev))
204-
return true;
205-
206-
return false;
192+
return !is_dev_otx2(pdev) && !is_dev_cn10ka_ax(pdev);
207193
}
208194

209195
int otx2_cpt_send_ready_msg(struct otx2_mbox *mbox, struct pci_dev *pdev);
@@ -223,5 +209,6 @@ int otx2_cpt_detach_rsrcs_msg(struct otx2_cptlfs_info *lfs);
223209
int otx2_cpt_msix_offset_msg(struct otx2_cptlfs_info *lfs);
224210
int otx2_cpt_sync_mbox_msg(struct otx2_mbox *mbox);
225211
int otx2_cpt_lf_reset_msg(struct otx2_cptlfs_info *lfs, int slot);
212+
int otx2_cpt_lmtst_tbl_setup_msg(struct otx2_cptlfs_info *lfs);
226213

227214
#endif /* __OTX2_CPT_COMMON_H */

‎drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -255,3 +255,28 @@ int otx2_cpt_lf_reset_msg(struct otx2_cptlfs_info *lfs, int slot)
255255
return ret;
256256
}
257257
EXPORT_SYMBOL_NS_GPL(otx2_cpt_lf_reset_msg, CRYPTO_DEV_OCTEONTX2_CPT);
258+
259+
int otx2_cpt_lmtst_tbl_setup_msg(struct otx2_cptlfs_info *lfs)
260+
{
261+
struct otx2_mbox *mbox = lfs->mbox;
262+
struct pci_dev *pdev = lfs->pdev;
263+
struct lmtst_tbl_setup_req *req;
264+
265+
req = (struct lmtst_tbl_setup_req *)
266+
otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
267+
sizeof(struct msg_rsp));
268+
if (!req) {
269+
dev_err(&pdev->dev, "RVU MBOX failed to alloc message.\n");
270+
return -EFAULT;
271+
}
272+
273+
req->hdr.id = MBOX_MSG_LMTST_TBL_SETUP;
274+
req->hdr.sig = OTX2_MBOX_REQ_SIG;
275+
req->hdr.pcifunc = 0;
276+
277+
req->use_local_lmt_region = true;
278+
req->lmt_iova = lfs->lmt_info.iova;
279+
280+
return otx2_cpt_send_mbox_msg(mbox, pdev);
281+
}
282+
EXPORT_SYMBOL_NS_GPL(otx2_cpt_lmtst_tbl_setup_msg, CRYPTO_DEV_OCTEONTX2_CPT);

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