[P1] Generate DFG.png by default for kernels

[tancheng]

Hi @HobbitQia, can you help to make the fir/histogram/bicg/relu by default generate .dot and .png?

dataflow/test/e2e/fir/fir_kernel.mlir

Lines 6 to 18 in 4f815fc

	// RUN: mlir-neura-opt %t-kernel.mlir \
	// RUN: --assign-accelerator \
	// RUN: --lower-llvm-to-neura \
	// RUN: --promote-func-arg-to-const \
	// RUN: --fold-constant \
	// RUN: --canonicalize-live-in \
	// RUN: --leverage-predicated-value \
	// RUN: --transform-ctrl-to-data-flow \
	// RUN: --fold-constant \
	// RUN: --insert-data-mov \
	// RUN: --map-to-accelerator="mapping-strategy=heuristic" \
	// RUN: --architecture-spec=../../arch_spec/architecture.yaml \
	// RUN: --generate-code -o %t-mapping.mlir

Thanks~!

[HobbitQia]

Attachments are their DFGs. Since current PR is pending, I cannot push my new commits to my repo so I just generated images and attached them here.

Besides, I found that the version of clang will influence the final results. My local clang version is 14.0, leading to failed running of tests in e2e folder. Only clang-12 can pass the tests so I changed my version:D

[tancheng]

Thanks @HobbitQia, you can create another branch locally to make a PR for this, right? I believe it is a simple fix, we need this ASAP actually.

[tancheng]

Hi @HobbitQia, @syifan created a fancy web GUI for CGRA-Flow: https://cgra-flow-ui-git-refactor-interface-tab-0853ae-syifans-projects.vercel.app/login

However, the dfg is shown now as:

(format is fine though it is not neat) My concern is the DFG we generate is based on a middle level of neura IR, which is not close to the simulated instructions.

So, can we generate two .dot, one is before doing neura optimization, e.g., just the mlir.llvm dot (so then users understand what the application look like):

dataflow/test/e2e/fir/fir_kernel.mlir

Line 163 in 75b6fbc

// RUN: mlir-neura-opt %t-kernel.mlir \

another one is the exact neura IR level after mapping (so then user understand what happens after mapping):

dataflow/test/e2e/fir/fir_kernel.mlir

Line 23 in 75b6fbc

// MAPPING: func.func @_Z6kernelPiS_S_(%arg0: !llvm.ptr {llvm.nocapture, llvm.noundef, llvm.readonly}, %arg1: !llvm.ptr {llvm.nocapture, llvm.noundef, llvm.readnone}, %arg2: !llvm.ptr {llvm.nocapture, llvm.noundef, llvm.readonly}) -> (i32 {llvm.noundef}) attributes {CConv = #llvm.cconv<ccc>, accelerator = "neura", dataflow_mode = "predicate", linkage = #llvm.linkage<external>, mapping_info = {compiled_ii = 5 : i32, mapping_mode = "spatial-temporal", mapping_strategy = "heuristic", rec_mii = 5 : i32, res_mii = 2 : i32, x_tiles = 4 : i32, y_tiles = 4 : i32}, memory_effects = #llvm.memory_effects<other = none, argMem = read, inaccessibleMem = none>, no_unwind, passthrough = ["mustprogress", "nofree", "norecurse", "nosync", ["uwtable", "2"], ["min-legal-vector-width", "0"], ["no-trapping-math", "true"], ["stack-protector-buffer-size", "8"], ["target-cpu", "x86-64"]], target_cpu = "x86-64", target_features = #llvm.target_features<["+cmov", "+cx8", "+fxsr", "+mmx", "+sse", "+sse2", "+x87"]>, tune_cpu = "generic", unnamed_addr = 1 : i64, visibility_ = 0 : i64, will_return} {

Can you plz help modify the e2e kernels lit commands https://github.com/coredac/dataflow/tree/main/test/e2e?