[P1] A memory hierarchy estimator for data array partition/mapping

[ShangkunLi]

We need to integrate a memory hierarchy estimator for single-CGRA/multi-CGRA for array partition/mapping.

Goal

1. A Memory Hierarchy Estimator
   This simulator takes the mapping result of a single kernel as input and estimates the extra latency brought by the memory hierarchy.

The estimator should be able to support the following memory hierarchy:

• SRAM
• Cache
• Configurable Shard Memory (SRAM + Cache)

2. A Multi-CGRA Scheduler for A Single Kernel
   Based on the estimation, we are able to determine the optimal array partition/schedule method of this single kernel on a multi-CGRA system. For example, equally distributing the whole fir kernel on a multi-CGRA system would explore more parallelism than deploying it on a single CGRA.

[tancheng]

equally distributing the whole fir kernel on a multi-CGRA system would explore more parallelism than deploying it on a single CGRA

What do you mean by "equally distributing the whole fir"?

Also, it seems you need a performance estimator instead of a simulator?

[ShangkunLi]

equally distributing the whole fir kernel on a multi-CGRA system would explore more parallelism than deploying it on a single CGRA

What do you mean by "equally distributing the whole fir"?

For example, if the array that a fir kernel accessed is too large (e.g., NTAPS=2048), this may exceed the SRAM/Cache/ShardMem size of a single CGRA. We can partition it into different CGRAs and get the sum of each CGRA's partial result.

void kernel(float input[], float output[], float coefficient[])
/*   input :           input sample array */
/*   output:           output sample array */
/*   coefficient:      coefficient array */
{
  int i;
  float sum = 0.0;
  #pragma clang loop unroll_count(4) vectorize_width(4)
  for (i = 0; i < NTAPS; ++i) {
    sum += input[i] * coefficient[i];
  }
  output[0] = sum;
}

Also, it seems you need a performance estimator instead of a simulator?

Correct.