diff --git a/docs/projects/ad4630_fmc/ad463x_hdl_cm0_cz1_1.svg b/docs/projects/ad4630_fmc/ad463x_hdl_cm0_cz1_1.svg
index cbaf0e184d9..ad22c2ca259 100644
--- a/docs/projects/ad4630_fmc/ad463x_hdl_cm0_cz1_1.svg
+++ b/docs/projects/ad4630_fmc/ad463x_hdl_cm0_cz1_1.svg
@@ -1,13 +1,13 @@
diff --git a/docs/projects/ad4630_fmc/ad463x_hdl_cm0_cz1_no_reorder.svg b/docs/projects/ad4630_fmc/ad463x_hdl_cm0_cz1_no_reorder.svg
index 7492e8cb49e..431aace6279 100644
--- a/docs/projects/ad4630_fmc/ad463x_hdl_cm0_cz1_no_reorder.svg
+++ b/docs/projects/ad4630_fmc/ad463x_hdl_cm0_cz1_no_reorder.svg
@@ -1,13 +1,13 @@
diff --git a/docs/projects/ad4630_fmc/ad463x_hdl_cm0_cz2_1.svg b/docs/projects/ad4630_fmc/ad463x_hdl_cm0_cz2_1.svg
index 6e689309e32..d3755516eea 100644
--- a/docs/projects/ad4630_fmc/ad463x_hdl_cm0_cz2_1.svg
+++ b/docs/projects/ad4630_fmc/ad463x_hdl_cm0_cz2_1.svg
@@ -1,13 +1,13 @@
-
-
-
+ inkscape:stockid="TriangleOutM"
+ viewBox="0 0 4.2595265 4.9243081"
+ markerWidth="4.2595263"
+ markerHeight="4.9243078"
+ preserveAspectRatio="xMidYMid">
+
+
+
+ style="display:inline;opacity:1;fill:#000000;fill-opacity:0;fill-rule:nonzero;stroke:#000000;stroke-width:1.51069;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:0;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" />
+ style="display:inline;opacity:1;vector-effect:none;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:2.1981;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:0;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" />
AXI PWMGEN
-
- CNV
@@ -1771,15 +1763,15 @@
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path1206-1-0-95-1-7-7"
- d="M 685.12089,322.41327 H 534.11429"
+ d="M 685.12089,398.14977 H 534.11429"
style="display:inline;fill:none;stroke:#000000;stroke-width:2.18646;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#marker1216-0-3-1-2-9-5);shape-rendering:crispEdges;enable-background:new" />
REF_CLK
@@ -1787,13 +1779,13 @@
xml:space="preserve"
style="font-style:normal;font-weight:normal;font-size:11.6611px;line-height:1.25;font-family:sans-serif;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.874582"
x="594.99811"
- y="341.26895"
+ y="414.73434"
id="text1555"
transform="scale(0.97000757,1.0309198)">100MHz
ECHO SCLK
+
+
trigger
-
@@ -2294,5 +2291,72 @@
sodipodi:nodetypes="cc" />
+
+ GPIO
+ CNV
+ TRIGGER
+
+ OR
+
+
diff --git a/docs/projects/ad4630_fmc/ad463x_hdl_cm1_cz2_1.svg b/docs/projects/ad4630_fmc/ad463x_hdl_cm1_cz2_1.svg
index d1a6381600d..fe9ea24a31f 100644
--- a/docs/projects/ad4630_fmc/ad463x_hdl_cm1_cz2_1.svg
+++ b/docs/projects/ad4630_fmc/ad463x_hdl_cm1_cz2_1.svg
@@ -1,13 +1,13 @@
diff --git a/docs/projects/ad4630_fmc/index.rst b/docs/projects/ad4630_fmc/index.rst
index ef946c57752..c2e2dee529c 100644
--- a/docs/projects/ad4630_fmc/index.rst
+++ b/docs/projects/ad4630_fmc/index.rst
@@ -111,32 +111,42 @@ SPI mode - transfer zone 1
The main aspect of this mode is the fact that it is using the BUSY signal from
the ADC to trigger the Offload module. Data is then clocked out by the
-Execution module and transferred to the DMA by the Offload module. CNV is
-always generated by the AXI PWM GEN IP core regardless of the mode. Zone 1
-transfer is not currently supported by the pre-compiled HDL files that are
-included in the SD card image that is provided with the evaluation board.
+Execution module and transferred to the DMA by the Offload module. CNV is an "or"
+function of the AXI PWM GEN IP and the ad463x_trigger (EMIO) regardless of the
+mode. It is the software responsibility to configure the correct behavior for
+the trigger source. Zone 1 transfer is not currently supported by the
+pre-compiled HDL files that are included in the SD card image that is provided
+with the evaluation board.
.. image:: ad463x_hdl_cm0_cz1_1.svg
:width: 800
:align: center
:alt: AD4630_FMC SPI mode - transfer zone 1 block diagram
-For 1 SDI (:adi:`AD4030`) or 2 SDIs (:adi:`AD4630`) a special mode can be built,
-that bypasses the spi_axis_reorder IP and connects the SPI Engine Offload directly
-to DMA. For **other** number of SDIs this special mode **is not expected to work**.
+The DATA REORDER IP (spi_axis_reorder) is instantiated according to the
+combination of the NUM_OF_CHANNEL and LANES_PER_CHANNEL parameters. The
+following modes does not use the spi_axis_reorder IP and directly connects the
+SPI Engine Offload to the DMA:
+
+- 1 MISO/SDI (:adi:`AD4030`) - NUM_OF_CHANNEL = 1 LANES_PER_CHANNEL = 1;
+- 2 MISOs/SDIs (:adi:`AD4030`) - NUM_OF_CHANNEL = 1 LANES_PER_CHANNEL = 2;
+- 2 MISOs/SDIs (:adi:`AD4630`) - NUM_OF_CHANNEL = 2 LANES_PER_CHANNEL = 1.
+
+The last case may instantiate spi_axis_reorder IP if INTERLEAVE_MODE=1 is used.
.. image:: ad463x_hdl_cm0_cz1_no_reorder.svg
:width: 800
:align: center
:alt: AD4630_FMC SPI mode - transfer zone 1 block diagram without using the spi_axis_reorder IP
-
+
SPI mode - transfer zone 2
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-In this mode, the BUSY signal is not used and both the CNV and the Offload
-trigger signals are generated by the AXI PWM GEN core. The reason for using two
-PWM outputs instead of a common one is to accommodate for the averaging mode
-where the two signals will have different frequencies.
+In this mode, the BUSY signal is not used. Offload trigger is generated by the AXI
+PWM GEN core. CNV is still generated by the "or" function of the AXI PWM GEN and the
+ad463x_trigger (EMIO). The reason for using two PWM outputs instead of a common one
+is to accommodate for the averaging mode where the two signals will have different
+frequencies.
.. image:: ad463x_hdl_cm0_cz2_1.svg
:width: 800
@@ -153,9 +163,11 @@ Echo clock mode - transfer zone 2
In this configuration, the ADC's BUSY-SCKOUT pin functions as a bit-clock
output and is generated by looping-through the host’s SCK. The SPI engine is
-driving the SPI signals except it is no longer reading the data. For this
-purpose, the Data Capture IP is used. This also allows for reading data in DDR
-mode.
+driving the SPI signals except it is no longer reading the data. In echo clock
+mode, data reading reading is done by a dedicated Data Capture IP that is
+configured to capture data either in SDR or DDR mode.
+Again, CNV is generated by the "or" function of the AXI PWM GEN and the
+ad463x_trigger (EMIO).
.. image:: ad463x_hdl_cm1_cz2_1.svg
:width: 800
@@ -167,14 +179,32 @@ mode.
:align: center
:alt: ADAQ4224_FMC Echo clock mode - transfer zone 2 block diagram
-The design supports the following interface and clock modes both in SDR and DDR:
+The design supports the following modes:
+
+.. list-table::
+ :header-rows: 1
-================== ================== ================== ==================
-Mode 1 Lane per channel 2 Lane per channel 4 lane per channel
-================== ================== ================== ==================
-SPI mode yes yes yes
-Echo Clock mode yes yes yes
-================== ================== ================== ==================
+ * - Mode
+ - 1 Lane per channel
+ - 2 Lanes per channel
+ - 4 Lanes per channel
+ - Interleave
+ - SDR
+ - DDR
+ * - SPI mode
+ - yes
+ - yes
+ - yes
+ - yes
+ - yes
+ - no
+ * - Echo Clock mode
+ - yes
+ - yes
+ - yes
+ - yes
+ - yes
+ - yes
Configuration modes
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -182,16 +212,20 @@ Configuration modes
The CLK_MODE configuration parameter defines clocking mode of the device's
digital interface:
-- 0 - SPI mode
-- 1 - Echo-clock or Master clock mode
+- 0 - SPI mode;
+- 1 - Echo-clock or Master clock mode.
+
+The NUM_OF_CHANNEL configuration parameter defines the number of ADC channels:
+
+- 1 - AD403x devices;
+- 2 - AD463x/adaq42xx devices (default).
-The NUM_OF_SDI configuration parameter defines the number of MOSI lines of the
-SPI interface:
+The LANES_PER_CHANNEL configuration parameter defines the number of MISO lanes
+per channel of the SPI interface:
-- 1 - Interleaved mode
-- 2 - 1 lane per channel,
-- 4 - 2 lanes per channel
-- 8 - 4 lanes per channel
+- 1 - 1 lane per channel: Interleaved mode or single lane per channel;
+- 2 - 2 lanes per channel;
+- 4 - 4 lanes per channel (default).
The CAPTURE_ZONE configuration parameter defines the capture zone of the next
sample. There are two capture zones:
@@ -206,12 +240,13 @@ and master clock mode the SDI lines can have Single or Double Data Rates:
- 0 - MISO runs on SDR
- 1 - MISO runs on DDR.
-The ``NO_REORDER`` configuration parameter removes the spi_axis_reorder IP from
-the system for CAPTURE_ZONE = 1 and NUM_OF_SDI = 1 (AD4030) or NUM_OF_SDI = 2
-(AD4630) and directly connects the SPI Engine to DMA:
+The INTERLEAVE_MODE configuration parameter defines whether the interleaved
+mode is enabled or disabled. Interleaved mode can be only used for
+NUM_OF_CHANNEL = 2 and LANES_PER_CHANNEL = 1 (ad463x). Enabling INTERLEAVE_MODE
+for any other configuration is invalid.
-- 0 - spi_axis_reorder present (default)
-- 1 - spi_axis_reorder removed
+- 0 - interleave mode disabled, each channel has their own MISO lanes. (default);
+- 1 - interleave mode enabled, the ad463x ADC share the same MISO lanes.
CPU/Memory interconnects addresses
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -318,6 +353,10 @@ The Software GPIO number is calculated as follows:
- INOUT
- 35
- 89
+ * - ad463x_trigger
+ - OUT
+ - 36
+ - 90
.. admonition:: Legend
:class: note
@@ -360,11 +399,11 @@ by the configuration used:
if the following command was run
-``make NUM_OF_SDI=4 CAPTURE_ZONE=2``
+``make NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=4 CAPTURE_ZONE=2``
then the folder name will be:
-``NUMOFSDI4_CAPTUREZONE2``
+``NUMOFCHANNEL2_NUMOFSDI4_CAPTUREZONE2``
A more comprehensive build guide can be found in the :ref:`build_hdl` user guide.
diff --git a/projects/ad4630_fmc/common/ad463x_bd.tcl b/projects/ad4630_fmc/common/ad463x_bd.tcl
index 0be531bfbc3..e25ba1537b7 100644
--- a/projects/ad4630_fmc/common/ad463x_bd.tcl
+++ b/projects/ad4630_fmc/common/ad463x_bd.tcl
@@ -5,13 +5,32 @@
source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
# system level parameters
-set NUM_OF_SDI $ad_project_params(NUM_OF_SDI)
-set CAPTURE_ZONE $ad_project_params(CAPTURE_ZONE)
-set CLK_MODE $ad_project_params(CLK_MODE)
-set DDR_EN $ad_project_params(DDR_EN)
-set NO_REORDER $ad_project_params(NO_REORDER)
+set LANES_PER_CHANNEL $ad_project_params(LANES_PER_CHANNEL)
+set NUM_OF_CHANNEL $ad_project_params(NUM_OF_CHANNEL)
+set CAPTURE_ZONE $ad_project_params(CAPTURE_ZONE)
+set CLK_MODE $ad_project_params(CLK_MODE)
+set DDR_EN $ad_project_params(DDR_EN)
+set INTERLEAVE_MODE $ad_project_params(INTERLEAVE_MODE)
+
+if {$INTERLEAVE_MODE == 1} {
+ if {$LANES_PER_CHANNEL != 1 || $NUM_OF_CHANNEL != 2} {
+ puts "ERROR: Interleave mode is only supported with 2 channels (NUM_OF_CHANNEL == 2) and 1 lane per channel (LANES_PER_CHANNEL == 1)."
+ exit 2
+ }
+ set NUM_OF_SDI 1
+ # REORDER is mandatory in interleaved mode
+ set NO_REORDER 0
+} else {
+ set NUM_OF_SDI [expr {$ad_project_params(NUM_OF_CHANNEL) * $ad_project_params(LANES_PER_CHANNEL)}]
+ if {$NUM_OF_SDI > 2} {
+ # REORDER is mandatory when more than 2 lanes are used
+ set NO_REORDER 0
+ } else {
+ set NO_REORDER 1
+ }
+}
-puts "build parameters: NUM_OF_SDI: $NUM_OF_SDI ; CAPTURE_ZONE: $CAPTURE_ZONE ; CLK_MODE: $CLK_MODE ; DDR_EN: $DDR_EN ; NO_REORDER: $NO_REORDER"
+puts "build parameters: NUM_OF_SDI: $NUM_OF_SDI ; CAPTURE_ZONE: $CAPTURE_ZONE ; CLK_MODE: $CLK_MODE ; DDR_EN: $DDR_EN ; INTERLEAVE_MODE: $INTERLEAVE_MODE"
# block design ports and interfaces
# specify the CNV generator's reference clock frequency in MHz
@@ -36,6 +55,7 @@ create_bd_port -dir I ad463x_echo_sclk
create_bd_port -dir I ad463x_busy
create_bd_port -dir O ad463x_cnv
+create_bd_port -dir I ad463x_trigger
create_bd_port -dir I ad463x_ext_clk
create_bd_port -dir O max17687_sync_clk
@@ -77,7 +97,7 @@ ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_axi_regmap CONFIG.CFG_INFO_3
set sampling_cycle [expr int(ceil(double($cnv_ref_clk * 1000000) / $adc_sampling_rate))]
## setup the pulse period for the MAX17687 and LT8608 SYNC signal
-set max17687_cycle [expr int(ceil(double($cnv_ref_clk * 1000000) / $max17687_sync_freq))]
+set max17687_cycle [expr int(ceil(double($cnv_ref_clk * 1000000) / $max17687_sync_freq))]
ad_ip_instance axi_pwm_gen cnv_generator
ad_ip_parameter cnv_generator CONFIG.N_PWMS 2
@@ -93,17 +113,8 @@ ad_ip_parameter sync_generator CONFIG.PULSE_0_PERIOD $max17687_cycle
ad_ip_parameter sync_generator CONFIG.PULSE_0_WIDTH [expr int(ceil(double($max17687_cycle) / 2))]
if {$NO_REORDER == 0} {
-
ad_ip_instance spi_axis_reorder data_reorder
ad_ip_parameter data_reorder CONFIG.NUM_OF_LANES $NUM_OF_SDI
-
-} elseif {$NO_REORDER == 1} {
-
- if {$CAPTURE_ZONE == 2} {
- puts "ERROR: Invalid configuration - Disabling Reorder IP is invalid for Capture Zone 2."
- exit 2
- }
-
}
# dma to receive data stream
@@ -116,19 +127,23 @@ ad_ip_parameter axi_ad463x_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_ad463x_dma CONFIG.AXI_SLICE_SRC 1
if {$NO_REORDER == 0} {
ad_ip_parameter axi_ad463x_dma CONFIG.DMA_DATA_WIDTH_SRC 64
-} elseif {$NO_REORDER == 1} {
- if {$NUM_OF_SDI == 1} {
- ad_ip_parameter axi_ad463x_dma CONFIG.DMA_DATA_WIDTH_SRC 32
- } elseif {$NUM_OF_SDI == 2} {
- ad_ip_parameter axi_ad463x_dma CONFIG.DMA_DATA_WIDTH_SRC 64
- }
+} else {
+ #REORDER BYPASSED
+ ad_ip_parameter axi_ad463x_dma CONFIG.DMA_DATA_WIDTH_SRC [expr min(32 * $NUM_OF_SDI, 64)]
}
-
+
ad_ip_parameter axi_ad463x_dma CONFIG.DMA_DATA_WIDTH_DEST 64
+# or logic for CNV generation
+ad_ip_instance ilvector_logic or_logic_cnv
+ad_ip_parameter or_logic_cnv CONFIG.C_SIZE 1
+ad_ip_parameter or_logic_cnv CONFIG.C_OPERATION or
+
+ad_connect cnv_generator/pwm_1 or_logic_cnv/Op1
+ad_connect ad463x_trigger or_logic_cnv/Op2
+
# Trigger for SPI offload
if {$CAPTURE_ZONE == 1} {
-
## SPI mode is using the echo SCLK, on echo SPI and Master mode the BUSY
# is used for SDI latching
switch $CLK_MODE {
@@ -137,7 +152,7 @@ if {$CAPTURE_ZONE == 1} {
}
1 -
2 {
- puts "ERROR: Invalid configuration option. CAPTURE_ZONE 1 can be used only in SPI mode (CLK_MODE == 1)."
+ puts "ERROR: Invalid configuration option. CAPTURE_ZONE 1 can be used only in SPI mode (CLK_MODE == 0)."
exit 2
}
default {
@@ -159,6 +174,7 @@ if {$CAPTURE_ZONE == 1} {
ad_connect ad463x_busy busy_sync/in_bits
ad_connect busy_sync/out_bits busy_capture/signal_in
ad_connect $hier_spi_engine/trigger busy_capture/signal_out
+
## SDI is latched by the SPIE execution module
if {$NO_REORDER == 0} {
ad_connect $hier_spi_engine/m_axis_sample data_reorder/s_axis
@@ -167,7 +183,6 @@ if {$CAPTURE_ZONE == 1} {
}
} elseif {$CAPTURE_ZONE == 2} {
-
# Zone 2 - trigger to next consecutive CNV
ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_offload CONFIG.ASYNC_TRIG 1
ad_connect cnv_generator/pwm_0 $hier_spi_engine/trigger
@@ -179,7 +194,11 @@ if {$CAPTURE_ZONE == 1} {
switch $CLK_MODE {
0 {
## SDI is latched by the SPIE execution module
- ad_connect $hier_spi_engine/m_axis_sample data_reorder/s_axis
+ if {$NO_REORDER == 0} {
+ ad_connect $hier_spi_engine/m_axis_sample data_reorder/s_axis
+ } else {
+ ad_connect $hier_spi_engine/m_axis_sample axi_ad463x_dma/s_axis
+ }
}
1 -
2 {
@@ -193,8 +212,12 @@ if {$CAPTURE_ZONE == 1} {
ad_connect ad463x_busy data_capture/echo_sclk
ad_connect ad463x_spi_sdi data_capture/data_in
- ad_connect data_capture/m_axis data_reorder/s_axis
-
+ ## SDI is latched by the SPIE execution module
+ if {$NO_REORDER == 0} {
+ ad_connect data_capture/m_axis data_reorder/s_axis
+ } else {
+ ad_connect data_capture/m_axis axi_ad463x_dma/s_axis
+ }
}
default {
puts "ERROR: Invalid value for CLK_MODE (valid values are 0 or 1 or 2)."
@@ -203,12 +226,11 @@ if {$CAPTURE_ZONE == 1} {
}
} else {
-
puts "ERROR: Invalid capture zone, please choose 1 or 2."
exit 2
-
}
-ad_connect ad463x_cnv cnv_generator/pwm_1
+
+ad_connect ad463x_cnv or_logic_cnv/Res
ad_connect max17687_sync_clk sync_generator/pwm_0
# clocks
diff --git a/projects/ad4630_fmc/zed/Makefile b/projects/ad4630_fmc/zed/Makefile
index 8f0b0a9fdc9..7506d13987f 100644
--- a/projects/ad4630_fmc/zed/Makefile
+++ b/projects/ad4630_fmc/zed/Makefile
@@ -1,15 +1,19 @@
####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2025 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := ad4630_fmc_zed
-M_DEPS += system_constr_8sdi.xdc
-M_DEPS += system_constr_4sdi.xdc
-M_DEPS += system_constr_2sdi.xdc
-M_DEPS += system_constr_1sdi.xdc
+M_DEPS += system_constr_1sdi_1ch.xdc
+M_DEPS += system_constr_1sdi_2ch_interleave.xdc
+M_DEPS += system_constr_2sdi_1ch.xdc
+M_DEPS += system_constr_2sdi_2ch.xdc
+M_DEPS += system_constr_4sdi_1ch.xdc
+M_DEPS += system_constr_4sdi_2ch.xdc
+M_DEPS += system_constr_8sdi_2ch.xdc
+
M_DEPS += ../common/ad463x_bd.tcl
M_DEPS += ../../scripts/adi_pd.tcl
M_DEPS += ../../common/zed/zed_system_constr.xdc
diff --git a/projects/ad4630_fmc/zed/README.md b/projects/ad4630_fmc/zed/README.md
index 5ab446ca646..bda78f151ff 100644
--- a/projects/ad4630_fmc/zed/README.md
+++ b/projects/ad4630_fmc/zed/README.md
@@ -24,43 +24,44 @@ need to be changed, as well as the Linux project configurations:
The overwritable parameters from the environment are:
- CLK_MODE: clocking mode of the device's digital interface
- - 0 - SPI (default)
- - 1 - Echo-clock or Master clock
-- NUM_OF_SDI: the number of MISO lines of the SPI interface
- - 1 - Interleaved
- - 2 - 1LPC
- - 4 - 2LPC (default)
- - 8 - 4LPC
+ - 0 - SPI (default);
+ - 1 - Echo-clock or Master clock;
+- NUM_OF_CHANNEL: the number of ADC channels
+ - 1 - AD403x devices;
+ - 2 - AD463x/adaq42xx devices (default).
+- LANES_PER_CHANNEL: the number of MISO lanes of the SPI interface per channel
+ - 1 - 1 lane per channel: Interleaved mode or single lane per channel;
+ - 2 - 2 lanes per channel;
+ - 4 - 4 lanes per channel (default).
- CAPTURE_ZONE: the capture zone of the next sample
- - 1 - negative edge of BUSY
- - 2 - next positive edge of CNV (default)
-- DDR_EN: in echo and master clock mode, the SDI lines can have Single or Double data rates
- - 0 - MISO runs on SDR (default)
- - 1 - MISO runs on DDR
-- NO_REORDER: removes the spi_axis_reorder from system for CAPTURE_ZONE = 1 and
- NUM_OF_SDI = 1 (AD4030) or NUM_OF_SDI = 2 (AD4630) and directly connects the SPI
- Engine to DMA
- - 0 - spi_axis_reorder present (default)
- - 1 - spi_axis_reorder removed
+ - 1 - negative edge of BUSY;
+ - 2 - next positive edge of CNV (default);
+- DDR_EN: in echo or master clock mode, the MISO lanes can have Single or Double data rates
+ - 0 - MISO runs on SDR (default);
+ - 1 - MISO runs on DDR;
+- INTERLEAVE_MODE: parameter used for NUM_OF_CHANNEL = 2 and LANES_PER_CHANNEL = 1 (ad463x).
+ Enabling INTERLEAVE_MODE for any other configuration is invalid.
+ - 0 - interleave mode disabled, each channel has their own MISO lanes. (default);
+ - 1 - interleave mode enabled, the ad463x ADC share the same MISO lanes.
### Example configurations
-#### Clock mode SPI, MISO lines 4, Capture zone 2, SDR (default)
+#### Clock mode SPI, 2 channels, MISO lanes 4 (2 per channel), Capture zone 2, SDR (default)
This specific command is equivalent to running `make` only:
```
-make CLK_MODE=0 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0
+make CLK_MODE=0 NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=2 CAPTURE_ZONE=2 DDR_EN=0
```
Corresponding device trees:
- [zynq-zed-adv7511-ad4630-24.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4630-24.dts)
- [zynq-zed-adv7511-ad4630-16.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4630-16.dts)
-#### Clock mode SPI, MISO lines 2, Capture zone 2, SDR
+#### Clock mode SPI, 1 channel, MISO lane 1, Capture zone 2, SDR
```
-make CLK_MODE=0 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0
+make CLK_MODE=0 NUM_OF_CHANNEL=1 LANES_PER_CHANNEL=1 CAPTURE_ZONE=2 DDR_EN=0
```
Corresponding device trees:
@@ -71,62 +72,120 @@ Corresponding device trees:
- [zynq-zed-adv7511-adaq4220.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4220.dts)
- [zynq-zed-adv7511-adaq4224-24.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4224-24.dts)
-#### Clock mode SPI, MISO lines 4, Capture zone 2, SDR
+#### 1-Channel options
+#### Clock mode SPI, 1 channel, MISO lane 1, Capture zone 2, SDR
```
-make CLK_MODE=0 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0
+make CLK_MODE=0 NUM_OF_CHANNEL=1 LANES_PER_CHANNEL=1 CAPTURE_ZONE=2 DDR_EN=0
```
-#### Clock mode SPI, MISO lines 8, Capture zone 2, SDR
+#### Clock mode SPI, 1 channel, MISO lanes 2, Capture zone 2, SDR
```
-make CLK_MODE=0 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0
+make CLK_MODE=0 NUM_OF_CHANNEL=1 LANES_PER_CHANNEL=2 CAPTURE_ZONE=2 DDR_EN=0
```
-#### Clock mode ECHO, MISO lines 2, Capture zone 2, SDR
+#### Clock mode SPI, 1 channel, MISO lanes 4, Capture zone 2, SDR
```
-make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0
+make CLK_MODE=0 NUM_OF_CHANNEL=1 LANES_PER_CHANNEL=4 CAPTURE_ZONE=2 DDR_EN=0
```
-#### Clock mode ECHO, MISO lines 4, Capture zone 2, SDR
+#### Clock mode Echo, 1 channel, MISO lane 1, Capture zone 2, SDR
```
-make CLK_MODE=1 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0
+make CLK_MODE=1 NUM_OF_CHANNEL=1 LANES_PER_CHANNEL=1 CAPTURE_ZONE=2 DDR_EN=0
```
-#### Clock mode ECHO, MISO lines 8, Capture zone 2, SDR
+#### Clock mode Echo, 1 channel, MISO lanes 2, Capture zone 2, SDR
```
-make CLK_MODE=1 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0
+make CLK_MODE=1 NUM_OF_CHANNEL=1 LANES_PER_CHANNEL=2 CAPTURE_ZONE=2 DDR_EN=0
```
-#### Clock mode ECHO, MISO lines 2, Capture zone 2, DDR
+#### Clock mode Echo, 1 channel, MISO lanes 4, Capture zone 2, SDR
```
-make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=1 NO_REORDER=0
+make CLK_MODE=1 NUM_OF_CHANNEL=1 LANES_PER_CHANNEL=4 CAPTURE_ZONE=2 DDR_EN=0
```
-#### Clock mode ECHO, MISO lines 4, Capture zone 2, DDR
+#### Clock mode Echo, 1 channel, MISO lane 1, Capture zone 2, DDR
```
-make CLK_MODE=1 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=1 NO_REORDER=0
+make CLK_MODE=1 NUM_OF_CHANNEL=1 LANES_PER_CHANNEL=1 CAPTURE_ZONE=2 DDR_EN=1
```
-#### Clock mode ECHO, MISO lines 8, Capture zone 2, DDR
+#### Clock mode Echo, 1 channel, MISO lanes 2, Capture zone 2, DDR
```
-make CLK_MODE=1 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=1 NO_REORDER=0
+make CLK_MODE=1 NUM_OF_CHANNEL=1 LANES_PER_CHANNEL=2 CAPTURE_ZONE=2 DDR_EN=1
```
-#### Clock mode SPI, MISO lines 1, Capture zone 1, SDR (AD4030)
+#### Clock mode Echo, 1 channel, MISO lanes 4, Capture zone 2, DDR
```
-make CLK_MODE=0 NUM_OF_SDI=1 CAPTURE_ZONE=1 DDR_EN=0 NO_REORDER=1
+make CLK_MODE=1 NUM_OF_CHANNEL=1 LANES_PER_CHANNEL=4 CAPTURE_ZONE=2 DDR_EN=1
```
-#### Clock mode SPI, MISO lines 2, Capture zone 1, SDR (AD4630)
+#### 2-Channel options
+#### Clock mode SPI, 2 channels, MISO lanes 2 (1 per channel), Capture zone 2, SDR
```
-make CLK_MODE=0 NUM_OF_SDI=2 CAPTURE_ZONE=1 DDR_EN=0 NO_REORDER=1
+make CLK_MODE=0 NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=1 CAPTURE_ZONE=2 DDR_EN=0
```
+
+#### Clock mode SPI, 2 channels, MISO lanes 4 (2 per channel), Capture zone 2, SDR
+
+```
+make CLK_MODE=0 NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=2 CAPTURE_ZONE=2 DDR_EN=0
+```
+
+#### Clock mode SPI, 2 channels, MISO lanes 8 (4 per channel), Capture zone 2, SDR
+
+```
+make CLK_MODE=0 NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=4 CAPTURE_ZONE=2 DDR_EN=0
+```
+
+#### Clock mode Echo, 2 channels, MISO lanes 2 (1 per channel), Capture zone 2, SDR
+
+```
+make CLK_MODE=1 NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=1 CAPTURE_ZONE=2 DDR_EN=0
+```
+
+#### Clock mode Echo, 2 channels, MISO lanes 4 (2 per channel), Capture zone 2, SDR
+
+```
+make CLK_MODE=1 NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=2 CAPTURE_ZONE=2 DDR_EN=0
+```
+
+#### Clock mode Echo, 2 channels, MISO lanes 8 (4 per channel), Capture zone 2, SDR
+
+```
+make CLK_MODE=1 NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=4 CAPTURE_ZONE=2 DDR_EN=0
+```
+
+#### Clock mode Echo, 2 channels, MISO lanes 2 (1 per channel), Capture zone 2, DDR
+
+```
+make CLK_MODE=1 NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=1 CAPTURE_ZONE=2 DDR_EN=1
+```
+
+#### Clock mode Echo, 2 channels, MISO lanes 4 (2 per channel), Capture zone 2, DDR
+
+```
+make CLK_MODE=1 NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=2 CAPTURE_ZONE=2 DDR_EN=1
+```
+
+#### Clock mode Echo, 2 channels, MISO lanes 8 (4 per channel), Capture zone 2, DDR
+
+```
+make CLK_MODE=1 NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=4 CAPTURE_ZONE=2 DDR_EN=1
+```
+
+#### Unsupported options
+
+Any combination of NUM_OF_CHANNEL=1 and INTERLEAVE_MODE=1. It makes no sense to interleave the data of a single channel.
+
+Any combination of LANES_PER_CHANNEL > 1 and INTERLEAVE_MODE=1. It is necessary a single MISO lane for interleaving.
+
+Any combination of CLK_MODE=0 and DDR_EN=1. The DDR mode is available only valid for echo clock and host clock modes - see MODES REGISTER specification.
\ No newline at end of file
diff --git a/projects/ad4630_fmc/zed/system_bd.tcl b/projects/ad4630_fmc/zed/system_bd.tcl
index a2bfc589676..5b01af53fbb 100644
--- a/projects/ad4630_fmc/zed/system_bd.tcl
+++ b/projects/ad4630_fmc/zed/system_bd.tcl
@@ -20,9 +20,10 @@ ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
set sys_cstring "CLK_MODE=$ad_project_params(CLK_MODE)\
-NUM_OF_SDI=$ad_project_params(NUM_OF_SDI)\
+LANES_PER_CHANNEL=$ad_project_params(LANES_PER_CHANNEL)\
+NUM_OF_CHANNEL=$ad_project_params(NUM_OF_CHANNEL)\
CAPTURE_ZONE=$ad_project_params(CAPTURE_ZONE)\
DDR_EN=$ad_project_params(DDR_EN)\
-NO_REORDER=$ad_project_params(NO_REORDER)"
+INTERLEAVE_MODE=$ad_project_params(INTERLEAVE_MODE)"
sysid_gen_sys_init_file $sys_cstring
diff --git a/projects/ad4630_fmc/zed/system_constr.xdc b/projects/ad4630_fmc/zed/system_constr.xdc
index 1a2dae34580..71743b8bd71 100644
--- a/projects/ad4630_fmc/zed/system_constr.xdc
+++ b/projects/ad4630_fmc/zed/system_constr.xdc
@@ -1,25 +1,25 @@
###############################################################################
-## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ad463x_fmc SPI interface
-set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_spi_sdo] ; ## C11 FMC_LA06_N
-set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_spi_sclk] ; ## G6 FMC_LA00_CC_P
-set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_cs] ; ## G7 FMC_LA00_CC_N
-
-set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports ad463x_echo_sclk] ; ## D20 FMC_LA17_CC_P
-set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports ad463x_resetn] ; ## D9 FMC_LA01_CC_N
-set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports ad463x_busy] ; ## C22 FMC_LA18_CC_P
-set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad463x_cnv] ; ## D8 FMC_LA01_CC_P
-set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports ad463x_ext_clk] ; ## H4 FMC_CLK0_P
-
-set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports {adaq42xx_pgia_mux[0]}] ; ## G12 FMC-LA08_P
-set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports {adaq42xx_pgia_mux[1]}] ; ## G13 FMC-LA08_N
-
-set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports max17687_rst] ; ## H13 FMC-LA07_P
-set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports max17687_en] ; ## H14 FMC-LA07_N
-set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports max17687_sync_clk] ; ## D21 FMC-LA17_N_CC
+set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_spi_sdo] ; ## C11 FMC_LPC_LA06_N
+set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_spi_sclk] ; ## G6 FMC_LPC_LA00_CC_P
+set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_cs] ; ## G7 FMC_LPC_LA00_CC_N
+
+set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports ad463x_echo_sclk] ; ## D20 FMC_LPC_LA17_CC_P
+set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports ad463x_resetn] ; ## D9 FMC_LPC_LA01_CC_N
+set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports ad463x_busy] ; ## C22 FMC_LPC_LA18_CC_P
+set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad463x_cnv] ; ## D8 FMC_LPC_LA01_CC_P
+set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports ad463x_ext_clk] ; ## H4 FMC_LPC_CLK0_P
+
+set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports {adaq42xx_pgia_mux[0]}] ; ## G12 FMC_LPC_LA08_P
+set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports {adaq42xx_pgia_mux[1]}] ; ## G13 FMC_LPC_LA08_N
+
+set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports max17687_rst] ; ## H13 FMC_LPC_LA07_P
+set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports max17687_en] ; ## H14 FMC_LPC_LA07_N
+set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports max17687_sync_clk] ; ## D21 FMC_LPC_LA17_N_CC
# external clock, that drives the CNV generator, must have a maximum 100 MHz frequency
create_clock -period 10.000 -name cnv_ext_clk [get_ports ad463x_ext_clk]
diff --git a/projects/ad4630_fmc/zed/system_constr_1sdi.xdc b/projects/ad4630_fmc/zed/system_constr_1sdi_1ch.xdc
similarity index 67%
rename from projects/ad4630_fmc/zed/system_constr_1sdi.xdc
rename to projects/ad4630_fmc/zed/system_constr_1sdi_1ch.xdc
index ff30f115886..0531097ef14 100644
--- a/projects/ad4630_fmc/zed/system_constr_1sdi.xdc
+++ b/projects/ad4630_fmc/zed/system_constr_1sdi_1ch.xdc
@@ -1,14 +1,16 @@
###############################################################################
-## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
-set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi] ; ## H07 FMC_LPC_LA02_P
+# Constraints for 1 SDI, 1 Channel configuration
# input delays for MISO lines (SDO for the device)
# data is latched on negative edge
set tsetup 5.6
set thold 1.4
-set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi]
-set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi]
+set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[0]] ; ## H07 FMC_LPC_LA02_P
+
+set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[0]]
+set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[0]]
diff --git a/projects/ad4630_fmc/zed/system_constr_1sdi_2ch_interleave.xdc b/projects/ad4630_fmc/zed/system_constr_1sdi_2ch_interleave.xdc
new file mode 100644
index 00000000000..a7675265904
--- /dev/null
+++ b/projects/ad4630_fmc/zed/system_constr_1sdi_2ch_interleave.xdc
@@ -0,0 +1,17 @@
+###############################################################################
+## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+# Constraints for 1 SDI, 2 Channels configuration without reorder (NO_REORDER=1)
+# This results in only 1 SDI line total
+# input delays for MISO lines (SDO for the device)
+# data is latched on negative edge
+
+set tsetup 5.6
+set thold 1.4
+
+set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] ; ## H07 FMC_LPC_LA02_P
+
+set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[0]}]
+set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[0]}]
diff --git a/projects/ad4630_fmc/zed/system_constr_2sdi.xdc b/projects/ad4630_fmc/zed/system_constr_2sdi_1ch.xdc
similarity index 73%
rename from projects/ad4630_fmc/zed/system_constr_2sdi.xdc
rename to projects/ad4630_fmc/zed/system_constr_2sdi_1ch.xdc
index 179c562f7f4..b5dbe7105b9 100644
--- a/projects/ad4630_fmc/zed/system_constr_2sdi.xdc
+++ b/projects/ad4630_fmc/zed/system_constr_2sdi_1ch.xdc
@@ -1,17 +1,18 @@
###############################################################################
-## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
-set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[0]] ; ## H07 FMC_LPC_LA02_P
-set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[1]] ; ## H10 FMC_LPC_LA04_P
-
+# Constraints for 2 SDI, 1 Channel configuration
# input delays for MISO lines (SDO for the device)
# data is latched on negative edge
set tsetup 5.6
set thold 1.4
+set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] ; ## H07 FMC_LPC_LA02_P
+set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}] ; ## H08 FMC_LPC_LA02_N
+
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[0]]
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[0]]
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[1]]
diff --git a/projects/ad4630_fmc/zed/system_constr_2sdi_2ch.xdc b/projects/ad4630_fmc/zed/system_constr_2sdi_2ch.xdc
new file mode 100644
index 00000000000..d1342aa104f
--- /dev/null
+++ b/projects/ad4630_fmc/zed/system_constr_2sdi_2ch.xdc
@@ -0,0 +1,20 @@
+###############################################################################
+## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+# Constraints for 1 SDI per channel, 2 Channels configuration with reorder (NO_REORDER=0)
+# This results in 2 SDI lines total
+# input delays for MISO lines (SDO for the device)
+# data is latched on negative edge
+
+set tsetup 5.6
+set thold 1.4
+
+set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] ; ## H07 FMC_LPC_LA02_P
+set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}] ; ## H10 FMC_LPC_LA04_P
+
+set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[0]}]
+set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[0]}]
+set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[1]}]
+set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[1]}]
diff --git a/projects/ad4630_fmc/zed/system_constr_4sdi_1ch.xdc b/projects/ad4630_fmc/zed/system_constr_4sdi_1ch.xdc
new file mode 100644
index 00000000000..d7486a705a4
--- /dev/null
+++ b/projects/ad4630_fmc/zed/system_constr_4sdi_1ch.xdc
@@ -0,0 +1,25 @@
+###############################################################################
+## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+# Constraints for 4 SDI, 1 Channel configuration
+# input delays for MISO lines (SDO for the device)
+# data is latched on negative edge
+
+set tsetup 5.6
+set thold 1.6
+
+set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[0]] ; ## H07 FMC_LPC_LA02_P
+set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[1]] ; ## H08 FMC_LPC_LA02_N
+set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[2]] ; ## G09 FMC_LPC_LA03_P
+set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[3]] ; ## G10 FMC_LPC_LA03_N
+
+set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[0]]
+set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[0]]
+set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[1]]
+set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[1]]
+set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[2]]
+set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[2]]
+set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[3]]
+set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[3]]
diff --git a/projects/ad4630_fmc/zed/system_constr_4sdi.xdc b/projects/ad4630_fmc/zed/system_constr_4sdi_2ch.xdc
similarity index 79%
rename from projects/ad4630_fmc/zed/system_constr_4sdi.xdc
rename to projects/ad4630_fmc/zed/system_constr_4sdi_2ch.xdc
index 0aca6b40eab..35c81ab3ff9 100644
--- a/projects/ad4630_fmc/zed/system_constr_4sdi.xdc
+++ b/projects/ad4630_fmc/zed/system_constr_4sdi_2ch.xdc
@@ -1,19 +1,20 @@
###############################################################################
-## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
-set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] ; ## H07 FMC_LA02_P
-set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}] ; ## H08 FMC_LA02_N
-set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[2]}] ; ## H10 FMC_LA04_P
-set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[3]}] ; ## H11 FMC_LA04_N
-
+# Constraints for 2 SDI per channel, 2 Channels configuration (4 SDI lines total)
# input delays for MISO lines (SDO for the device)
# data is latched on negative edge
set tsetup 5.6
set thold 1.4
+set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] ; ## H07 FMC_LPC_LA02_P
+set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}] ; ## H08 FMC_LPC_LA02_N
+set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[2]}] ; ## H10 FMC_LPC_LA04_P
+set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[3]}] ; ## H11 FMC_LPC_LA04_N
+
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[0]}]
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports {ad463x_spi_sdi[0]}]
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports {ad463x_spi_sdi[1]}]
diff --git a/projects/ad4630_fmc/zed/system_constr_8sdi.xdc b/projects/ad4630_fmc/zed/system_constr_8sdi_2ch.xdc
similarity index 94%
rename from projects/ad4630_fmc/zed/system_constr_8sdi.xdc
rename to projects/ad4630_fmc/zed/system_constr_8sdi_2ch.xdc
index d8819d0e1eb..d709c5729a5 100644
--- a/projects/ad4630_fmc/zed/system_constr_8sdi.xdc
+++ b/projects/ad4630_fmc/zed/system_constr_8sdi_2ch.xdc
@@ -1,8 +1,15 @@
###############################################################################
-## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
+# Constraints for 4 SDI per channel, 2 Channels configuration (8 SDI lines total)
+# input delays for MISO lines (SDO for the device)
+# data is latched on negative edge
+
+set tsetup 5.6
+set thold 1.6
+
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[0]] ; ## H07 FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[1]] ; ## H08 FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[2]] ; ## G09 FMC_LPC_LA03_P
@@ -12,10 +19,6 @@ set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_s
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[6]] ; ## D11 FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[7]] ; ## D12 FMC_LPC_LA05_N
-set tsetup 5.6
-set thold 1.6
-
-# input delays for MISO lines (SDO for the device)
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[0]]
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -min $thold [get_ports ad463x_spi_sdi[0]]
set_input_delay -clock [get_clocks ECHOSCLK_clk] -clock_fall -max $tsetup [get_ports ad463x_spi_sdi[1]]
diff --git a/projects/ad4630_fmc/zed/system_project.tcl b/projects/ad4630_fmc/zed/system_project.tcl
index 45d56750e6c..6701e80a9f9 100644
--- a/projects/ad4630_fmc/zed/system_project.tcl
+++ b/projects/ad4630_fmc/zed/system_project.tcl
@@ -13,7 +13,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
# How to use over-writable parameters from the environment:
#
# e.g.
-# make NUM_OF_SDI=4 CAPTURE_ZONE=2
+# make LANES_PER_CHANNEL=4 CAPTURE_ZONE=2
#
#
# Parameter description:
@@ -23,12 +23,16 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
# 0 - SPI Mode
# 1 - Echo-clock or Master clock mode
#
-# NUM_OF_SDI : the number of MOSI lines of the SPI interface
+# NUM_OF_CHANNEL : the number of ADC channels
#
-# 1 - Interleaved mode
-# 2 - 1 lane per channel
-# 4 - 2 lanes per channel
-# 8 - 4 lanes per channel
+# 1 - AD403x devices
+# 2 - AD463x/adaq42xx devices
+#
+# LANES_PER_CHANNEL : the number of MOSI lines of the SPI interface
+#
+# 1 - 1 lane per channel: Interleaved mode or single lane per channel
+# 2 - 2 lanes per channel
+# 4 - 4 lanes per channel
#
# CAPTURE_ZONE : the capture zone of the next sample
# There are two capture zones for AD4624-30:
@@ -43,24 +47,24 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
# 0 - MISO runs on SDR
# 1 - MISO runs on DDR
#
-# NO_REORDER : Parameter used for CAPTURE_ZONE = 1 and NUM_OF_SDI = 1 (ad4030)
-# or NUM_OF_SDI = 2 (ad4630) to connect the SPI Engine directly to DMA bypassing
-# the spi_axis_reorder IP
+# INTERLEAVE_MODE: parameter used for NUM_OF_CHANNEL = 2 and LANES_PER_CHANNEL = 1 (ad463x).
+# Enabling INTERLEAVE_MODE for any other configuration is invalid.
#
-# 0 - spi_axis_reorder present in the system
-# 1 - spi_axis_reorder removed from the system
+# 0 - interleave mode disabled, each channel has its own SDI line
+# 1 - interleave mode enabled, the ad463x ADC share the same SDI line
#
# Example:
#
-# make NUM_OF_SDI=2 CAPTURE_ZONE=2
+# make CLK_MODE=0 NUM_OF_CHANNEL=2 LANES_PER_CHANNEL=4 CAPTURE_ZONE=2 DDR_EN=0 INTERLEAVE_MODE=0
#
adi_project ad4630_fmc_zed 0 [list \
- CLK_MODE [get_env_param CLK_MODE 0] \
- NUM_OF_SDI [get_env_param NUM_OF_SDI 4] \
- CAPTURE_ZONE [get_env_param CAPTURE_ZONE 2] \
- DDR_EN [get_env_param DDR_EN 0] \
- NO_REORDER [get_env_param NO_REORDER 0] ]
+ CLK_MODE [get_env_param CLK_MODE 0] \
+ LANES_PER_CHANNEL [get_env_param LANES_PER_CHANNEL 2] \
+ NUM_OF_CHANNEL [get_env_param NUM_OF_CHANNEL 2] \
+ CAPTURE_ZONE [get_env_param CAPTURE_ZONE 2] \
+ DDR_EN [get_env_param DDR_EN 0] \
+ INTERLEAVE_MODE [get_env_param INTERLEAVE_MODE 0] ]
adi_project_files ad4630_fmc_zed [list \
"$ad_hdl_dir/library/common/ad_iobuf.v" \
@@ -69,26 +73,53 @@ adi_project_files ad4630_fmc_zed [list \
"system_constr.xdc" \
"system_top.v" ]
-switch [get_env_param NUM_OF_SDI 4] {
+switch [get_env_param LANES_PER_CHANNEL 2] {
1 {
- adi_project_files ad4630_fmc_zed [list \
- "system_constr_1sdi.xdc" ]
+ # For 1 lane per channel, check NUM_OF_CHANNEL
+ if {[get_env_param NUM_OF_CHANNEL 2] == 1} {
+ # 1 channel, 1 SDI lane
+ adi_project_files ad4630_fmc_zed [list \
+ "system_constr_1sdi_1ch.xdc" ]
+ } else {
+ # 2 channels, check INTERLEAVE_MODE
+ if {[get_env_param INTERLEAVE_MODE 0] == 0} {
+ # INTERLEAVE_MODE=0: 2 SDI lanes (1 per channel)
+ adi_project_files ad4630_fmc_zed [list \
+ "system_constr_2sdi_2ch.xdc" ]
+ } else {
+ # INTERLEAVE_MODE=1: valid for AD463x only, both channels share the same SDI line
+ adi_project_files ad4630_fmc_zed [list \
+ "system_constr_1sdi_2ch_interleave.xdc" ]
+ }
+ }
}
2 {
- adi_project_files ad4630_fmc_zed [list \
- "system_constr_2sdi.xdc" ]
+ # For 2 lanes per channel, check NUM_OF_CHANNEL
+ if {[get_env_param NUM_OF_CHANNEL 2] == 1} {
+ # 1 channel, 2 SDI lanes
+ adi_project_files ad4630_fmc_zed [list \
+ "system_constr_2sdi_1ch.xdc" ]
+ } else {
+ # 2 channels, 4 SDI lanes (2 per channel)
+ adi_project_files ad4630_fmc_zed [list \
+ "system_constr_4sdi_2ch.xdc" ]
+ }
}
4 {
- adi_project_files ad4630_fmc_zed [list \
- "system_constr_4sdi.xdc" ]
- }
- 8 {
- adi_project_files ad4630_fmc_zed [list \
- "system_constr_8sdi.xdc" ]
+ # For 4 lanes per channel, check NUM_OF_CHANNEL
+ if {[get_env_param NUM_OF_CHANNEL 2] == 1} {
+ # 1 channel, 4 SDI lanes
+ adi_project_files ad4630_fmc_zed [list \
+ "system_constr_4sdi_1ch.xdc" ]
+ } else {
+ # 2 channels, 8 SDI lanes (4 per channel)
+ adi_project_files ad4630_fmc_zed [list \
+ "system_constr_8sdi_2ch.xdc" ]
+ }
}
default {
adi_project_files ad4630_fmc_zed [list \
- "system_constr_2sdi.xdc" ]
+ "system_constr_4sdi_2ch.xdc" ]
}
}
diff --git a/projects/ad4630_fmc/zed/system_top.v b/projects/ad4630_fmc/zed/system_top.v
index cf55b9eea60..d9d95116818 100644
--- a/projects/ad4630_fmc/zed/system_top.v
+++ b/projects/ad4630_fmc/zed/system_top.v
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
-// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -117,11 +117,13 @@ module system_top #(
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
wire ad463x_echo_sclk_s;
+ wire ad463x_trigger;
// instantiations
- assign gpio_i[63:36] = 27'b0;
- assign max17687_en = 1'b1;
+ assign gpio_i[63:37] = 26'b0;
+ assign max17687_en = 1'b1;
+ assign ad463x_trigger = gpio_o[36];
ad_data_clk #(
.SINGLE_ENDED (1)
@@ -243,6 +245,7 @@ module system_top #(
.ad463x_echo_sclk (ad463x_echo_sclk_s),
.ad463x_busy (ad463x_busy),
.ad463x_cnv (ad463x_cnv),
+ .ad463x_trigger (ad463x_trigger),
.ad463x_ext_clk (ext_clk_s),
.max17687_sync_clk (max17687_sync_clk),
.otg_vbusoc (otg_vbusoc),