Skip to content

Commit e8d6a2f

Browse files
caosjrcaosjr
committed
library/spi_engine: update spi lane mask instruction
There is a different register for SDI lane mask and SDO lane mask; Update the NUM_OF_SDI parameter to NUM_OF_SDIO parameter to reflect that both SDI and SDO are symmetrical. The control over them is through the SDI/SDO lane masks. Inserts a ready signal for when the valid_indices has finished its inner logic. This avoid the possible issue where the latency of the command is smaller than this logic. This could only happen in the FIFO mode. Signed-off-by: Carlos Souza <carlos.souza@analog.com>
1 parent 5a9529d commit e8d6a2f

19 files changed

+256
-218
lines changed

‎library/spi_engine/axi_spi_engine/axi_spi_engine.v‎

Lines changed: 11 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ module axi_spi_engine #(
4848
parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = 4,
4949
parameter ID = 0,
5050
parameter [15:0] DATA_WIDTH = 8,
51-
parameter [ 7:0] NUM_OF_SDI = 1,
51+
parameter [ 7:0] NUM_OF_SDIO = 1,
5252
parameter CFG_INFO_0 = 0,
5353
parameter CFG_INFO_1 = 0,
5454
parameter CFG_INFO_2 = 0,
@@ -110,7 +110,7 @@ module axi_spi_engine #(
110110

111111
output sdi_data_ready,
112112
input sdi_data_valid,
113-
input [(NUM_OF_SDI * DATA_WIDTH)-1:0] sdi_data,
113+
input [(NUM_OF_SDIO * DATA_WIDTH)-1:0] sdi_data,
114114

115115
output sync_ready,
116116
input sync_valid,
@@ -136,7 +136,7 @@ module axi_spi_engine #(
136136
localparam PCORE_VERSION = 'h010600;
137137
localparam S_AXI = 0;
138138
localparam UP_FIFO = 1;
139-
localparam max_num_of_reads = NUM_OF_SDI-1;
139+
localparam max_num_of_reads = NUM_OF_SDIO-1;
140140

141141
wire clk;
142142
wire rstn;
@@ -158,15 +158,16 @@ module axi_spi_engine #(
158158
wire sdo_fifo_in_valid;
159159

160160
wire [31:0] sdi_fifo_level;
161-
reg [NUM_OF_SDI*DATA_WIDTH/8-1:0] sdi_fifo_tkeep_int;
162-
wire [NUM_OF_SDI*DATA_WIDTH/8-1:0] sdi_fifo_tkeep;
161+
reg [NUM_OF_SDIO*DATA_WIDTH/8-1:0] sdi_fifo_tkeep_int;
162+
wire [NUM_OF_SDIO*DATA_WIDTH/8-1:0] sdi_fifo_tkeep;
163163
wire sdi_fifo_almost_full;
164164
wire up_sdi_fifo_almost_full;
165165

166166
wire [DATA_WIDTH-1:0] sdi_fifo_out_data;
167167
wire sdi_fifo_out_ready;
168168
reg find_next_valid_fifo_value;
169169
wire sdi_fifo_out_valid;
170+
reg [3:0] sdi_out_counter;
170171

171172
wire [7:0] sync_fifo_data;
172173
wire sync_fifo_valid;
@@ -331,7 +332,7 @@ module axi_spi_engine #(
331332
8'h00: up_rdata_ff <= PCORE_VERSION;
332333
8'h01: up_rdata_ff <= ID;
333334
8'h02: up_rdata_ff <= up_scratch;
334-
8'h03: up_rdata_ff <= {8'b0, NUM_OF_SDI, DATA_WIDTH};
335+
8'h03: up_rdata_ff <= {8'b0, NUM_OF_SDIO, DATA_WIDTH};
335336
8'h04: up_rdata_ff <= {16'b0, offload_sdo_mem_address_width, offload_cmd_mem_address_width};
336337
8'h05: up_rdata_ff <= {sdi_fifo_address_width, sdo_fifo_address_width, sync_fifo_address_width, cmd_fifo_address_width};
337338
8'h10: up_rdata_ff <= up_sw_reset;
@@ -435,7 +436,7 @@ module axi_spi_engine #(
435436
assign sdo_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h39;
436437
assign sdo_fifo_in_data = up_wdata_s[DATA_WIDTH-1:0];
437438

438-
util_axis_fifo #(
439+
util_axis_fifo #(
439440
.DATA_WIDTH(DATA_WIDTH),
440441
.ASYNC_CLK(ASYNC_SPI_CLK),
441442
.ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH),
@@ -469,10 +470,10 @@ module axi_spi_engine #(
469470
integer i;
470471
always @(posedge spi_clk) begin
471472
if (!spi_resetn) begin
472-
sdi_fifo_tkeep_int <= {(NUM_OF_SDI*DATA_WIDTH/8){1'b1}};
473+
sdi_fifo_tkeep_int <= {(NUM_OF_SDIO*DATA_WIDTH/8){1'b1}};
473474
end else begin
474475
if (cmd_valid && cmd_data[15:8] == 8'h23) begin
475-
for (i = 0; i < NUM_OF_SDI; i = i + 1) begin
476+
for (i = 0; i < NUM_OF_SDIO; i = i + 1) begin
476477
sdi_fifo_tkeep_int[i*DATA_WIDTH/8+:DATA_WIDTH/8] <= {DATA_WIDTH/8{cmd_data[i]}};
477478
end
478479
end
@@ -482,7 +483,7 @@ module axi_spi_engine #(
482483

483484
util_axis_fifo_asym #(
484485
.ASYNC_CLK(ASYNC_SPI_CLK),
485-
.S_DATA_WIDTH(NUM_OF_SDI * DATA_WIDTH),
486+
.S_DATA_WIDTH(NUM_OF_SDIO * DATA_WIDTH),
486487
.M_DATA_WIDTH(DATA_WIDTH),
487488
.ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH),
488489
.M_AXIS_REGISTERED(0),
@@ -502,7 +503,6 @@ module axi_spi_engine #(
502503
.s_axis_tkeep(sdi_fifo_tkeep),
503504
.s_axis_full(),
504505
.s_axis_almost_full(sdi_fifo_almost_full),
505-
506506
.m_axis_aclk(clk),
507507
.m_axis_aresetn(up_sw_resetn),
508508
.m_axis_ready(sdi_fifo_out_ready || find_next_valid_fifo_value),
@@ -516,8 +516,6 @@ module axi_spi_engine #(
516516

517517
assign sdi_fifo_out_ready = up_rreq_s == 1'b1 && up_raddr_s == 8'h3a;
518518

519-
reg [3:0] sdi_out_counter;
520-
reg find_next_valid_fifo_value;
521519
always @(posedge clk) begin
522520
if (rstn == 1'b0) begin
523521
up_rack_ff <= 'd0;

‎library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -33,15 +33,15 @@ ad_ip_parameter OFFLOAD0_CMD_MEM_ADDRESS_WIDTH INTEGER 4
3333
ad_ip_parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH INTEGER 4
3434
ad_ip_parameter ID INTEGER 0
3535
ad_ip_parameter DATA_WIDTH INTEGER 8
36-
ad_ip_parameter NUM_OF_SDI INTEGER 1
36+
ad_ip_parameter NUM_OF_SDIO INTEGER 1
3737

3838
proc p_elaboration {} {
3939

4040
# read parameters
4141

4242
set mm_if_type [get_parameter_value "MM_IF_TYPE"]
4343

44-
set num_of_sdi [get_parameter_value NUM_OF_SDI]
44+
set num_of_sdi [get_parameter_value NUM_OF_SDIO]
4545
set data_width [get_parameter_value DATA_WIDTH]
4646

4747
# interrupt

‎library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -195,13 +195,13 @@ set_property -dict [list \
195195
] \
196196
[ipx::get_user_parameters DATA_WIDTH -of_objects $cc]
197197

198-
## NUM_OF_SDI
198+
## NUM_OF_SDIO
199199
set_property -dict [list \
200200
"value_validation_type" "range_long" \
201201
"value_validation_range_minimum" "1" \
202202
"value_validation_range_maximum" "8" \
203203
] \
204-
[ipx::get_user_parameters NUM_OF_SDI -of_objects $cc]
204+
[ipx::get_user_parameters NUM_OF_SDIO -of_objects $cc]
205205

206206
## Customize IP Layout
207207

@@ -228,11 +228,11 @@ set_property -dict [list \
228228
"tooltip" "\[DATA_WIDTH\] Define the data interface width"
229229
] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component $cc]
230230

231-
ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group
231+
ipgui::add_param -name "NUM_OF_SDIO" -component $cc -parent $general_group
232232
set_property -dict [list \
233-
"display_name" "Number of MISO lines" \
234-
"tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \
235-
] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc]
233+
"display_name" "Number of MISO/MOSI lines" \
234+
"tooltip" "\[NUM_OF_SDIO\] Define the number of MISO/MOSI lines" \
235+
] [ipgui::get_guiparamspec -name "NUM_OF_SDIO" -component $cc]
236236

237237
ipgui::add_param -name "MM_IF_TYPE" -component $cc -parent $general_group
238238
set_property -dict [list \

‎library/spi_engine/axi_spi_engine/axi_spi_engine_ltt.tcl‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -115,11 +115,11 @@ set ip [ipl::set_parameter -ip $ip \
115115
-group1 {General Configuration} \
116116
-group2 Config]
117117
set ip [ipl::set_parameter -ip $ip \
118-
-id NUM_OF_SDI \
118+
-id NUM_OF_SDIO \
119119
-type param \
120120
-value_type int \
121121
-conn_mod axi_spi_engine \
122-
-title {Number of MISO lines} \
122+
-title {Number of MISO/MOSI lines} \
123123
-default 1 \
124124
-output_formatter nostr \
125125
-value_range {(1, 8)} \

‎library/spi_engine/scripts/spi_engine.tcl‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -33,15 +33,15 @@ proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {n
3333
ad_ip_instance spi_engine_execution $execution
3434
ad_ip_parameter $execution CONFIG.DATA_WIDTH $data_width
3535
ad_ip_parameter $execution CONFIG.NUM_OF_CS $num_cs
36-
ad_ip_parameter $execution CONFIG.NUM_OF_SDI $num_sdi
36+
ad_ip_parameter $execution CONFIG.NUM_OF_SDIO $num_sdi
3737
ad_ip_parameter $execution CONFIG.SDO_DEFAULT 1
3838
ad_ip_parameter $execution CONFIG.SDI_DELAY $sdi_delay
3939
ad_ip_parameter $execution CONFIG.ECHO_SCLK $echo_sclk
4040

4141
ad_ip_instance axi_spi_engine $axi_regmap
4242
ad_ip_parameter $axi_regmap CONFIG.DATA_WIDTH $data_width
4343
ad_ip_parameter $axi_regmap CONFIG.NUM_OFFLOAD 1
44-
ad_ip_parameter $axi_regmap CONFIG.NUM_OF_SDI $num_sdi
44+
ad_ip_parameter $axi_regmap CONFIG.NUM_OF_SDIO $num_sdi
4545
ad_ip_parameter $axi_regmap CONFIG.ASYNC_SPI_CLK $async_spi_clk
4646
ad_ip_parameter $axi_regmap CONFIG.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH $cmd_mem_addr_width
4747
ad_ip_parameter $axi_regmap CONFIG.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH $data_mem_addr_width
@@ -53,14 +53,14 @@ proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {n
5353
ad_ip_instance spi_engine_offload $offload
5454
ad_ip_parameter $offload CONFIG.DATA_WIDTH $data_width
5555
ad_ip_parameter $offload CONFIG.ASYNC_SPI_CLK 0
56-
ad_ip_parameter $offload CONFIG.NUM_OF_SDI $num_sdi
56+
ad_ip_parameter $offload CONFIG.NUM_OF_SDIO $num_sdi
5757
ad_ip_parameter $offload CONFIG.CMD_MEM_ADDRESS_WIDTH $cmd_mem_addr_width
5858
ad_ip_parameter $offload CONFIG.SDO_MEM_ADDRESS_WIDTH $data_mem_addr_width
5959
ad_ip_parameter $offload CONFIG.SDO_STREAMING $sdo_streaming
6060

6161
ad_ip_instance spi_engine_interconnect $interconnect
6262
ad_ip_parameter $interconnect CONFIG.DATA_WIDTH $data_width
63-
ad_ip_parameter $interconnect CONFIG.NUM_OF_SDI $num_sdi
63+
ad_ip_parameter $interconnect CONFIG.NUM_OF_SDIO $num_sdi
6464

6565
ad_connect $axi_regmap/spi_engine_offload_ctrl0 $offload/spi_engine_offload_ctrl
6666
ad_connect $offload/m_interconnect_ctrl $interconnect/s_interconnect_ctrl

‎library/spi_engine/spi_engine_execution/spi_engine_execution.v‎

Lines changed: 23 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@ module spi_engine_execution #(
4141
parameter DEFAULT_SPI_CFG = 0,
4242
parameter DEFAULT_CLK_DIV = 0,
4343
parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32
44-
parameter NUM_OF_SDI = 1,
44+
parameter NUM_OF_SDIO = 1,
4545
parameter [0:0] SDO_DEFAULT = 1'b0,
4646
parameter ECHO_SCLK = 0,
4747
parameter [1:0] SDI_DELAY = 2'b00
@@ -62,17 +62,17 @@ module spi_engine_execution #(
6262

6363
input sdi_data_ready,
6464
output sdi_data_valid,
65-
output [(NUM_OF_SDI * DATA_WIDTH)-1:0] sdi_data,
65+
output [(NUM_OF_SDIO * DATA_WIDTH)-1:0] sdi_data,
6666

6767
input sync_ready,
6868
output reg sync_valid,
6969
output [7:0] sync,
7070

7171
input echo_sclk,
7272
output reg sclk,
73-
output reg [NUM_OF_SDI-1:0] sdo,
73+
output reg [NUM_OF_SDIO-1:0] sdo,
7474
output reg sdo_t,
75-
input [NUM_OF_SDI-1:0] sdi,
75+
input [NUM_OF_SDIO-1:0] sdi,
7676
output reg [NUM_OF_CS-1:0] cs,
7777
output reg three_wire
7878
);
@@ -86,11 +86,12 @@ module spi_engine_execution #(
8686
localparam MISC_SYNC = 1'b0;
8787
localparam MISC_SLEEP = 1'b1;
8888

89-
localparam REG_CLK_DIV = 2'b00;
90-
localparam REG_CONFIG = 2'b01;
91-
localparam REG_WORD_LENGTH = 2'b10;
92-
localparam REG_SPI_LANE_CONFIG = 2'b11;
93-
localparam ALL_ACTIVE_LANE_MASK = (2 ** NUM_OF_SDI) - 1; //by default all lanes are enabled
89+
localparam REG_CLK_DIV = 3'b000;
90+
localparam REG_CONFIG = 3'b001;
91+
localparam REG_WORD_LENGTH = 3'b010;
92+
localparam REG_SDI_LANE_CONFIG = 3'b011;
93+
localparam REG_SDO_LANE_CONFIG = 3'b100;
94+
localparam ALL_ACTIVE_LANE_MASK = (2 ** NUM_OF_SDIO) - 1; //by default all lanes are enabled
9495

9596
localparam BIT_COUNTER_WIDTH = DATA_WIDTH > 16 ? 5 :
9697
DATA_WIDTH > 8 ? 4 : 3;
@@ -125,7 +126,7 @@ module spi_engine_execution #(
125126
reg [7:0] word_length = DATA_WIDTH;
126127
reg [7:0] last_bit_count = DATA_WIDTH-1;
127128
reg [7:0] left_aligned = 8'b0;
128-
reg [7:0] spi_lane_mask = ALL_ACTIVE_LANE_MASK;
129+
reg [7:0] sdo_lane_mask = ALL_ACTIVE_LANE_MASK;
129130

130131
reg cpha = DEFAULT_SPI_CFG[0];
131132
reg cpol = DEFAULT_SPI_CFG[1];
@@ -140,7 +141,7 @@ module spi_engine_execution #(
140141
wire sdo_enabled_io;
141142
wire sdi_enabled_io;
142143

143-
wire [NUM_OF_SDI-1:0] sdo_int_s;
144+
wire [NUM_OF_SDIO-1:0] sdo_int_s;
144145

145146
reg last_bit;
146147
wire echo_last_bit;
@@ -153,7 +154,6 @@ module spi_engine_execution #(
153154
wire exec_transfer_cmd = exec_cmd && inst == CMD_TRANSFER;
154155
wire exec_chipselect_cmd = exec_cmd && inst == CMD_CHIPSELECT;
155156
wire exec_write_cmd = exec_cmd && inst == CMD_WRITE;
156-
wire exec_lane_config_cmd = exec_write_cmd && cmd[9:8] == REG_SPI_LANE_CONFIG;
157157
wire exec_misc_cmd = exec_cmd && inst == CMD_MISC;
158158
wire exec_cs_inv_cmd = exec_cmd && inst == CMD_CS_INV;
159159
wire exec_sync_cmd = exec_misc_cmd && cmd[8] == MISC_SYNC;
@@ -165,7 +165,7 @@ module spi_engine_execution #(
165165
reg cmd_d1_sleep_instr;
166166
reg exec_transfer_cmd_reg = 1'b0; //avoid comparison in the shiftreg
167167
reg exec_write_cmd_reg = 1'b0; //avoid comparison in the shiftreg data assemble
168-
reg exec_lane_config_cmd_reg = 1'b0; //avoid comparison in the shiftreg data assemble
168+
reg exec_sdo_lane_config_reg = 1'b0; //avoid comparison in the shiftreg data assemble
169169
reg exec_chipselect_cmd_reg = 1'b0; //avoid comparison cs_gen
170170
reg cmd_d1_time_is_zero;
171171

@@ -189,12 +189,11 @@ module spi_engine_execution #(
189189
.DEFAULT_SPI_CFG(DEFAULT_SPI_CFG),
190190
.ALL_ACTIVE_LANE_MASK(ALL_ACTIVE_LANE_MASK),
191191
.DATA_WIDTH(DATA_WIDTH),
192-
.NUM_OF_SDI(NUM_OF_SDI),
192+
.NUM_OF_SDIO(NUM_OF_SDIO),
193193
.SDI_DELAY(SDI_DELAY),
194194
.ECHO_SCLK(ECHO_SCLK),
195195
.CMD_TRANSFER(CMD_TRANSFER),
196-
.CMD_WRITE(CMD_WRITE),
197-
.REG_SPI_LANE_CONFIG(REG_SPI_LANE_CONFIG)
196+
.CMD_WRITE(CMD_WRITE)
198197
) shiftreg (
199198
.clk(clk),
200199
.resetn(resetn),
@@ -212,11 +211,11 @@ module spi_engine_execution #(
212211
.sdi_enabled(sdi_enabled),
213212
.current_cmd(cmd_d1),
214213
.exec_cmd(exec_transfer_cmd_reg),
215-
.spi_lane_cmd(exec_lane_config_cmd_reg),
214+
.exec_sdo_lane_cmd(exec_sdo_lane_config_reg),
216215
.sdo_idle_state(sdo_idle_state),
217216
.left_aligned(left_aligned),
218217
.word_length(word_length),
219-
.spi_lane_mask(spi_lane_mask),
218+
.sdo_lane_mask(sdo_lane_mask),
220219
.sdo_io_ready(sdo_io_ready),
221220
.echo_last_bit(echo_last_bit),
222221
.transfer_active(transfer_active),
@@ -252,7 +251,7 @@ module spi_engine_execution #(
252251
exec_transfer_cmd_reg <= (inst == CMD_TRANSFER);
253252
exec_write_cmd_reg <= (inst == CMD_WRITE);
254253
exec_chipselect_cmd_reg <= (inst == CMD_CHIPSELECT);
255-
exec_lane_config_cmd_reg <= (inst == CMD_WRITE) && (cmd[9:8] == REG_SPI_LANE_CONFIG);
254+
exec_sdo_lane_config_reg <= (inst == CMD_WRITE) && (cmd[10:8] == REG_SDO_LANE_CONFIG);
256255
end else begin
257256
sleep_counter_compare <= sleep_counter == cmd_d1_time && clk_div_last && sleep_counter_increment;
258257
end
@@ -280,10 +279,10 @@ module spi_engine_execution #(
280279
clk_div <= DEFAULT_CLK_DIV;
281280
word_length <= DATA_WIDTH;
282281
left_aligned <= 0;
283-
spi_lane_mask <= ALL_ACTIVE_LANE_MASK;
282+
sdo_lane_mask <= ALL_ACTIVE_LANE_MASK;
284283
end else begin
285284
if (exec_write_cmd) begin
286-
case (cmd[9:8])
285+
case (cmd[10:8])
287286
REG_CLK_DIV : begin
288287
clk_div <= cmd[7:0];
289288
end
@@ -299,9 +298,9 @@ module spi_engine_execution #(
299298
// needed 1 cycle before transfer_active goes high
300299
left_aligned <= DATA_WIDTH - cmd[7:0];
301300
end
302-
REG_SPI_LANE_CONFIG : begin
301+
REG_SDO_LANE_CONFIG : begin
303302
//max number of spi lanes is 8
304-
spi_lane_mask <= cmd[7:0];
303+
sdo_lane_mask <= cmd[7:0];
305304
end
306305
endcase
307306
end
@@ -355,7 +354,7 @@ module spi_engine_execution #(
355354
end else begin
356355
first_bit <= ((bit_counter + ntx_rx == 0) || (bit_counter == word_length-1));
357356
last_bit <= (bit_counter == last_bit_count);
358-
357+
359358
if (clk_div_last && ~wait_for_io) begin
360359
if (last_bit && transfer_active && ntx_rx) begin
361360
bit_counter <= 0;

‎library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,14 +20,14 @@ ad_ip_parameter NUM_OF_CS INTEGER 1
2020
ad_ip_parameter DEFAULT_SPI_CFG INTEGER 0
2121
ad_ip_parameter DEFAULT_CLK_DIV INTEGER 0
2222
ad_ip_parameter DATA_WIDTH INTEGER 8
23-
ad_ip_parameter NUM_OF_SDI INTEGER 1
23+
ad_ip_parameter NUM_OF_SDIO INTEGER 1
2424
ad_ip_parameter SDI_DELAY INTEGER 0
2525
ad_ip_parameter SDO_DEFAULT INTEGER 0
2626

2727
proc p_elaboration {} {
2828

2929
set data_width [get_parameter_value DATA_WIDTH]
30-
set num_of_sdi [get_parameter_value NUM_OF_SDI]
30+
set num_of_sdi [get_parameter_value NUM_OF_SDIO]
3131
set num_of_cs [get_parameter_value NUM_OF_CS]
3232

3333
# clock and reset interface

0 commit comments

Comments
 (0)