library/spi_engine: Update for SDO extension

* Extend SDO support to 8 (symmetrical with SDI support);
* Update SDI to use asymmetrical FIFO;
* Insert symmetrical FIFO for the SDO;
* Insert SDI lane mask configuration instruction to reg 3'b011;
* Insert SDO lane mask configuration instruction to reg 3'b100;
* Insert offload active interface for interconnect and execution;
* Remove register 8'h3b from spi engine regmap;
* Improvements on the critical paths of the execution module.

Prefetching on offload work iff all lanes are active.

Signed-off-by: Carlos Souza <carlos.souza@analog.com>

Author: caosjr

library/spi_engine/axi_spi_engine/Makefile

@@ -20,6 +20,7 @@ XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl.xml
 XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
 
 XILINX_LIB_DEPS += util_axis_fifo
+XILINX_LIB_DEPS += util_axis_fifo_asym
 XILINX_LIB_DEPS += util_cdc
 
 XILINX_INTERFACE_DEPS += spi_engine/interfaces

library/spi_engine/axi_spi_engine/axi_spi_engine.v

@@ -106,11 +106,11 @@ module axi_spi_engine #(
 
   input sdo_data_ready,
   output sdo_data_valid,
-  output [(DATA_WIDTH-1):0] sdo_data,
+  output [(DATA_WIDTH)-1:0] sdo_data,
 
   output sdi_data_ready,
   input sdi_data_valid,
-  input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
+  input [(NUM_OF_SDI * DATA_WIDTH)-1:0] sdi_data,
 
   output sync_ready,
   input sync_valid,
@@ -122,7 +122,7 @@ module axi_spi_engine #(
   output [15:0] offload0_cmd_wr_data,
 
   output offload0_sdo_wr_en,
-  output [(DATA_WIDTH-1):0] offload0_sdo_wr_data,
+  output [(DATA_WIDTH)-1:0] offload0_sdo_wr_data,
 
   output offload0_mem_reset,
   output offload0_enable,
@@ -133,9 +133,10 @@ module axi_spi_engine #(
   input [7:0] offload_sync_data
 );
 
-  localparam PCORE_VERSION = 'h010501;
+  localparam PCORE_VERSION = 'h010600;
   localparam S_AXI = 0;
   localparam UP_FIFO = 1;
+  localparam max_num_of_reads = NUM_OF_SDI-1;
 
   wire clk;
   wire rstn;
@@ -152,17 +153,19 @@ module axi_spi_engine #(
   wire sdo_fifo_almost_empty;
   wire up_sdo_fifo_almost_empty;
 
-  wire [(DATA_WIDTH-1):0] sdo_fifo_in_data;
+  wire [DATA_WIDTH-1:0] sdo_fifo_in_data;
   wire sdo_fifo_in_ready;
   wire sdo_fifo_in_valid;
 
-  wire sdi_fifo_out_data_msb_s;
-  wire [SDI_FIFO_ADDRESS_WIDTH-1:0] sdi_fifo_level;
+  wire [31:0] sdi_fifo_level;
+  reg  [NUM_OF_SDI*DATA_WIDTH/8-1:0] sdi_fifo_tkeep_int;
+  wire [NUM_OF_SDI*DATA_WIDTH/8-1:0] sdi_fifo_tkeep;
   wire sdi_fifo_almost_full;
   wire up_sdi_fifo_almost_full;
 
-  wire [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_fifo_out_data;
+  wire [DATA_WIDTH-1:0] sdi_fifo_out_data;
   wire sdi_fifo_out_ready;
+  reg  find_next_valid_fifo_value;
   wire sdi_fifo_out_valid;
 
   wire [7:0] sync_fifo_data;
@@ -317,23 +320,6 @@ module axi_spi_engine #(
     end
   end
 
-  always @(posedge clk) begin
-    if (rstn == 1'b0) begin
-      up_rack_ff <= 'd0;
-    end else begin
-      up_rack_ff <= up_rreq_s;
-    end
-  end
-
-  generate
-  if (NUM_OF_SDI > 1) begin
-    // Only the first two SDI data can be recovered through AXI regmap
-    assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data[DATA_WIDTH+:DATA_WIDTH];
-  end else begin
-    assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data;
-  end
-  endgenerate
-
   reg [7:0] offload_sdo_mem_address_width = OFFLOAD0_SDO_MEM_ADDRESS_WIDTH;
   reg [7:0] offload_cmd_mem_address_width = OFFLOAD0_CMD_MEM_ADDRESS_WIDTH;
   reg [7:0] sdi_fifo_address_width = SDI_FIFO_ADDRESS_WIDTH;
@@ -356,10 +342,9 @@ module axi_spi_engine #(
       8'h31: up_rdata_ff <= offload_sync_id;
       8'h34: up_rdata_ff <= cmd_fifo_room;
       8'h35: up_rdata_ff <= sdo_fifo_room;
-      8'h36: up_rdata_ff <= (sdi_fifo_out_valid == 1) ? sdi_fifo_level + 1 : sdi_fifo_level; /* beacuse of first-word-fall-through */
+      8'h36: up_rdata_ff <= (sdi_fifo_out_valid == 1) ? sdi_fifo_level + 1 : sdi_fifo_level; /* because of first-word-fall-through */
       8'h3a: up_rdata_ff <= sdi_fifo_out_data[DATA_WIDTH-1:0];
-      8'h3b: up_rdata_ff <= sdi_fifo_out_data_msb_s; /* store SDI's 32 bits MSB, if exists */
-      8'h3c: up_rdata_ff <= sdi_fifo_out_data; /* PEEK register */
+      8'h3c: up_rdata_ff <= sdi_fifo_out_data[DATA_WIDTH-1:0]; /* PEEK register */
       8'h40: up_rdata_ff <= {offload0_enable_reg};
       8'h41: up_rdata_ff <= {offload0_enabled_s};
       8'h80: up_rdata_ff <= CFG_INFO_0;
@@ -421,7 +406,9 @@ module axi_spi_engine #(
     .ASYNC_CLK(ASYNC_SPI_CLK),
     .M_AXIS_REGISTERED(0),
     .ALMOST_EMPTY_THRESHOLD(1),
-    .ALMOST_FULL_THRESHOLD(1)
+    .ALMOST_FULL_THRESHOLD(1),
+    .TLAST_EN(0),
+    .TKEEP_EN(0)
   ) i_cmd_fifo (
     .s_axis_aclk(clk),
     .s_axis_aresetn(up_sw_resetn),
@@ -430,22 +417,25 @@ module axi_spi_engine #(
     .s_axis_data(cmd_fifo_in_data),
     .s_axis_room(cmd_fifo_room),
     .s_axis_tlast(1'b0),
+    .s_axis_tkeep(),
     .s_axis_full(),
     .s_axis_almost_full(),
+
     .m_axis_aclk(spi_clk),
     .m_axis_aresetn(spi_resetn),
     .m_axis_ready(cmd_ready),
     .m_axis_valid(cmd_valid),
     .m_axis_data(cmd_data),
     .m_axis_tlast(),
+    .m_axis_tkeep(),
+    .m_axis_level(),
     .m_axis_empty(),
-    .m_axis_almost_empty(cmd_fifo_almost_empty),
-    .m_axis_level());
+    .m_axis_almost_empty(cmd_fifo_almost_empty));
 
   assign sdo_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h39;
-  assign sdo_fifo_in_data = up_wdata_s[(DATA_WIDTH-1):0];
+  assign sdo_fifo_in_data = up_wdata_s[DATA_WIDTH-1:0];
 
-  util_axis_fifo #(
+   util_axis_fifo #(
     .DATA_WIDTH(DATA_WIDTH),
     .ASYNC_CLK(ASYNC_SPI_CLK),
     .ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH),
@@ -460,6 +450,7 @@ module axi_spi_engine #(
     .s_axis_data(sdo_fifo_in_data),
     .s_axis_room(sdo_fifo_room),
     .s_axis_tlast(1'b0),
+    .s_axis_tkeep(),
     .s_axis_full(),
     .s_axis_almost_full(),
     .m_axis_aclk(spi_clk),
@@ -468,62 +459,128 @@ module axi_spi_engine #(
     .m_axis_valid(sdo_data_valid),
     .m_axis_data(sdo_data),
     .m_axis_tlast(),
+    .m_axis_tkeep(),
     .m_axis_level(),
     .m_axis_empty(),
     .m_axis_almost_empty(sdo_fifo_almost_empty));
 
   assign sdi_fifo_out_ready = up_rreq_s == 1'b1 && up_raddr_s == 8'h3a;
 
-  util_axis_fifo #(
-    .DATA_WIDTH(NUM_OF_SDI * DATA_WIDTH),
+  integer i;
+  always @(posedge spi_clk) begin
+    if (!spi_resetn) begin
+      sdi_fifo_tkeep_int <= {(NUM_OF_SDI*DATA_WIDTH/8){1'b1}};
+    end else begin
+      if (cmd_valid && cmd_data[15:8] == 8'h23) begin
+         for (i = 0; i < NUM_OF_SDI; i = i + 1) begin
+          sdi_fifo_tkeep_int[i*DATA_WIDTH/8+:DATA_WIDTH/8] <= {DATA_WIDTH/8{cmd_data[i]}};
+         end
+      end
+    end
+  end
+  assign sdi_fifo_tkeep = sdi_fifo_tkeep_int;
+
+  util_axis_fifo_asym #(
     .ASYNC_CLK(ASYNC_SPI_CLK),
-    .ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH),
+    .S_DATA_WIDTH(NUM_OF_SDI * DATA_WIDTH),
+    .M_DATA_WIDTH(DATA_WIDTH),
+    .ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH),
     .M_AXIS_REGISTERED(0),
     .ALMOST_EMPTY_THRESHOLD(1),
-    .ALMOST_FULL_THRESHOLD(31)
-  ) i_sdi_fifo (
+    .ALMOST_FULL_THRESHOLD(1),
+    .TLAST_EN(0),
+    .TKEEP_EN(1),
+    .REDUCED_FIFO(0)
+  ) i_sdi_fifo(
     .s_axis_aclk(spi_clk),
     .s_axis_aresetn(spi_resetn),
     .s_axis_ready(sdi_data_ready),
     .s_axis_valid(sdi_data_valid),
     .s_axis_data(sdi_data),
     .s_axis_room(),
     .s_axis_tlast(),
+    .s_axis_tkeep(sdi_fifo_tkeep),
     .s_axis_full(),
     .s_axis_almost_full(sdi_fifo_almost_full),
+    
     .m_axis_aclk(clk),
     .m_axis_aresetn(up_sw_resetn),
-    .m_axis_ready(sdi_fifo_out_ready),
+    .m_axis_ready(sdi_fifo_out_ready || find_next_valid_fifo_value),
     .m_axis_valid(sdi_fifo_out_valid),
     .m_axis_data(sdi_fifo_out_data),
     .m_axis_tlast(),
+    .m_axis_tkeep(),
     .m_axis_level(sdi_fifo_level),
     .m_axis_empty(),
     .m_axis_almost_empty());
 
+  assign sdi_fifo_out_ready = up_rreq_s == 1'b1 && up_raddr_s == 8'h3a;
+
+  reg [3:0] sdi_out_counter;
+  reg find_next_valid_fifo_value;
+  always @(posedge clk) begin
+    if (rstn == 1'b0) begin
+      up_rack_ff <= 'd0;
+    end else begin
+      if (sdi_fifo_out_ready || find_next_valid_fifo_value) begin
+        up_rack_ff <= sdi_fifo_out_valid;
+      end else begin
+        up_rack_ff <= up_rreq_s;
+      end
+    end
+  end
+
+  //the current logic is considering that there is only one active lane in the set of lanes
+  always @(posedge clk) begin
+    if (!up_sw_resetn) begin
+      find_next_valid_fifo_value <= 1'b0;
+      sdi_out_counter <= 4'hf;
+    end else if (sdi_fifo_out_ready) begin
+      find_next_valid_fifo_value <= ~sdi_fifo_out_valid; //only in the next cycle it is possible to check if it is necessary a new read
+      sdi_out_counter <= sdi_fifo_out_valid ? 4'hf : 0;
+    end else begin
+      if (!sdi_fifo_out_valid && sdi_out_counter < max_num_of_reads) begin
+        find_next_valid_fifo_value <= 1'b1;
+        sdi_out_counter <= sdi_out_counter + 1'b1;
+      end else begin
+        find_next_valid_fifo_value <= 1'b0;
+        sdi_out_counter <= 4'hf;
+      end
+    end
+  end
+
   generate if (ASYNC_SPI_CLK) begin
 
     // synchronization FIFO for the SYNC interface
     util_axis_fifo #(
       .DATA_WIDTH(8),
       .ASYNC_CLK(ASYNC_SPI_CLK),
       .ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
-      .M_AXIS_REGISTERED(0)
+      .M_AXIS_REGISTERED(0),
+      .TLAST_EN(0),
+      .TKEEP_EN(0)
     ) i_sync_fifo (
       .s_axis_aclk(spi_clk),
       .s_axis_aresetn(spi_resetn),
       .s_axis_ready(sync_ready),
       .s_axis_valid(sync_valid),
       .s_axis_data(sync_data),
       .s_axis_room(),
+      .s_axis_tlast(),
+      .s_axis_tkeep(),
       .s_axis_full(),
+      .s_axis_almost_full(),
+
       .m_axis_aclk(clk),
       .m_axis_aresetn(up_sw_resetn),
       .m_axis_ready(1'b1),
       .m_axis_valid(sync_fifo_valid),
       .m_axis_data(sync_fifo_data),
+      .m_axis_tlast(),
+      .m_axis_tkeep(),
       .m_axis_level(),
-      .m_axis_empty());
+      .m_axis_empty(),
+      .m_axis_almost_empty());
 
     // synchronization FIFO for the offload command interface
     wire up_offload0_cmd_wr_en_s;
@@ -533,50 +590,68 @@ module axi_spi_engine #(
       .DATA_WIDTH(16),
       .ASYNC_CLK(ASYNC_SPI_CLK),
       .ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
-      .M_AXIS_REGISTERED(0)
+      .M_AXIS_REGISTERED(0),
+      .TLAST_EN(0),
+      .TKEEP_EN(0)
     ) i_offload_cmd_fifo (
       .s_axis_aclk(clk),
       .s_axis_aresetn(up_sw_resetn),
       .s_axis_ready(),
       .s_axis_valid(up_offload0_cmd_wr_en_s),
       .s_axis_data(up_offload0_cmd_wr_data_s),
       .s_axis_room(),
+      .s_axis_tlast(),
+      .s_axis_tkeep(),
       .s_axis_full(),
+      .s_axis_almost_full(),
+
       .m_axis_aclk(spi_clk),
       .m_axis_aresetn(spi_resetn),
       .m_axis_ready(1'b1),
       .m_axis_valid(offload0_cmd_wr_en),
       .m_axis_data(offload0_cmd_wr_data),
+      .m_axis_tlast(),
+      .m_axis_tkeep(),
       .m_axis_level(),
-      .m_axis_empty());
+      .m_axis_empty(),
+      .m_axis_almost_empty());
 
     assign up_offload0_cmd_wr_en_s = up_wreq_s == 1'b1 && up_waddr_s == 8'h44;
     assign up_offload0_cmd_wr_data_s = up_wdata_s[15:0];
 
     // synchronization FIFO for the offload SDO interface
     wire up_offload0_sdo_wr_en_s;
-    wire [DATA_WIDTH-1:0] up_offload0_sdo_wr_data_s;
+    wire [(DATA_WIDTH-1):0] up_offload0_sdo_wr_data_s;
 
     util_axis_fifo #(
       .DATA_WIDTH(DATA_WIDTH),
       .ASYNC_CLK(ASYNC_SPI_CLK),
       .ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
-      .M_AXIS_REGISTERED(0)
+      .M_AXIS_REGISTERED(0),
+      .TLAST_EN(0),
+      .TKEEP_EN(0)
     ) i_offload_sdo_fifo (
       .s_axis_aclk(clk),
       .s_axis_aresetn(up_sw_resetn),
       .s_axis_ready(),
       .s_axis_valid(up_offload0_sdo_wr_en_s),
       .s_axis_data(up_offload0_sdo_wr_data_s),
       .s_axis_room(),
+      .s_axis_tlast(),
+      .s_axis_tkeep(),
       .s_axis_full(),
+      .s_axis_almost_full(),
+
       .m_axis_aclk(spi_clk),
       .m_axis_aresetn(spi_resetn),
       .m_axis_ready(1'b1),
       .m_axis_valid(offload0_sdo_wr_en),
       .m_axis_data(offload0_sdo_wr_data),
+      .m_axis_tlast(),
+      .m_axis_tkeep(),
       .m_axis_level(),
-      .m_axis_empty());
+      .m_axis_empty(),
+      .m_axis_almost_empty());
 
     assign up_offload0_sdo_wr_en_s = up_wreq_s == 1'b1 && up_waddr_s == 8'h45;
     assign up_offload0_sdo_wr_data_s = up_wdata_s[DATA_WIDTH-1:0];
@@ -586,22 +661,31 @@ module axi_spi_engine #(
       .DATA_WIDTH(8),
       .ASYNC_CLK(ASYNC_SPI_CLK),
       .ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
-      .M_AXIS_REGISTERED(0)
+      .M_AXIS_REGISTERED(0),
+      .TLAST_EN(0),
+      .TKEEP_EN(0)
     ) i_offload_sync_fifo (
       .s_axis_aclk(spi_clk),
       .s_axis_aresetn(spi_resetn),
       .s_axis_ready(offload_sync_ready),
       .s_axis_valid(offload_sync_valid),
       .s_axis_data(offload_sync_data),
       .s_axis_room(),
+      .s_axis_tlast(),
+      .s_axis_tkeep(),
       .s_axis_full(),
+      .s_axis_almost_full(),
+
       .m_axis_aclk(clk),
       .m_axis_aresetn(up_sw_resetn),
       .m_axis_ready(1'b1),
       .m_axis_valid(offload_sync_fifo_valid),
       .m_axis_data(offload_sync_fifo_data),
+      .m_axis_tlast(),
+      .m_axis_tkeep(),
       .m_axis_level(),
-      .m_axis_empty());
+      .m_axis_empty(),
+      .m_axis_almost_empty());
 
   end else begin /* ASYNC_SPI_CLK == 0 */