Skip to content

Commit 6deb5cc

Browse files
Update srk_weak_final_non_diagonal.jl
1 parent 567688f commit 6deb5cc

File tree

1 file changed

+5
-4
lines changed

1 file changed

+5
-4
lines changed

test/weak_convergence/srk_weak_final_non_diagonal.jl

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -114,7 +114,8 @@ sim = test_convergence(dts, ensemble_prob, RDI1WM(),
114114
weak_timeseries_errors = false, weak_dense_errors = false,
115115
expected_value = exp(-3.0)
116116
)
117-
@test_broken abs(sim.𝒪est[:weak_final]-1.5) < 0.3 # seems closer to 1.5?
117+
@test_broken abs(sim.𝒪est[:weak_final]-2.0) < 0.3 # seems closer to 1.5?
118+
@test abs(sim.𝒪est[:weak_final]-1.5) < 0.3 # seems closer to 1.5?
118119
println("RDI1WM:", sim.𝒪est[:weak_final])
119120

120121
numtraj = Int(1e7)
@@ -127,21 +128,21 @@ sim = test_convergence(dts, ensemble_prob, RDI2WM(),
127128
weak_timeseries_errors = false, weak_dense_errors = false,
128129
expected_value = exp(-3.0)
129130
)
130-
@test -(sim.𝒪est[:weak_final]-2.5) < 0.3 # order 2.517769274990593
131+
@test abs(sim.𝒪est[:weak_final]-2.0) < 0.3
131132
println("RDI2WM:", sim.𝒪est[:weak_final])
132133

133134
sim = test_convergence(dts, ensemble_prob, RDI3WM(),
134135
save_everystep = false, trajectories = numtraj, save_start = false, adaptive = false,
135136
weak_timeseries_errors = false, weak_dense_errors = false,
136137
expected_value = exp(-3.0)
137138
)
138-
@test abs(sim.𝒪est[:weak_final]-2) < 0.3
139+
@test abs(sim.𝒪est[:weak_final]-3) < 0.4
139140
println("RDI3WM:", sim.𝒪est[:weak_final])
140141

141142
sim = test_convergence(dts, ensemble_prob, RDI4WM(),
142143
save_everystep = false, trajectories = numtraj, save_start = false, adaptive = false,
143144
weak_timeseries_errors = false, weak_dense_errors = false,
144145
expected_value = exp(-3.0)
145146
)
146-
@test abs(sim.𝒪est[:weak_final]-2) < 0.3
147+
@test abs(sim.𝒪est[:weak_final]-3) < 0.4
147148
println("RDI4WM:", sim.𝒪est[:weak_final])

0 commit comments

Comments
 (0)