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torvaldstorvalds
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Merge tag 'drm-next-2023-11-10' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Daniel Vetter: "Dave's VPN to the big machine died, so it's on me to do fixes pr this and next week while everyone else is at plumbers. - big pile of amd fixes, but mostly for hw support newly added in 6.7 - i915 fixes, mostly minor things - qxl memory leak fix - vc4 uaf fix in mock helpers - syncobj fix for DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE" * tag 'drm-next-2023-11-10' of git://anongit.freedesktop.org/drm/drm: (78 commits) drm/amdgpu: fix error handling in amdgpu_vm_init drm/amdgpu: Fix possible null pointer dereference drm/amdgpu: move UVD and VCE sched entity init after sched init drm/amdgpu: move kfd_resume before the ip late init drm/amd: Explicitly check for GFXOFF to be enabled for s0ix drm/amdgpu: Change WREG32_RLC to WREG32_SOC15_RLC where inst != 0 (v2) drm/amdgpu: Use correct KIQ MEC engine for gfx9.4.3 (v5) drm/amdgpu: add smu v13.0.6 pcs xgmi ras error query support drm/amdgpu: fix software pci_unplug on some chips drm/amd/display: remove duplicated argument drm/amdgpu: correct mca debugfs dump reg list drm/amdgpu: correct acclerator check architecutre dump drm/amdgpu: add pcs xgmi v6.4.0 ras support drm/amdgpu: Change extended-scope MTYPE on GC 9.4.3 drm/amdgpu: disable smu v13.0.6 mca debug mode by default drm/amdgpu: Support multiple error query modes drm/amdgpu: refine smu v13.0.6 mca dump driver drm/amdgpu: Do not program PF-only regs in hdp_v4_0.c under SRIOV (v2) drm/amdgpu: Skip PCTL0_MMHUB_DEEPSLEEP_IB write in jpegv4.0.3 under SRIOV drm: amd: Resolve Sphinx unexpected indentation warning ...
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‎drivers/gpu/drm/amd/amdgpu/amdgpu.h‎

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1159,11 +1159,18 @@ uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
11591159
uint32_t reg, uint32_t acc_flags);
11601160
u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,
11611161
u64 reg_addr);
1162+
uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev,
1163+
uint32_t reg, uint32_t acc_flags,
1164+
uint32_t xcc_id);
11621165
void amdgpu_device_wreg(struct amdgpu_device *adev,
11631166
uint32_t reg, uint32_t v,
11641167
uint32_t acc_flags);
11651168
void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev,
11661169
u64 reg_addr, u32 reg_data);
1170+
void amdgpu_device_xcc_wreg(struct amdgpu_device *adev,
1171+
uint32_t reg, uint32_t v,
1172+
uint32_t acc_flags,
1173+
uint32_t xcc_id);
11671174
void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
11681175
uint32_t reg, uint32_t v, uint32_t xcc_id);
11691176
void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
@@ -1204,8 +1211,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
12041211
#define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
12051212
#define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
12061213

1207-
#define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
1208-
#define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
1214+
#define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0)
1215+
#define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0)
12091216

12101217
#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
12111218
#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
@@ -1215,6 +1222,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
12151222
#define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
12161223
#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
12171224
#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1225+
#define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst)
1226+
#define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst)
12181227
#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
12191228
#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
12201229
#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))

‎drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1494,6 +1494,9 @@ bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev)
14941494
if (adev->asic_type < CHIP_RAVEN)
14951495
return false;
14961496

1497+
if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1498+
return false;
1499+
14971500
/*
14981501
* If ACPI_FADT_LOW_POWER_S0 is not set in the FADT, it is generally
14991502
* risky to do any special firmware-related preparations for entering

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c‎

Lines changed: 18 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -300,14 +300,13 @@ static int kgd_gfx_v9_4_3_hqd_load(struct amdgpu_device *adev, void *mqd,
300300
hqd_end = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_AQL_DISPATCH_ID_HI);
301301

302302
for (reg = hqd_base; reg <= hqd_end; reg++)
303-
WREG32_RLC(reg, mqd_hqd[reg - hqd_base]);
303+
WREG32_XCC(reg, mqd_hqd[reg - hqd_base], inst);
304304

305305

306306
/* Activate doorbell logic before triggering WPTR poll. */
307307
data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
308308
CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
309-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_DOORBELL_CONTROL),
310-
data);
309+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_DOORBELL_CONTROL, data);
311310

312311
if (wptr) {
313312
/* Don't read wptr with get_user because the user
@@ -336,27 +335,24 @@ static int kgd_gfx_v9_4_3_hqd_load(struct amdgpu_device *adev, void *mqd,
336335
guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);
337336
guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
338337

339-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_LO),
340-
lower_32_bits(guessed_wptr));
341-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI),
342-
upper_32_bits(guessed_wptr));
343-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR),
344-
lower_32_bits((uintptr_t)wptr));
345-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
346-
regCP_HQD_PQ_WPTR_POLL_ADDR_HI),
338+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_LO,
339+
lower_32_bits(guessed_wptr));
340+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI,
341+
upper_32_bits(guessed_wptr));
342+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR,
343+
lower_32_bits((uintptr_t)wptr));
344+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
347345
upper_32_bits((uintptr_t)wptr));
348-
WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_PQ_WPTR_POLL_CNTL1),
349-
(uint32_t)kgd_gfx_v9_get_queue_mask(adev, pipe_id,
350-
queue_id));
346+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_PQ_WPTR_POLL_CNTL1,
347+
(uint32_t)kgd_gfx_v9_get_queue_mask(adev, pipe_id, queue_id));
351348
}
352349

353350
/* Start the EOP fetcher */
354-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_EOP_RPTR),
355-
REG_SET_FIELD(m->cp_hqd_eop_rptr,
356-
CP_HQD_EOP_RPTR, INIT_FETCHER, 1));
351+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_EOP_RPTR,
352+
REG_SET_FIELD(m->cp_hqd_eop_rptr, CP_HQD_EOP_RPTR, INIT_FETCHER, 1));
357353

358354
data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
359-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_ACTIVE), data);
355+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_ACTIVE, data);
360356

361357
kgd_gfx_v9_release_queue(adev, inst);
362358

@@ -494,15 +490,15 @@ static uint32_t kgd_gfx_v9_4_3_set_address_watch(
494490
VALID,
495491
1);
496492

497-
WREG32_RLC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
493+
WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
498494
regTCP_WATCH0_ADDR_H) +
499495
(watch_id * TCP_WATCH_STRIDE)),
500-
watch_address_high);
496+
watch_address_high, inst);
501497

502-
WREG32_RLC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
498+
WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
503499
regTCP_WATCH0_ADDR_L) +
504500
(watch_id * TCP_WATCH_STRIDE)),
505-
watch_address_low);
501+
watch_address_low, inst);
506502

507503
return watch_address_cntl;
508504
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c‎

Lines changed: 20 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -91,8 +91,8 @@ void kgd_gfx_v9_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmi
9191
{
9292
kgd_gfx_v9_lock_srbm(adev, 0, 0, 0, vmid, inst);
9393

94-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmSH_MEM_CONFIG), sh_mem_config);
95-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmSH_MEM_BASES), sh_mem_bases);
94+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_CONFIG, sh_mem_config);
95+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_BASES, sh_mem_bases);
9696
/* APE1 no longer exists on GFX9 */
9797

9898
kgd_gfx_v9_unlock_srbm(adev, inst);
@@ -239,14 +239,13 @@ int kgd_gfx_v9_hqd_load(struct amdgpu_device *adev, void *mqd,
239239

240240
for (reg = hqd_base;
241241
reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++)
242-
WREG32_RLC(reg, mqd_hqd[reg - hqd_base]);
242+
WREG32_XCC(reg, mqd_hqd[reg - hqd_base], inst);
243243

244244

245245
/* Activate doorbell logic before triggering WPTR poll. */
246246
data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
247247
CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
248-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL),
249-
data);
248+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL, data);
250249

251250
if (wptr) {
252251
/* Don't read wptr with get_user because the user
@@ -275,25 +274,24 @@ int kgd_gfx_v9_hqd_load(struct amdgpu_device *adev, void *mqd,
275274
guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);
276275
guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
277276

278-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_LO),
279-
lower_32_bits(guessed_wptr));
280-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI),
281-
upper_32_bits(guessed_wptr));
282-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR),
283-
lower_32_bits((uintptr_t)wptr));
284-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
285-
upper_32_bits((uintptr_t)wptr));
286-
WREG32_SOC15(GC, GET_INST(GC, inst), mmCP_PQ_WPTR_POLL_CNTL1,
287-
(uint32_t)kgd_gfx_v9_get_queue_mask(adev, pipe_id, queue_id));
277+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_LO,
278+
lower_32_bits(guessed_wptr));
279+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI,
280+
upper_32_bits(guessed_wptr));
281+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR,
282+
lower_32_bits((uintptr_t)wptr));
283+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
284+
upper_32_bits((uintptr_t)wptr));
285+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_PQ_WPTR_POLL_CNTL1,
286+
(uint32_t)kgd_gfx_v9_get_queue_mask(adev, pipe_id, queue_id));
288287
}
289288

290289
/* Start the EOP fetcher */
291-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_EOP_RPTR),
292-
REG_SET_FIELD(m->cp_hqd_eop_rptr,
293-
CP_HQD_EOP_RPTR, INIT_FETCHER, 1));
290+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_EOP_RPTR,
291+
REG_SET_FIELD(m->cp_hqd_eop_rptr, CP_HQD_EOP_RPTR, INIT_FETCHER, 1));
294292

295293
data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
296-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE), data);
294+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE, data);
297295

298296
kgd_gfx_v9_release_queue(adev, inst);
299297

@@ -556,7 +554,7 @@ int kgd_gfx_v9_hqd_destroy(struct amdgpu_device *adev, void *mqd,
556554
break;
557555
}
558556

559-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_DEQUEUE_REQUEST), type);
557+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_DEQUEUE_REQUEST, type);
560558

561559
end_jiffies = (utimeout * HZ / 1000) + jiffies;
562560
while (true) {
@@ -908,8 +906,8 @@ void kgd_gfx_v9_get_iq_wait_times(struct amdgpu_device *adev,
908906
uint32_t inst)
909907

910908
{
911-
*wait_times = RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
912-
mmCP_IQ_WAIT_TIME2));
909+
*wait_times = RREG32_SOC15_RLC(GC, GET_INST(GC, inst),
910+
mmCP_IQ_WAIT_TIME2);
913911
}
914912

915913
void kgd_gfx_v9_set_vm_context_page_table_base(struct amdgpu_device *adev,

‎drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -172,6 +172,7 @@ int amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id,
172172
}
173173

174174
rcu_read_unlock();
175+
*result = NULL;
175176
return -ENOENT;
176177
}
177178

‎drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1415,7 +1415,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
14151415
if (r == -ENOMEM)
14161416
DRM_ERROR("Not enough memory for command submission!\n");
14171417
else if (r != -ERESTARTSYS && r != -EAGAIN)
1418-
DRM_ERROR("Failed to process the buffer list %d!\n", r);
1418+
DRM_DEBUG("Failed to process the buffer list %d!\n", r);
14191419
goto error_fini;
14201420
}
14211421

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c‎

Lines changed: 105 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -73,6 +73,7 @@
7373
#include "amdgpu_pmu.h"
7474
#include "amdgpu_fru_eeprom.h"
7575
#include "amdgpu_reset.h"
76+
#include "amdgpu_virt.h"
7677

7778
#include <linux/suspend.h>
7879
#include <drm/task_barrier.h>
@@ -472,7 +473,7 @@ uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
472473
if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
473474
amdgpu_sriov_runtime(adev) &&
474475
down_read_trylock(&adev->reset_domain->sem)) {
475-
ret = amdgpu_kiq_rreg(adev, reg);
476+
ret = amdgpu_kiq_rreg(adev, reg, 0);
476477
up_read(&adev->reset_domain->sem);
477478
} else {
478479
ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
@@ -509,6 +510,49 @@ uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset)
509510
BUG();
510511
}
511512

513+
514+
/**
515+
* amdgpu_device_xcc_rreg - read a memory mapped IO or indirect register with specific XCC
516+
*
517+
* @adev: amdgpu_device pointer
518+
* @reg: dword aligned register offset
519+
* @acc_flags: access flags which require special behavior
520+
* @xcc_id: xcc accelerated compute core id
521+
*
522+
* Returns the 32 bit value from the offset specified.
523+
*/
524+
uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev,
525+
uint32_t reg, uint32_t acc_flags,
526+
uint32_t xcc_id)
527+
{
528+
uint32_t ret, rlcg_flag;
529+
530+
if (amdgpu_device_skip_hw_access(adev))
531+
return 0;
532+
533+
if ((reg * 4) < adev->rmmio_size) {
534+
if (amdgpu_sriov_vf(adev) &&
535+
!amdgpu_sriov_runtime(adev) &&
536+
adev->gfx.rlc.rlcg_reg_access_supported &&
537+
amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags,
538+
GC_HWIP, false,
539+
&rlcg_flag)) {
540+
ret = amdgpu_virt_rlcg_reg_rw(adev, reg, 0, rlcg_flag, xcc_id);
541+
} else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
542+
amdgpu_sriov_runtime(adev) &&
543+
down_read_trylock(&adev->reset_domain->sem)) {
544+
ret = amdgpu_kiq_rreg(adev, reg, xcc_id);
545+
up_read(&adev->reset_domain->sem);
546+
} else {
547+
ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
548+
}
549+
} else {
550+
ret = adev->pcie_rreg(adev, reg * 4);
551+
}
552+
553+
return ret;
554+
}
555+
512556
/*
513557
* MMIO register write with bytes helper functions
514558
* @offset:bytes offset from MMIO start
@@ -556,7 +600,7 @@ void amdgpu_device_wreg(struct amdgpu_device *adev,
556600
if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
557601
amdgpu_sriov_runtime(adev) &&
558602
down_read_trylock(&adev->reset_domain->sem)) {
559-
amdgpu_kiq_wreg(adev, reg, v);
603+
amdgpu_kiq_wreg(adev, reg, v, 0);
560604
up_read(&adev->reset_domain->sem);
561605
} else {
562606
writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
@@ -597,6 +641,47 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
597641
}
598642
}
599643

644+
/**
645+
* amdgpu_device_xcc_wreg - write to a memory mapped IO or indirect register with specific XCC
646+
*
647+
* @adev: amdgpu_device pointer
648+
* @reg: dword aligned register offset
649+
* @v: 32 bit value to write to the register
650+
* @acc_flags: access flags which require special behavior
651+
* @xcc_id: xcc accelerated compute core id
652+
*
653+
* Writes the value specified to the offset specified.
654+
*/
655+
void amdgpu_device_xcc_wreg(struct amdgpu_device *adev,
656+
uint32_t reg, uint32_t v,
657+
uint32_t acc_flags, uint32_t xcc_id)
658+
{
659+
uint32_t rlcg_flag;
660+
661+
if (amdgpu_device_skip_hw_access(adev))
662+
return;
663+
664+
if ((reg * 4) < adev->rmmio_size) {
665+
if (amdgpu_sriov_vf(adev) &&
666+
!amdgpu_sriov_runtime(adev) &&
667+
adev->gfx.rlc.rlcg_reg_access_supported &&
668+
amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags,
669+
GC_HWIP, true,
670+
&rlcg_flag)) {
671+
amdgpu_virt_rlcg_reg_rw(adev, reg, v, rlcg_flag, xcc_id);
672+
} else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
673+
amdgpu_sriov_runtime(adev) &&
674+
down_read_trylock(&adev->reset_domain->sem)) {
675+
amdgpu_kiq_wreg(adev, reg, v, xcc_id);
676+
up_read(&adev->reset_domain->sem);
677+
} else {
678+
writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
679+
}
680+
} else {
681+
adev->pcie_wreg(adev, reg * 4, v);
682+
}
683+
}
684+
600685
/**
601686
* amdgpu_device_indirect_rreg - read an indirect register
602687
*
@@ -2499,6 +2584,18 @@ static int amdgpu_device_init_schedulers(struct amdgpu_device *adev)
24992584
ring->name);
25002585
return r;
25012586
}
2587+
r = amdgpu_uvd_entity_init(adev, ring);
2588+
if (r) {
2589+
DRM_ERROR("Failed to create UVD scheduling entity on ring %s.\n",
2590+
ring->name);
2591+
return r;
2592+
}
2593+
r = amdgpu_vce_entity_init(adev, ring);
2594+
if (r) {
2595+
DRM_ERROR("Failed to create VCE scheduling entity on ring %s.\n",
2596+
ring->name);
2597+
return r;
2598+
}
25022599
}
25032600

25042601
amdgpu_xcp_update_partition_sched_list(adev);
@@ -4486,19 +4583,18 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
44864583
}
44874584
amdgpu_fence_driver_hw_init(adev);
44884585

4489-
r = amdgpu_device_ip_late_init(adev);
4490-
if (r)
4491-
goto exit;
4492-
4493-
queue_delayed_work(system_wq, &adev->delayed_init_work,
4494-
msecs_to_jiffies(AMDGPU_RESUME_MS));
4495-
44964586
if (!adev->in_s0ix) {
44974587
r = amdgpu_amdkfd_resume(adev, adev->in_runpm);
44984588
if (r)
44994589
goto exit;
45004590
}
45014591

4592+
r = amdgpu_device_ip_late_init(adev);
4593+
if (r)
4594+
goto exit;
4595+
4596+
queue_delayed_work(system_wq, &adev->delayed_init_work,
4597+
msecs_to_jiffies(AMDGPU_RESUME_MS));
45024598
exit:
45034599
if (amdgpu_sriov_vf(adev)) {
45044600
amdgpu_virt_init_data_exchange(adev);

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