From 619d782174d7b9489ca4ad6302f6e5f6d77f4265 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Tue, 7 Oct 2025 16:13:47 +0200
Subject: [PATCH 01/77] initial version of multi-threading implementation

---
 CMakeLists.txt               |   1 +
 src/sysc/core2sc_adapter.h   |  65 ++++-
 src/sysc/core_complex.cpp    |   7 -
 src/sysc/core_complex_mt.cpp | 526 +++++++++++++++++++++++++++++++++++
 src/sysc/core_complex_mt.h   | 226 +++++++++++++++
 src/sysc/sc2core_if.h        |   2 +
 6 files changed, 815 insertions(+), 12 deletions(-)
 create mode 100644 src/sysc/core_complex_mt.cpp
 create mode 100644 src/sysc/core_complex_mt.h

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 377c6fd..08c10b2 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -261,6 +261,7 @@ if(TARGET scc-sysc)
     project(dbt-rise-riscv_sc VERSION 1.0.0)
     set(LIB_SOURCES
         src/sysc/core_complex.cpp
+        src/sysc/core_complex_mt.cpp
         src/sysc/register_cores.cpp
         src/sysc/register_rv32gcv.cpp
         src/sysc/register_rv64gcv.cpp
diff --git a/src/sysc/core2sc_adapter.h b/src/sysc/core2sc_adapter.h
index 368a5ac..353bb81 100644
--- a/src/sysc/core2sc_adapter.h
+++ b/src/sysc/core2sc_adapter.h
@@ -35,15 +35,18 @@
 #ifndef _SYSC_CORE2SC_ADAPTER_H_
 #define _SYSC_CORE2SC_ADAPTER_H_
 
-#include "core_complex.h"
+#include "core_complex_if.h"
 #include "sc2core_if.h"
 #include <iostream>
 #include <iss/arch/riscv_hart_common.h>
 #include <iss/iss.h>
 #include <iss/mem/memory_if.h>
 #include <iss/vm_types.h>
+#include <scc/async_event.h>
 #include <scc/report.h>
+#include <shared_mutex>
 #include <util/ities.h>
+
 namespace sysc {
 template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if {
 public:
@@ -51,6 +54,7 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
     using core = typename PLAT::core;
     using reg_t = typename PLAT::reg_t;
     using phys_addr_t = typename PLAT::phys_addr_t;
+    using mutex_t = std::shared_mutex;
     core2sc_adapter(sysc::riscv::core_complex_if* owner)
     : owner(owner) {
         this->csr_rd_cb[iss::arch::time] = MK_CSR_RD_CB(read_time);
@@ -68,6 +72,18 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
         this->register_csr_wr = util::delegate<void(unsigned, wr_csr_f)>::from<this_class, &this_class::_register_csr_wr>(this);
     }
 
+    void setup_mt() override {
+        this->set_hartid = util::delegate<void(unsigned)>::from<this_class, &this_class::_set_mhartid_mt>(this);
+        this->set_irq_count = util::delegate<void(unsigned)>::from<this_class, &this_class::_set_irq_num_mt>(this);
+        this->get_mode = util::delegate<uint32_t()>::from<this_class, &this_class::_get_mode_mt>(this);
+        this->get_state = util::delegate<uint64_t()>::from<this_class, &this_class::_get_state_mt>(this);
+        this->get_interrupt_execution = util::delegate<bool()>::from<this_class, &this_class::_get_interrupt_execution_mt>(this);
+        this->set_interrupt_execution = util::delegate<void(bool)>::from<this_class, &this_class::_set_interrupt_execution_mt>(this);
+        this->local_irq = util::delegate<void(short, bool)>::from<this_class, &this_class::_local_irq_mt>(this);
+        this->register_csr_rd = util::delegate<void(unsigned, rd_csr_f)>::from<this_class, &this_class::_register_csr_rd_mt>(this);
+        this->register_csr_wr = util::delegate<void(unsigned, wr_csr_f)>::from<this_class, &this_class::_register_csr_wr_mt>(this);
+    }
+
     virtual ~core2sc_adapter() {}
 
     void notify_phase(iss::arch_if::exec_phase p) {
@@ -88,8 +104,9 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
             std::stringstream s;
             s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0') << std::setw(sizeof(reg_t) * 2)
               << (reg_t)this->state.mstatus << std::dec << ";c:" << this->reg.icount + this->cycle_offset << "]";
-            SCCDEBUG(owner->hier_name()) << "disass: " << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc
-                                         << "\t\t" << std::setw(40) << std::setfill(' ') << std::left << instr << s.str();
+            SCCDEBUG(owner->hier_name()) << "disass: "
+                                         << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t"
+                                         << std::setw(40) << std::setfill(' ') << std::left << instr << s.str();
         }
     };
 
@@ -172,22 +189,46 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
         SCCDEBUG(owner->hier_name()) << "Sleeping until interrupt";
         PLAT::wait_until(flags);
         while(this->reg.pending_trap == 0 && (this->csr[iss::arch::mip] & this->csr[iss::arch::mie]) == 0) {
-            sc_core::wait(wfi_evt);
+            sc_core::wait(wfi_evt.event());
         }
     }
 
 private:
     void _set_mhartid(unsigned id) { PLAT::set_mhartid(id); }
+    void _set_mhartid_mt(unsigned id) {
+        std::unique_lock<mutex_t> lock(sync_mtx);
+        PLAT::set_mhartid(id);
+    }
 
     void _set_irq_num(unsigned num) { PLAT::set_irq_num(num); }
+    void _set_irq_num_mt(unsigned num) {
+        std::unique_lock<mutex_t> lock(sync_mtx);
+        PLAT::set_irq_num(num);
+    }
 
     uint32_t _get_mode() { return this->reg.PRIV; }
+    uint32_t _get_mode_mt() {
+        std::shared_lock<mutex_t> lock(sync_mtx);
+        return this->reg.PRIV;
+    }
 
     void _set_interrupt_execution(bool v) { this->interrupt_sim = v ? 1 : 0; }
+    void _set_interrupt_execution_mt(bool v) {
+        std::unique_lock<mutex_t> lock(sync_mtx);
+        this->interrupt_sim = v ? 1 : 0;
+    }
 
     bool _get_interrupt_execution() { return this->interrupt_sim; }
+    bool _get_interrupt_execution_mt() {
+        std::shared_lock<mutex_t> lock(sync_mtx);
+        return this->interrupt_sim;
+    }
 
     uint64_t _get_state() { return this->state.mstatus.backing.val; }
+    uint64_t _get_state_mt() {
+        std::shared_lock<mutex_t> lock(sync_mtx);
+        return this->state.mstatus.backing.val;
+    }
 
     void _local_irq(short id, bool value) {
         reg_t mask = 0;
@@ -215,6 +256,10 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
         if(value)
             SCCTRACE(owner->hier_name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap;
     }
+    void _local_irq_mt(short id, bool value) {
+        std::unique_lock<mutex_t> lock(sync_mtx);
+        _local_irq(id, value);
+    }
 
     void _register_csr_rd(unsigned addr, rd_csr_f cb) {
         std::function<iss::status(unsigned addr, reg_t&)> lambda = [cb](unsigned addr, reg_t& r) -> iss::status {
@@ -225,15 +270,25 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
         };
         this->register_csr(addr, lambda);
     }
+    void _register_csr_rd_mt(unsigned addr, rd_csr_f cb) {
+        std::unique_lock<mutex_t> lock(sync_mtx);
+        _register_csr_rd(addr, cb);
+    }
+
     void _register_csr_wr(unsigned addr, wr_csr_f cb) {
         std::function<iss::status(unsigned addr, reg_t)> lambda = [cb](unsigned addr, reg_t r) -> iss::status { return cb(addr, r); };
         this->register_csr(addr, lambda);
     }
+    void _register_csr_wr_mt(unsigned addr, wr_csr_f cb) {
+        std::unique_lock<mutex_t> lock(sync_mtx);
+        _register_csr_wr(addr, cb);
+    }
 
     sysc::riscv::core_complex_if* const owner{nullptr};
-    sc_core::sc_event wfi_evt;
+    scc::async_event wfi_evt;
     unsigned to_host_wr_cnt = 0;
     bool first{true};
+    mutex_t sync_mtx;
 };
 } // namespace sysc
 #endif /* _SYSC_CORE2SC_ADAPTER_H_ */
diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index 728048e..9ce5f92 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -51,15 +51,8 @@
 #include <iss/plugin/cycle_estimate.h>
 #include <iss/plugin/instruction_count.h>
 #include <util/ities.h>
-
 // clang-format on
 
-#define STR(X) #X
-#define CREATE_CORE(CN)                                                                                                                    \
-    if(type == STR(CN)) {                                                                                                                  \
-        std::tie(cpu, vm) = create_core<CN##_plat_type>(backend, gdb_port, hart_id);                                                       \
-    } else
-
 #ifdef HAS_SCV
 #include <scv.h>
 #else
diff --git a/src/sysc/core_complex_mt.cpp b/src/sysc/core_complex_mt.cpp
new file mode 100644
index 0000000..c4136b9
--- /dev/null
+++ b/src/sysc/core_complex_mt.cpp
@@ -0,0 +1,526 @@
+/*******************************************************************************
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+// clang-format off
+#include "core_complex_mt.h"
+#include <future>
+#include <iss/debugger/gdb_session.h>
+#include <iss/debugger/encoderdecoder.h>
+#include <iss/debugger/server.h>
+#include <iss/debugger/target_adapter_if.h>
+#include <iss/iss.h>
+#include <iss/vm_types.h>
+#include "iss_factory.h"
+#include <memory>
+#include <sstream>
+#include <sysc/kernel/sc_time.h>
+#include <tlm/scc/tlm_signal_gp.h>
+#include <tlm_core/tlm_2/tlm_generic_payload/tlm_gp.h>
+#ifndef WIN32
+#include <iss/plugin/loader.h>
+#endif
+#include <scc/report.h>
+#include <util/ities.h>
+#include <array>
+#include <iss/plugin/cycle_estimate.h>
+#include <iss/plugin/instruction_count.h>
+#include <util/ities.h>
+// clang-format on
+
+#ifdef HAS_SCV
+#include <scv.h>
+#else
+#include <scv-tr.h>
+using namespace scv_tr;
+#endif
+
+#define GET_PROP_VALUE(P) P.get_value()
+
+#ifdef _MSC_VER
+// not #if defined(_WIN32) || defined(_WIN64) because we have strncasecmp in mingw
+#define strncasecmp _strnicmp
+#define strcasecmp _stricmp
+#endif
+
+namespace sysc {
+namespace riscv {
+using namespace std;
+using namespace iss;
+using namespace logging;
+using namespace sc_core;
+
+namespace {
+iss::debugger::encoder_decoder encdec;
+std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
+} // namespace
+
+template <unsigned int BUSWIDTH>
+int core_complex_mt<BUSWIDTH>::cmd_sysc(int argc, char* argv[], debugger::out_func of, debugger::data_func df,
+                                        debugger::target_adapter_if* tgt_adapter) {
+    if(argc > 1) {
+        if(strcasecmp(argv[1], "print_time") == 0) {
+            std::string t = sc_time_stamp().to_string();
+            of(t.c_str());
+            std::array<char, 64> buf;
+            encdec.enc_string(t.c_str(), buf.data(), 63);
+            df(buf.data());
+            return Ok;
+        } else if(strcasecmp(argv[1], "break") == 0) {
+            sc_time t;
+            if(argc == 4) {
+                t = scc::parse_from_string(argv[2], argv[3]);
+            } else if(argc == 3) {
+                t = scc::parse_from_string(argv[2]);
+            } else
+                return Err;
+            // no check needed as it is only called if debug server is active
+            tgt_adapter->add_break_condition([t]() -> unsigned {
+                SCCTRACE() << "Checking condition at " << sc_time_stamp();
+                return sc_time_stamp() >= t ? std::numeric_limits<unsigned>::max() : 0;
+            });
+            return Ok;
+        }
+        return Err;
+    }
+    return Err;
+}
+
+template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::reset(uint64_t addr) { vm->reset(addr); }
+
+template <unsigned int BUSWIDTH> inline std::pair<uint64_t, bool> core_complex_mt<BUSWIDTH>::load_file(std::string const& name) {
+    iss::arch_if* cc = vm->get_arch();
+    return cc->load_file(name);
+};
+
+template <unsigned int BUSWIDTH>
+void core_complex_mt<BUSWIDTH>::create_cpu(std::string const& type, std::string const& backend, unsigned gdb_port, uint32_t hart_id) {
+    auto& f = sysc::iss_factory::instance();
+    if(type.size() == 0 || type == "?") {
+        std::unordered_map<std::string, std::vector<std::string>> core_by_backend;
+        for(auto& e : f.get_names()) {
+            auto p = e.find(':');
+            assert(p != std::string::npos);
+            core_by_backend[e.substr(p + 1)].push_back(e.substr(0, p));
+        }
+        std::ostringstream os;
+        os << "Available implementations\n";
+        os << "=========================\n";
+        for(auto& e : core_by_backend) {
+            std::sort(std::begin(e.second), std::end(e.second));
+            if(os.str().size())
+                os << "\n";
+            os << "  backend " << e.first << ":\n  - " << util::join(e.second, "\n  - ");
+        }
+        SCCINFO(SCMOD) << "\n" << os.str();
+        sc_core::sc_stop();
+    } else if(type.find(':') == std::string::npos) {
+        std::tie(core, vm) = f.create(type + ":" + backend, gdb_port, this);
+    } else {
+        auto base_isa = type.substr(0, 5);
+        if(base_isa == "tgc5d" || base_isa == "tgc5e") {
+            std::tie(core, vm) = f.create(type + "_clic_pmp:" + backend, gdb_port, this);
+        } else {
+            std::tie(core, vm) = f.create(type + ":" + backend, gdb_port, this);
+        }
+    }
+    if(!core) {
+        if(type != "?")
+            SCCFATAL() << "Could not create cpu for isa " << type << " and backend " << backend;
+    } else if(!vm) {
+        if(type != "?")
+            SCCFATAL() << "Could not create vm for isa " << type << " and backend " << backend;
+    } else {
+        core->set_hartid(hart_id);
+        auto* srv = debugger::server<debugger::gdb_session>::get();
+        if(srv)
+            tgt_adapter = srv->get_target(0); // FIXME: add core_id
+        if(tgt_adapter)
+            tgt_adapter->add_custom_command({"sysc",
+                                             [this](int argc, char* argv[], debugger::out_func of, debugger::data_func df) -> int {
+                                                 return cmd_sysc(argc, argv, of, df, tgt_adapter);
+                                             },
+                                             "SystemC sub-commands: break <time>, print_time"});
+    }
+}
+
+template <unsigned int BUSWIDTH>
+core_complex_mt<BUSWIDTH>::core_complex_mt(sc_module_name const& name)
+: sc_module(name)
+, fetch_lut(tlm_dmi_ext())
+, read_lut(tlm_dmi_ext())
+, write_lut(tlm_dmi_ext()) {
+    init();
+}
+
+template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::init() {
+    ibus.register_invalidate_direct_mem_ptr([this](uint64_t start, uint64_t end) -> void {
+        auto lut_entry = fetch_lut.getEntry(start);
+        if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
+            fetch_lut.removeEntry(lut_entry);
+        }
+    });
+    dbus.register_invalidate_direct_mem_ptr([this](uint64_t start, uint64_t end) -> void {
+        auto lut_entry = read_lut.getEntry(start);
+        if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
+            read_lut.removeEntry(lut_entry);
+        }
+        lut_entry = write_lut.getEntry(start);
+        if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
+            write_lut.removeEntry(lut_entry);
+        }
+    });
+
+    SC_HAS_PROCESS(core_complex_mt<BUSWIDTH>); // NOLINT
+    SC_THREAD(run);
+    SC_METHOD(rst_cb);
+    sensitive << rst_i;
+#ifdef USE_TLM_SIGNAL
+    sw_irq_i.register_nb_transport([this](tlm::scc::tlm_signal_gp<bool>& gp, tlm::tlm_phase& p, sc_core::sc_time& t) {
+        cpu->local_irq(3, gp.get_value());
+        return tlm::TLM_COMPLETED;
+    });
+    timer_irq_i.register_nb_transport([this](tlm::scc::tlm_signal_gp<bool>& gp, tlm::tlm_phase& p, sc_core::sc_time& t) {
+        cpu->local_irq(7, gp.get_value());
+        return tlm::TLM_COMPLETED;
+    });
+    ext_irq_i.register_nb_transport([this](tlm::scc::tlm_signal_gp<bool>& gp, tlm::tlm_phase& p, sc_core::sc_time& t) {
+        cpu->local_irq(11, gp.get_value());
+        return tlm::TLM_COMPLETED;
+    });
+    for(auto i = 0U; i < local_irq_i.size(); ++i)
+        local_irq_i[i].register_nb_transport([this, i](tlm::scc::tlm_signal_gp<bool>& gp, tlm::tlm_phase& p, sc_core::sc_time& t) {
+            cpu->local_irq(16 + i, gp.get_value());
+            return tlm::TLM_COMPLETED;
+        });
+#else
+    SC_METHOD(sw_irq_cb);
+    sensitive << sw_irq_i;
+    SC_METHOD(timer_irq_cb);
+    sensitive << timer_irq_i;
+    SC_METHOD(ext_irq_cb);
+    sensitive << ext_irq_i;
+    SC_METHOD(local_irq_cb);
+    for(auto pin : local_irq_i)
+        sensitive << pin;
+#endif
+    trc.m_db = scv_tr_db::get_default_db();
+
+    SC_METHOD(forward);
+    sensitive << clk_i;
+    SC_THREAD(core_task_handler);
+}
+
+template <unsigned int BUSWIDTH> core_complex_mt<BUSWIDTH>::~core_complex_mt() {
+    for(auto* p : plugin_list)
+        delete p;
+}
+
+template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::trace(sc_trace_file* trf) const {}
+
+template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::before_end_of_elaboration() {
+    auto& type = GET_PROP_VALUE(core_type);
+    SCCDEBUG(SCMOD) << "instantiating core " << type << " with " << GET_PROP_VALUE(backend) << " backend";
+    // cpu = scc::make_unique<core_wrapper>(this);
+    create_cpu(type, GET_PROP_VALUE(backend), GET_PROP_VALUE(gdb_server_port), GET_PROP_VALUE(mhartid));
+    if(type == "?")
+        return;
+    if(!local_irq_num.is_default_value()) {
+        core->set_irq_count(16 + local_irq_num);
+    }
+    sc_assert(vm);
+    auto disass = GET_PROP_VALUE(enable_disass);
+    if(disass && trc.m_db)
+        SCCINFO(SCMOD) << "Disasssembly will only be in transaction trace database!";
+    vm->setDisassEnabled(disass || trc.m_db != nullptr);
+    if(GET_PROP_VALUE(plugins).length()) {
+        auto p = util::split(GET_PROP_VALUE(plugins), ';');
+        for(std::string const& opt_val : p) {
+            std::string plugin_name = opt_val;
+            std::string filename{"cycles.txt"};
+            std::size_t found = opt_val.find('=');
+            if(found != std::string::npos) {
+                plugin_name = opt_val.substr(0, found);
+                filename = opt_val.substr(found + 1, opt_val.size());
+            }
+            if(plugin_name == "ic") {
+                auto* plugin = new iss::plugin::instruction_count(filename);
+                vm->register_plugin(*plugin);
+                plugin_list.push_back(plugin);
+            } else if(plugin_name == "ce") {
+                auto* plugin = new iss::plugin::cycle_estimate(filename);
+                vm->register_plugin(*plugin);
+                plugin_list.push_back(plugin);
+            } else {
+#ifndef WIN32
+                std::array<char const*, 1> a{{filename.c_str()}};
+                iss::plugin::loader l(plugin_name, {{"initPlugin"}});
+                auto* plugin = l.call_function<iss::vm_plugin*>("initPlugin", a.size(), a.data());
+                if(plugin) {
+                    vm->register_plugin(*plugin);
+                    plugin_list.push_back(plugin);
+                } else
+#endif
+                    SCCERR(SCMOD) << "Unknown plugin '" << plugin_name << "' or plugin not found";
+            }
+        }
+    }
+}
+
+template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::start_of_simulation() {
+    // quantum_keeper.reset();
+    if(GET_PROP_VALUE(elf_file).size() > 0) {
+        auto file_names = util::split(GET_PROP_VALUE(elf_file), ',');
+        for(auto& s : file_names) {
+            std::pair<uint64_t, bool> load_result = load_file(s);
+            if(!std::get<1>(load_result)) {
+                SCCWARN(SCMOD) << "Could not load FW file " << s;
+            } else {
+                if(reset_address.is_default_value())
+                    reset_address.set_value(load_result.first);
+            }
+        }
+    }
+    if(trc.m_db != nullptr && trc.stream_handle == nullptr) {
+        string basename(this->name());
+        trc.stream_handle = new scv_tr_stream((basename + ".instr").c_str(), "TRANSACTOR", trc.m_db);
+        trc.instr_tr_handle = new scv_tr_generator<>("execute", *trc.stream_handle);
+    }
+}
+
+template <unsigned int BUSWIDTH> bool core_complex_mt<BUSWIDTH>::disass_output(uint64_t pc, const std::string instr_str) {
+    if(trc.m_db == nullptr)
+        return false;
+    if(trc.tr_handle.is_active())
+        trc.tr_handle.end_transaction();
+    trc.tr_handle = trc.instr_tr_handle->begin_transaction();
+    trc.tr_handle.record_attribute("PC", pc);
+    trc.tr_handle.record_attribute("INSTR", instr_str);
+    trc.tr_handle.record_attribute("MODE", lvl[core->get_mode()]);
+    trc.tr_handle.record_attribute("MSTATUS", core->get_state());
+    trc.tr_handle.record_attribute("LTIME_START", quantum_keeper.get_current_time().value() / 1000);
+    return true;
+}
+
+template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::core_task_handler() {
+    std::packaged_task<bool()> task;
+    wait(SC_ZERO_TIME);
+    while(true) {
+        wait(core_tasks.data_event());
+        while(core_tasks.try_get(task))
+            task();
+    }
+}
+
+template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::forward() { set_clock_period(clk_i.read()); }
+
+template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::set_clock_period(sc_core::sc_time period) {
+    curr_clk = period;
+    if(period == SC_ZERO_TIME)
+        core->set_interrupt_execution(true);
+}
+
+template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::rst_cb() {
+    if(rst_i.read())
+        core->set_interrupt_execution(true);
+}
+
+#ifndef USE_TLM_SIGNAL
+template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::sw_irq_cb() { core->local_irq(3, sw_irq_i.read()); }
+
+template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::timer_irq_cb() { core->local_irq(7, timer_irq_i.read()); }
+
+template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::ext_irq_cb() { core->local_irq(11, ext_irq_i.read()); }
+
+template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::local_irq_cb() {
+    for(auto i = 0U; i < local_irq_i.size(); ++i) {
+        if(local_irq_i[i].event()) {
+            core->local_irq(16 + i, local_irq_i[i].read());
+        }
+    }
+}
+#endif
+
+template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::run() {
+    wait(SC_ZERO_TIME); // separate from elaboration phase
+    do {
+        wait(SC_ZERO_TIME);
+        if(rst_i.read()) {
+            reset(GET_PROP_VALUE(reset_address));
+            wait(rst_i.negedge_event());
+        }
+        while(curr_clk.read() == SC_ZERO_TIME) {
+            wait(curr_clk.value_changed_event());
+        }
+        quantum_keeper.reset();
+        core->set_interrupt_execution(false);
+        core->setup_mt();
+        core_executor.start([this]() { vm->start(std::numeric_limits<uint64_t>::max(), dump_ir); });
+        wait(core_executor.thread_finish_event());
+    } while(!core->get_interrupt_execution());
+    sc_stop();
+}
+
+template <unsigned int BUSWIDTH>
+bool core_complex_mt<BUSWIDTH>::read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) {
+    auto& dmi_lut = is_fetch ? fetch_lut : read_lut;
+    auto lut_entry = dmi_lut.getEntry(addr);
+    if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && (addr + length) <= (lut_entry.get_end_address() + 1)) {
+        auto offset = addr - lut_entry.get_start_address();
+        std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data);
+        if(is_fetch)
+            ibus_inc += lut_entry.get_read_latency() / curr_clk;
+        else
+            dbus_inc += lut_entry.get_read_latency() / curr_clk;
+        return true;
+    } else {
+        auto& sckt = is_fetch ? ibus : dbus;
+        tlm::tlm_generic_payload gp;
+        gp.set_command(tlm::TLM_READ_COMMAND);
+        gp.set_address(addr);
+        gp.set_data_ptr(data);
+        gp.set_data_length(length);
+        gp.set_streaming_width(length);
+        sc_time delay = quantum_keeper.get_local_time();
+        if(trc.m_db != nullptr && trc.tr_handle.is_valid()) {
+            if(is_fetch && trc.tr_handle.is_active()) {
+                trc.tr_handle.end_transaction();
+            }
+            auto preExt = new tlm::scc::scv::tlm_recording_extension(trc.tr_handle, this);
+            gp.set_extension(preExt);
+        }
+        auto pre_delay = delay;
+        exec_b_transport(gp, delay);
+        if(pre_delay > delay) {
+            quantum_keeper.reset();
+        } else {
+            auto incr = (delay - quantum_keeper.get_local_time()) / curr_clk;
+            if(is_fetch)
+                ibus_inc += incr;
+            else
+                dbus_inc += incr;
+        }
+        SCCTRACE(this->name()) << "[local time: " << delay << "]: finish read_mem(0x" << std::hex << addr << ") : 0x"
+                               << (length == 4   ? *(uint32_t*)data
+                                   : length == 2 ? *(uint16_t*)data
+                                                 : (unsigned)*data);
+        if(gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
+            return false;
+        }
+        if(gp.is_dmi_allowed() && !GET_PROP_VALUE(disable_dmi)) {
+            gp.set_command(tlm::TLM_READ_COMMAND);
+            gp.set_address(addr);
+            tlm_dmi_ext dmi_data;
+            if(exec_get_direct_mem_ptr(gp, dmi_data)) {
+                if(dmi_data.is_read_allowed() && (addr + length - 1) <= dmi_data.get_end_address())
+                    dmi_lut.addEntry(dmi_data, dmi_data.get_start_address(), dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
+            }
+        }
+        return true;
+    }
+}
+
+template <unsigned int BUSWIDTH> bool core_complex_mt<BUSWIDTH>::write_mem(uint64_t addr, unsigned length, const uint8_t* const data) {
+    auto lut_entry = write_lut.getEntry(addr);
+    if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && (addr + length) <= (lut_entry.get_end_address() + 1)) {
+        auto offset = addr - lut_entry.get_start_address();
+        std::copy(data, data + length, lut_entry.get_dmi_ptr() + offset);
+        dbus_inc += lut_entry.get_write_latency() / curr_clk;
+        return true;
+    } else {
+        write_buf.resize(length);
+        std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
+        tlm::tlm_generic_payload gp;
+        gp.set_command(tlm::TLM_WRITE_COMMAND);
+        gp.set_address(addr);
+        gp.set_data_ptr(write_buf.data());
+        gp.set_data_length(length);
+        gp.set_streaming_width(length);
+        sc_time delay = quantum_keeper.get_local_time();
+        if(trc.m_db != nullptr && trc.tr_handle.is_valid()) {
+            auto preExt = new tlm::scc::scv::tlm_recording_extension(trc.tr_handle, this);
+            gp.set_extension(preExt);
+        }
+        auto pre_delay = delay;
+        exec_b_transport(gp, delay);
+        if(pre_delay > delay)
+            quantum_keeper.reset();
+        else
+            dbus_inc += (delay - quantum_keeper.get_local_time()) / curr_clk;
+        SCCTRACE() << "[local time: " << delay << "]: finish write_mem(0x" << std::hex << addr << ") : 0x"
+                   << (length == 4   ? *(uint32_t*)data
+                       : length == 2 ? *(uint16_t*)data
+                                     : (unsigned)*data);
+        if(gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
+            return false;
+        }
+        if(gp.is_dmi_allowed() && !GET_PROP_VALUE(disable_dmi)) {
+            gp.set_command(tlm::TLM_READ_COMMAND);
+            gp.set_address(addr);
+            tlm_dmi_ext dmi_data;
+            if(exec_get_direct_mem_ptr(gp, dmi_data)) {
+                if(dmi_data.is_write_allowed() && (addr + length - 1) <= dmi_data.get_end_address())
+                    write_lut.addEntry(dmi_data, dmi_data.get_start_address(),
+                                       dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
+            }
+        }
+        return true;
+    }
+}
+
+template <unsigned int BUSWIDTH> bool core_complex_mt<BUSWIDTH>::read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) {
+    tlm::tlm_generic_payload gp;
+    gp.set_command(tlm::TLM_READ_COMMAND);
+    gp.set_address(addr);
+    gp.set_data_ptr(data);
+    gp.set_data_length(length);
+    gp.set_streaming_width(length);
+    return dbus->transport_dbg(gp) == length;
+}
+
+template <unsigned int BUSWIDTH> bool core_complex_mt<BUSWIDTH>::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) {
+    write_buf.resize(length);
+    std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
+    tlm::tlm_generic_payload gp;
+    gp.set_command(tlm::TLM_WRITE_COMMAND);
+    gp.set_address(addr);
+    gp.set_data_ptr(write_buf.data());
+    gp.set_data_length(length);
+    gp.set_streaming_width(length);
+    return dbus->transport_dbg(gp) == length;
+}
+
+template class core_complex_mt<scc::LT>;
+template class core_complex_mt<32>;
+template class core_complex_mt<64>;
+
+} // namespace riscv
+} /* namespace sysc */
diff --git a/src/sysc/core_complex_mt.h b/src/sysc/core_complex_mt.h
new file mode 100644
index 0000000..3280b2c
--- /dev/null
+++ b/src/sysc/core_complex_mt.h
@@ -0,0 +1,226 @@
+/*******************************************************************************
+ * Copyright (C) 2017-2021 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+#ifndef _SYSC_CORE_COMPLEX__MT_H_
+#define _SYSC_CORE_COMPLEX__MT_H_
+
+#include "core_complex_if.h"
+#include "sc2core_if.h"
+#include <cci_configuration>
+#include <future>
+#include <iss/debugger/target_adapter_if.h>
+#include <iss/debugger_if.h>
+#include <iss/vm_if.h>
+#include <scc/signal_opt_ports.h>
+#include <scc/tick2time.h>
+#include <scc/traceable.h>
+#include <scc/utilities.h>
+#include <tlm/scc/initiator_mixin.h>
+#include <tlm/scc/quantum_keeper.h>
+#include <tlm/scc/scv/tlm_rec_initiator_socket.h>
+#include <tlm_core/tlm_2/tlm_2_interfaces/tlm_dmi.h>
+#ifndef SC_SIGNAL_IF
+#include <tlm/scc/signal_target_mixin.h>
+#define USE_TLM_SIGNAL
+#endif
+#include <memory>
+#include <scc/async_queue.h>
+#include <scc/async_thread.h>
+#include <tlm>
+#include <tlm_utils/tlm_quantumkeeper.h>
+#include <util/range_lut.h>
+
+namespace iss {
+class vm_plugin;
+}
+namespace sysc {
+
+class tlm_dmi_ext : public tlm::tlm_dmi {
+public:
+    bool operator==(const tlm_dmi_ext& o) const {
+        return this->get_granted_access() == o.get_granted_access() && this->get_start_address() == o.get_start_address() &&
+               this->get_end_address() == o.get_end_address();
+    }
+
+    bool operator!=(const tlm_dmi_ext& o) const { return !operator==(o); }
+};
+
+namespace riscv {
+#ifdef USE_TLM_SIGNAL
+using irq_signal_t = tlm::scc::tlm_signal_bool_opt_in;
+#else
+using irq_signal_t = sc_core::sc_in<bool>;
+#endif
+
+template <unsigned int BUSWIDTH = scc::LT>
+class core_complex_mt : public sc_core::sc_module, public scc::traceable, public core_complex_if {
+public:
+    tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<BUSWIDTH>> ibus{"ibus"};
+
+    tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<BUSWIDTH>> dbus{"dbus"};
+
+    sc_core::sc_in<bool> rst_i{"rst_i"};
+
+    irq_signal_t ext_irq_i{"ext_irq_i"};
+
+    irq_signal_t timer_irq_i{"timer_irq_i"};
+
+    irq_signal_t sw_irq_i{"sw_irq_i"};
+
+    sc_core::sc_vector<irq_signal_t> local_irq_i{"local_irq_i", 16};
+
+    sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
+
+    cci::cci_param<std::string> elf_file{"elf_file", ""};
+
+    cci::cci_param<bool> enable_disass{"enable_disass", false};
+
+    cci::cci_param<bool> disable_dmi{"disable_dmi", false};
+
+    cci::cci_param<uint64_t> reset_address{"reset_address", 0ULL};
+
+    cci::cci_param<std::string> core_type{"core_type", "rv32imac_m"};
+
+    cci::cci_param<std::string> backend{"backend", "interp"};
+
+    cci::cci_param<unsigned short> gdb_server_port{"gdb_server_port", 0};
+
+    cci::cci_param<bool> dump_ir{"dump_ir", false};
+
+    cci::cci_param<uint32_t> mhartid{"mhartid", 0};
+
+    cci::cci_param<uint32_t> local_irq_num{"local_irq_num", 0};
+
+    cci::cci_param<std::string> plugins{"plugins", ""};
+
+    core_complex_mt(sc_core::sc_module_name const& name);
+
+    ~core_complex_mt();
+
+    unsigned get_last_bus_cycles() override {
+        auto mem_incr = std::max(ibus_inc, dbus_inc);
+        ibus_inc = dbus_inc = 0;
+        return mem_incr > 1 ? mem_incr : 1;
+    }
+
+    void sync(uint64_t cycle) override {
+        auto core_inc = curr_clk * (cycle - last_sync_cycle);
+        quantum_keeper.inc(core_inc);
+        if(quantum_keeper.need_sync()) {
+            wait(quantum_keeper.get_local_time());
+            quantum_keeper.reset();
+        }
+        last_sync_cycle = cycle;
+    }
+
+    bool read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) override;
+
+    bool write_mem(uint64_t addr, unsigned length, const uint8_t* const data) override;
+
+    bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) override;
+
+    bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) override;
+
+    void trace(sc_core::sc_trace_file* trf) const override;
+
+    bool disass_output(uint64_t pc, const std::string instr) override;
+
+    void set_clock_period(sc_core::sc_time period);
+
+    char const* hier_name() override { return name(); }
+
+    void reset(uint64_t addr);
+
+    inline std::pair<uint64_t, bool> load_file(std::string const& name);
+
+protected:
+    void create_cpu(std::string const& type, std::string const& backend, unsigned gdb_port, uint32_t hart_id);
+    int cmd_sysc(int argc, char* argv[], iss::debugger::out_func, iss::debugger::data_func, iss::debugger::target_adapter_if*);
+    void before_end_of_elaboration() override;
+    void start_of_simulation() override;
+    void core_task_handler();
+    void forward();
+    void run();
+    void rst_cb();
+#ifndef USE_TLM_SIGNAL
+    void sw_irq_cb();
+    void timer_irq_cb();
+    void ext_irq_cb();
+    void local_irq_cb();
+#endif
+    void exec_b_transport(tlm::tlm_generic_payload& gp, sc_core::sc_time& delay) {
+        std::packaged_task<bool()> t([this, &gp, &delay]() {
+            dbus->b_transport(gp, delay);
+            return true;
+        });
+        std::future<bool> fu = t.get_future();
+        core_tasks.emplace(std::move(t));
+        fu.get();
+        std::deque<std::packaged_task<bool()>> q;
+        // q.push_back(std::move(t));
+    }
+    bool exec_get_direct_mem_ptr(tlm::tlm_generic_payload& gp, tlm::tlm_dmi& dmi_data) {
+        std::packaged_task<bool()> t([this, &gp, &dmi_data]() { return dbus->get_direct_mem_ptr(gp, dmi_data); });
+        std::future<bool> fu = t.get_future();
+        core_tasks.emplace(std::move(t));
+        return fu.get();
+    }
+    uint64_t last_sync_cycle = 0;
+    util::range_lut<tlm_dmi_ext> fetch_lut, read_lut, write_lut;
+    tlm::scc::quantumkeeper quantum_keeper;
+    std::vector<uint8_t> write_buf;
+    sc_core::sc_signal<sc_core::sc_time> curr_clk;
+    uint64_t ibus_inc{0}, dbus_inc{0};
+    std::unique_ptr<sc2core_if> core;
+    std::unique_ptr<iss::vm_if> vm;
+    iss::debugger::target_adapter_if* tgt_adapter{nullptr};
+    scc::async_queue<std::packaged_task<bool()>> core_tasks;
+    scc::async_thread core_executor;
+    struct {
+        //! transaction recording database
+        SCVNS scv_tr_db* m_db{nullptr};
+        //! blocking transaction recording stream handle
+        SCVNS scv_tr_stream* stream_handle{nullptr};
+        //! transaction generator handle for blocking transactions
+        SCVNS scv_tr_generator<SCVNS _scv_tr_generator_default_data, SCVNS _scv_tr_generator_default_data>* instr_tr_handle{nullptr};
+        SCVNS scv_tr_handle tr_handle;
+    } trc;
+    std::unique_ptr<scc::tick2time> t2t;
+
+private:
+    void init();
+    std::vector<iss::vm_plugin*> plugin_list;
+};
+} // namespace riscv
+} /* namespace sysc */
+
+#endif /* _SYSC_CORE_COMPLEX__MT_H_ */
diff --git a/src/sysc/sc2core_if.h b/src/sysc/sc2core_if.h
index 7626334..1193880 100644
--- a/src/sysc/sc2core_if.h
+++ b/src/sysc/sc2core_if.h
@@ -47,6 +47,8 @@ struct sc2core_if {
     // this is needed since we want to call the destructor with a pointer-to-base
     virtual ~sc2core_if() = default;
 
+    virtual void setup_mt() = 0;
+
     util::delegate<void(unsigned)> set_hartid;
     util::delegate<void(unsigned)> set_irq_count;
     util::delegate<uint32_t()> get_mode;

From 06fe403e69ac61254e951b9751d567c166ce07dd Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Tue, 7 Oct 2025 16:17:14 +0200
Subject: [PATCH 02/77] fixes wron quantum keeper

---
 src/sysc/core_complex_mt.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/sysc/core_complex_mt.h b/src/sysc/core_complex_mt.h
index 3280b2c..2d4735a 100644
--- a/src/sysc/core_complex_mt.h
+++ b/src/sysc/core_complex_mt.h
@@ -196,7 +196,7 @@ class core_complex_mt : public sc_core::sc_module, public scc::traceable, public
     }
     uint64_t last_sync_cycle = 0;
     util::range_lut<tlm_dmi_ext> fetch_lut, read_lut, write_lut;
-    tlm::scc::quantumkeeper quantum_keeper;
+    tlm::scc::quantumkeeper_mt quantum_keeper;
     std::vector<uint8_t> write_buf;
     sc_core::sc_signal<sc_core::sc_time> curr_clk;
     uint64_t ibus_inc{0}, dbus_inc{0};

From 218f65211c80d21b93d79add3ae56d082b4f6adb Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Sat, 11 Oct 2025 09:26:28 +0200
Subject: [PATCH 03/77] utilizes mt quantum keeper

---
 src/sysc/core_complex_mt.cpp | 11 ++---------
 src/sysc/core_complex_mt.h   | 19 ++++++++++---------
 2 files changed, 12 insertions(+), 18 deletions(-)

diff --git a/src/sysc/core_complex_mt.cpp b/src/sysc/core_complex_mt.cpp
index c4136b9..d0b93fd 100644
--- a/src/sysc/core_complex_mt.cpp
+++ b/src/sysc/core_complex_mt.cpp
@@ -410,19 +410,12 @@ bool core_complex_mt<BUSWIDTH>::read_mem(uint64_t addr, unsigned length, uint8_t
         gp.set_data_length(length);
         gp.set_streaming_width(length);
         sc_time delay = quantum_keeper.get_local_time();
-        if(trc.m_db != nullptr && trc.tr_handle.is_valid()) {
-            if(is_fetch && trc.tr_handle.is_active()) {
-                trc.tr_handle.end_transaction();
-            }
-            auto preExt = new tlm::scc::scv::tlm_recording_extension(trc.tr_handle, this);
-            gp.set_extension(preExt);
-        }
         auto pre_delay = delay;
-        exec_b_transport(gp, delay);
+        exec_b_transport(gp, delay, is_fetch);
         if(pre_delay > delay) {
             quantum_keeper.reset();
         } else {
-            auto incr = (delay - quantum_keeper.get_local_time()) / curr_clk;
+            auto incr = (delay - pre_delay) / curr_clk;
             if(is_fetch)
                 ibus_inc += incr;
             else
diff --git a/src/sysc/core_complex_mt.h b/src/sysc/core_complex_mt.h
index 2d4735a..dabaf76 100644
--- a/src/sysc/core_complex_mt.h
+++ b/src/sysc/core_complex_mt.h
@@ -134,11 +134,7 @@ class core_complex_mt : public sc_core::sc_module, public scc::traceable, public
 
     void sync(uint64_t cycle) override {
         auto core_inc = curr_clk * (cycle - last_sync_cycle);
-        quantum_keeper.inc(core_inc);
-        if(quantum_keeper.need_sync()) {
-            wait(quantum_keeper.get_local_time());
-            quantum_keeper.reset();
-        }
+        quantum_keeper.check_and_sync(core_inc);
         last_sync_cycle = cycle;
     }
 
@@ -177,16 +173,21 @@ class core_complex_mt : public sc_core::sc_module, public scc::traceable, public
     void ext_irq_cb();
     void local_irq_cb();
 #endif
-    void exec_b_transport(tlm::tlm_generic_payload& gp, sc_core::sc_time& delay) {
-        std::packaged_task<bool()> t([this, &gp, &delay]() {
+    void exec_b_transport(tlm::tlm_generic_payload& gp, sc_core::sc_time& delay, bool is_fetch = false) {
+        std::packaged_task<bool()> t([this, &gp, &delay, is_fetch]() {
+            if(trc.m_db != nullptr && trc.tr_handle.is_valid()) {
+                if(is_fetch && trc.tr_handle.is_active()) {
+                    trc.tr_handle.end_transaction();
+                }
+                auto preExt = new tlm::scc::scv::tlm_recording_extension(trc.tr_handle, this);
+                gp.set_extension(preExt);
+            }
             dbus->b_transport(gp, delay);
             return true;
         });
         std::future<bool> fu = t.get_future();
         core_tasks.emplace(std::move(t));
         fu.get();
-        std::deque<std::packaged_task<bool()>> q;
-        // q.push_back(std::move(t));
     }
     bool exec_get_direct_mem_ptr(tlm::tlm_generic_payload& gp, tlm::tlm_dmi& dmi_data) {
         std::packaged_task<bool()> t([this, &gp, &dmi_data]() { return dbus->get_direct_mem_ptr(gp, dmi_data); });

From f3d4a689d5ff366f2deab65fccf3d5cd4a839986 Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Mon, 27 Oct 2025 14:33:02 +0100
Subject: [PATCH 04/77] updates ISA and regenerates affected cores

---
 gen_input/ISA                | 2 +-
 src/vm/asmjit/vm_rv32gcv.cpp | 6 ++++--
 src/vm/asmjit/vm_rv64gcv.cpp | 6 ++++--
 src/vm/interp/vm_rv32gcv.cpp | 4 +++-
 src/vm/interp/vm_rv64gcv.cpp | 4 +++-
 5 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/gen_input/ISA b/gen_input/ISA
index c0d5707..785b339 160000
--- a/gen_input/ISA
+++ b/gen_input/ISA
@@ -1 +1 @@
-Subproject commit c0d570783c2c36080195496e6bcf5c64e9960601
+Subproject commit 785b339d8f124c608f4c7d5e985df98a72fb7459
diff --git a/src/vm/asmjit/vm_rv32gcv.cpp b/src/vm/asmjit/vm_rv32gcv.cpp
index 9a0ad8f..61499b2 100644
--- a/src/vm/asmjit/vm_rv32gcv.cpp
+++ b/src/vm/asmjit/vm_rv32gcv.cpp
@@ -11850,8 +11850,10 @@ template <typename ARCH> class vm_impl : public iss::asmjit::vm_base<ARCH> {
                     setArg(call_calculate_new_vl_260, 1, uimm);
                     setArg(call_calculate_new_vl_260, 2, calculate_new_vl_260_arg1);
                     setRet(call_calculate_new_vl_260, 0, ret_val_calculate_new_vl_260);
-                    mov(cc, get_ptr_for(jh, traits::X0+ rd),
-                          load_reg_from_mem(jh, traits::vl));
+                    if(rd!=0){
+                        mov(cc, get_ptr_for(jh, traits::X0+ rd),
+                              load_reg_from_mem(jh, traits::vl));
+                    }
                     auto tmp261 =  get_reg_Gp(cc, 32, false);
                     mov(cc, tmp261, gen_ext(cc, 0, 32, false));
                     write_reg_to_mem(jh, tmp261, traits::vstart);
diff --git a/src/vm/asmjit/vm_rv64gcv.cpp b/src/vm/asmjit/vm_rv64gcv.cpp
index 600f51d..912d3a2 100644
--- a/src/vm/asmjit/vm_rv64gcv.cpp
+++ b/src/vm/asmjit/vm_rv64gcv.cpp
@@ -14431,8 +14431,10 @@ template <typename ARCH> class vm_impl : public iss::asmjit::vm_base<ARCH> {
                     setArg(call_calculate_new_vl_296, 1, uimm);
                     setArg(call_calculate_new_vl_296, 2, calculate_new_vl_296_arg1);
                     setRet(call_calculate_new_vl_296, 0, ret_val_calculate_new_vl_296);
-                    mov(cc, get_ptr_for(jh, traits::X0+ rd),
-                          load_reg_from_mem(jh, traits::vl));
+                    if(rd!=0){
+                        mov(cc, get_ptr_for(jh, traits::X0+ rd),
+                              load_reg_from_mem(jh, traits::vl));
+                    }
                     auto tmp297 =  get_reg_Gp(cc, 64, false);
                     mov(cc, tmp297, gen_ext(cc, 0, 64, false));
                     write_reg_to_mem(jh, tmp297, traits::vstart);
diff --git a/src/vm/interp/vm_rv32gcv.cpp b/src/vm/interp/vm_rv32gcv.cpp
index 75c5358..d0499c4 100644
--- a/src/vm/interp/vm_rv32gcv.cpp
+++ b/src/vm/interp/vm_rv32gcv.cpp
@@ -5942,7 +5942,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         else {
                                             uint16_t VLMAX = (uint16_t)(1 << ((uint16_t)(get_pow(traits::VLEN)) + (int16_t)(get_lmul_pow()) - (uint16_t)(get_sew_pow()))) & ~1;
                                             *vl = calculate_new_vl(uimm, VLMAX);
-                                            *(X+rd) = *vl;
+                                            if(rd != 0) {
+                                                *(X+rd) = *vl;
+                                            }
                                             *vstart = 0;
                                         }
                                     }
diff --git a/src/vm/interp/vm_rv64gcv.cpp b/src/vm/interp/vm_rv64gcv.cpp
index 7118e6f..738a282 100644
--- a/src/vm/interp/vm_rv64gcv.cpp
+++ b/src/vm/interp/vm_rv64gcv.cpp
@@ -7285,7 +7285,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         else {
                                             uint16_t VLMAX = (uint16_t)(1 << ((uint16_t)(get_pow(traits::VLEN)) + (int16_t)(get_lmul_pow()) - (uint16_t)(get_sew_pow()))) & ~1;
                                             *vl = calculate_new_vl(uimm, VLMAX);
-                                            *(X+rd) = *vl;
+                                            if(rd != 0) {
+                                                *(X+rd) = *vl;
+                                            }
                                             *vstart = 0;
                                         }
                                     }

From 1801efccd809fbcad5efffa4f90499cfa6c85a3b Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Mon, 27 Oct 2025 18:07:56 +0100
Subject: [PATCH 05/77] corrects vlenb behavior

---
 src/iss/arch/riscv_hart_common.h | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/src/iss/arch/riscv_hart_common.h b/src/iss/arch/riscv_hart_common.h
index f61713b..e55de95 100644
--- a/src/iss/arch/riscv_hart_common.h
+++ b/src/iss/arch/riscv_hart_common.h
@@ -854,27 +854,27 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
     }
 
     iss::status read_vlenb(unsigned addr, reg_t& val) {
-        val = csr[vlenb];
+        val = traits<BASE>::V_REGS_SIZE;
         return iss::Ok;
     }
 
     priv_if<reg_t> get_priv_if() {
         return priv_if<reg_t>{.read_csr = [this](unsigned addr, reg_t& val) -> iss::status { return read_csr(addr, val); },
-                              .write_csr = [this](unsigned addr, reg_t val) -> iss::status { return write_csr(addr, val); },
-                              .exec_htif = [this](uint8_t const* data, unsigned length) -> iss::status { return execute_htif(data, length); },
-                              .raise_trap =
-                                  [this](uint16_t trap_id, uint16_t cause, reg_t fault_data) {
-                                      this->reg.trap_state = 0x80ULL << 24 | (cause << 16) | trap_id;
-                                      this->fault_data = fault_data;
-                                  },
-                              .csr_rd_cb{this->csr_rd_cb},
-                              .csr_wr_cb{csr_wr_cb},
-                              .state{this->state},
-                              .PRIV{this->reg.PRIV},
-                              .PC{this->reg.PC},
-                              .tohost{this->tohost},
-                              .fromhost{this->fromhost},
-                              .max_irq{mcause_max_irq}};
+            .write_csr = [this](unsigned addr, reg_t val) -> iss::status { return write_csr(addr, val); },
+            .exec_htif = [this](uint8_t const* data, unsigned length) -> iss::status { return execute_htif(data, length); },
+            .raise_trap =
+                [this](uint16_t trap_id, uint16_t cause, reg_t fault_data) {
+                    this->reg.trap_state = 0x80ULL << 24 | (cause << 16) | trap_id;
+                    this->fault_data = fault_data;
+                },
+            .csr_rd_cb{this->csr_rd_cb},
+            .csr_wr_cb{csr_wr_cb},
+            .state{this->state},
+            .PRIV{this->reg.PRIV},
+            .PC{this->reg.PC},
+            .tohost{this->tohost},
+            .fromhost{this->fromhost},
+            .max_irq{mcause_max_irq}};
     }
 
     iss::status execute_htif(uint8_t const* data, unsigned length) {

From 504135f38eada6368385e577da9bcabe2ce2fdf2 Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Wed, 29 Oct 2025 12:16:24 +0100
Subject: [PATCH 06/77] adds cci param to allow dumping of post run stats

---
 src/sysc/core_complex.cpp | 6 ++++++
 src/sysc/core_complex.h   | 4 ++++
 2 files changed, 10 insertions(+)

diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index 728048e..6c77742 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -260,6 +260,12 @@ template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::init() {
 template <unsigned int BUSWIDTH> core_complex<BUSWIDTH>::~core_complex() {
     for(auto* p : plugin_list)
         delete p;
+    if(post_run_stats.get_value()) {
+        auto instr_if = vm->get_arch()->get_instrumentation_if();
+        auto instrs = instr_if->get_instr_count();
+        auto cycles = instr_if->get_total_cycles();
+        SCCINFO(SCMOD) << "Ran " << instrs << " instructions in " << cycles << " cycles";
+    }
 }
 
 template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::trace(sc_trace_file* trf) const {}
diff --git a/src/sysc/core_complex.h b/src/sysc/core_complex.h
index ac4f01b..910f836 100644
--- a/src/sysc/core_complex.h
+++ b/src/sysc/core_complex.h
@@ -121,6 +121,8 @@ template <unsigned int BUSWIDTH = scc::LT> class core_complex : public sc_core::
 
     cci::cci_param<std::string> plugins{"plugins", ""};
 
+    cci::cci_param<bool> post_run_stats{"post_run_stats", false};
+
     core_complex(sc_core::sc_module_name const& name);
 
 #else
@@ -146,6 +148,8 @@ template <unsigned int BUSWIDTH = scc::LT> class core_complex : public sc_core::
 
     scml_property<std::string> plugins{"plugins", ""};
 
+    scml_property<bool> post_run_stats{"post_run_stats", false};
+
     core_complex(sc_core::sc_module_name const& name)
     : sc_module(name)
     , local_irq_i{"local_irq_i", 16}

From 24b3597007a602deed878406e05dca4a91b2461a Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Wed, 5 Nov 2025 22:23:18 +0100
Subject: [PATCH 07/77] enables disass logger for trap information output

---
 src/main.cpp | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/main.cpp b/src/main.cpp
index ca6a09e..6fc75a6 100644
--- a/src/main.cpp
+++ b/src/main.cpp
@@ -102,16 +102,19 @@ int main(int argc, char* argv[]) {
     LOGGER(DEFAULT)::print_time() = false;
     LOGGER(connection)::print_time() = false;
     LOGGER(dbt_rise_iss)::print_time() = false;
+    LOGGER(disass)::print_time() = false;
     auto l = logging::as_log_level(clim["verbose"].as<int>());
     LOGGER(DEFAULT)::reporting_level() = l;
     LOGGER(connection)::reporting_level() = l;
     LOGGER(dbt_rise_iss)::reporting_level() = l;
+    LOGGER(disass)::reporting_level() = l;
     if(clim.count("logfile")) {
         // configure the connection logger
         auto f = fopen(clim["logfile"].as<std::string>().c_str(), "w");
         LOG_OUTPUT(DEFAULT)::stream() = f;
         LOG_OUTPUT(connection)::stream() = f;
         LOG_OUTPUT(dbt_rise_iss)::stream() = f;
+        LOG_OUTPUT(disass)::stream() = f;
     }
 
     std::vector<iss::vm_plugin*> plugin_list;

From dba9a81450788cfba7c39edcfd16f31d520ede5b Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Thu, 6 Nov 2025 12:55:36 +0100
Subject: [PATCH 08/77] adds instance based logger in riscv_hart_common and SC
 adapter

---
 src/iss/arch/riscv_hart_common.h | 66 ++++++++++++++++++--------------
 src/sysc/core2sc_adapter.h       | 54 +++++++++++++++++++++++++-
 2 files changed, 89 insertions(+), 31 deletions(-)

diff --git a/src/iss/arch/riscv_hart_common.h b/src/iss/arch/riscv_hart_common.h
index e55de95..eeec825 100644
--- a/src/iss/arch/riscv_hart_common.h
+++ b/src/iss/arch/riscv_hart_common.h
@@ -37,6 +37,7 @@
 
 #include "mstatus.h"
 #include "util/delegate.h"
+#include "util/logging.h"
 #include <array>
 #include <cstdint>
 #include <elfio/elf_types.hpp>
@@ -52,7 +53,7 @@
 #include <sstream>
 #include <string>
 #include <unordered_map>
-#include <util/logging.h>
+#include <util/instance_logger.h>
 #include <util/sparse_array.h>
 
 #if defined(__GNUC__)
@@ -434,7 +435,7 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
 
     ~riscv_hart_common() {
         if(io_buf.str().length()) {
-            CPPLOG(INFO) << "tohost send '" << io_buf.str() << "'";
+            ILOG(isslogger, logging::INFO, fmt::format("tohost send '{}'", io_buf.str()));
         }
     }
 
@@ -446,22 +447,22 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
 
     void set_semihosting_callback(semihosting_cb_t<reg_t> cb) { semihosting_cb = cb; };
 
-    std::pair<uint64_t, bool> load_file(std::string name, int type) {
+    std::pair<uint64_t, bool> load_file(std::string const& name, int type) override {
         return std::make_pair(entry_address, read_elf_file(name, sizeof(reg_t) == 4 ? ELFIO::ELFCLASS32 : ELFIO::ELFCLASS64));
     }
 
-    bool read_elf_file(std::string name, uint8_t expected_elf_class) {
+    bool read_elf_file(std::string const& name, uint8_t expected_elf_class) {
         // Create elfio reader
         ELFIO::elfio reader;
         // Load ELF data
         if(reader.load(name)) {
             // check elf properties
             if(reader.get_class() != expected_elf_class) {
-                CPPLOG(ERR) << "ISA missmatch, selected XLEN does not match supplied file ";
+                ILOG(isslogger, logging::ERR, "ISA missmatch, selected XLEN does not match supplied file ");
                 return false;
             }
             if(reader.get_type() != ELFIO::ET_EXEC && reader.get_type() != ELFIO::ET_DYN) {
-                CPPLOG(ERR) << "Input is neither an executable nor a pie executable (dyn)";
+                ILOG(isslogger, logging::ERR, "Input is neither an executable nor a pie executable (dyn)");
                 return false;
             }
             if(reader.get_machine() != ELFIO::EM_RISCV)
@@ -475,7 +476,8 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
                     auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM,
                                            pseg->get_physical_address(), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
                     if(res != iss::Ok)
-                        CPPLOG(ERR) << "problem writing " << fsize << " bytes to 0x" << std::hex << pseg->get_physical_address();
+                        ILOG(isslogger, logging::ERR,
+                             fmt::format("problem writing {} bytes to 0x{:x}", fsize, pseg->get_physical_address()));
                 }
             }
             const auto sym_sec = reader.sections[".symtab"];
@@ -494,7 +496,7 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
                     if(name != "") {
                         this->symbol_table[name] = value;
 #ifndef NDEBUG
-                        CPPLOG(TRACE) << "Found Symbol " << name;
+                        ILOG(isslogger, logging::TRACE, fmt::format("Found Symbol {}", name));
 #endif
                     }
                 }
@@ -516,13 +518,13 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
         uint64_t len = loaded_payload[3];
         std::vector<char> buf(len);
         if(aif->read(address_type::PHYSICAL, access_type::DEBUG_READ, mem_type, buf_ptr, len, reinterpret_cast<uint8_t*>(buf.data()))) {
-            CPPLOG(ERR) << "SYS_WRITE buffer read went wrong";
+            ILOG(isslogger, logging::ERR, "SYS_WRITE buffer read went wrong");
             return iss::Err;
         }
         // we disregard the fd and just log to stdout
         for(size_t i = 0; i < len; i++) {
             if(buf[i] == '\n' || buf[i] == '\0') {
-                CPPLOG(INFO) << "tohost send '" << io_buf.str() << "'";
+                ILOG(isslogger, logging::INFO, fmt::format("tohost send '{}'", io_buf.str()));
                 io_buf.str("");
             } else
                 io_buf << buf[i];
@@ -532,7 +534,7 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
         uint8_t ret_val = 1;
         if(fromhost != std::numeric_limits<uint64_t>::max())
             if(aif->write(address_type::PHYSICAL, access_type::DEBUG_WRITE, mem_type, fromhost, 1, &ret_val)) {
-                CPPLOG(ERR) << "Fromhost write went wrong";
+                ILOG(isslogger, logging::ERR, "Fromhost write went wrong");
                 return iss::Err;
             }
         return iss::Ok;
@@ -543,11 +545,9 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
     constexpr reg_t get_pc_mask() { return has_compressed() ? (reg_t)~1 : (reg_t)~3; }
 
     void disass_output(uint64_t pc, const std::string instr) override {
-        // NSCLOG(INFO, LOGCAT) << fmt::format("0x{:016x}    {:40} [p:{};s:0x{:x};c:{}]", pc, instr, lvl[this->reg.PRIV],
-        // (reg_t)state.mstatus,
-        //                                     this->reg.cycle + cycle_offset);
-        NSCLOG(INFO, LOGCAT) << fmt::format("0x{:016x}    {:40} [p:{};c:{}]", pc, instr, lvl[this->reg.PRIV],
-                                            this->reg.cycle + cycle_offset);
+        if(::logging ::INFO <= disasslogger.get_log_level())
+            ILOG(disasslogger, ::logging ::INFO,
+                 fmt::format("0x{:016x}    {:40} [p:{};c:{}]", pc, instr, lvl[this->reg.PRIV], this->reg.cycle + cycle_offset));
     };
 
     void register_csr(unsigned addr, rd_csr_f f) { csr_rd_cb[addr] = f; }
@@ -859,7 +859,8 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
     }
 
     priv_if<reg_t> get_priv_if() {
-        return priv_if<reg_t>{.read_csr = [this](unsigned addr, reg_t& val) -> iss::status { return read_csr(addr, val); },
+        return priv_if<reg_t>{
+            .read_csr = [this](unsigned addr, reg_t& val) -> iss::status { return read_csr(addr, val); },
             .write_csr = [this](unsigned addr, reg_t val) -> iss::status { return write_csr(addr, val); },
             .exec_htif = [this](uint8_t const* data, unsigned length) -> iss::status { return execute_htif(data, length); },
             .raise_trap =
@@ -885,32 +886,37 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
         // Extract Command (bits 55:48)
         uint8_t command = traits<BASE>::XLEN == 32 ? 0 : (cur_data >> 48) & 0xFF;
         // Extract payload (bits 47:0)
-        uint64_t payload_addr = cur_data & 0xFFFFFFFFFFFFULL;
-        if(payload_addr & 1) {
-            CPPLOG(FATAL) << "this->tohost value is 0x" << std::hex << payload_addr << std::dec << " (" << payload_addr
-                          << "), stopping simulation";
+        uint64_t payload_data = cur_data & 0xFFFFFFFFFFFFULL;
+        if(payload_data & 1) {
+            if(payload_data & ~1)
+                ILOG(isslogger, logging::FATAL,
+                     fmt::format("this->tohost value is 0x{:x} ({}), stopping simulation", payload_data, payload_data));
+            else
+                ILOG(isslogger, logging::INFO,
+                     fmt::format("this->tohost value is 0x{:x} ({}), stopping simulation", payload_data, payload_data));
             this->reg.trap_state = std::numeric_limits<uint32_t>::max();
-            this->interrupt_sim = payload_addr;
+            this->interrupt_sim = payload_data;
             return iss::Ok;
         } else if(device == 0 && command == 0) {
             std::array<uint64_t, 8> loaded_payload;
-            if(memory.rd_mem(access_type::DEBUG_READ, payload_addr, 8 * sizeof(uint64_t),
+            if(memory.rd_mem(access_type::DEBUG_READ, payload_data, 8 * sizeof(uint64_t),
                              reinterpret_cast<uint8_t*>(loaded_payload.data())) == iss::Err)
-                CPPLOG(ERR) << "Syscall read went wrong";
+                ILOG(isslogger, logging::ERR, "Syscall read went wrong");
             uint64_t syscall_num = loaded_payload.at(0);
             if(syscall_num == 64) { // SYS_WRITE
                 return this->execute_sys_write(this, loaded_payload, traits<BASE>::MEM);
             } else {
-                CPPLOG(ERR) << "this->tohost syscall with number 0x" << std::hex << syscall_num << std::dec << " (" << syscall_num
-                            << ") not implemented";
+                ILOG(isslogger, logging::ERR,
+                     fmt::format("this->tohost syscall with number 0x{:x} ({}) not implemented", syscall_num, syscall_num));
                 this->reg.trap_state = std::numeric_limits<uint32_t>::max();
-                this->interrupt_sim = payload_addr;
+                this->interrupt_sim = payload_data;
                 return iss::Ok;
             }
         } else {
-            CPPLOG(ERR) << "this->tohost functionality not implemented for device " << device << " and command " << command;
+            ILOG(isslogger, logging::ERR,
+                 fmt::format("this->tohost functionality not implemented for device {} and command {}", device, command));
             this->reg.trap_state = std::numeric_limits<uint32_t>::max();
-            this->interrupt_sim = payload_addr;
+            this->interrupt_sim = payload_data;
             return iss::Ok;
         }
     }
@@ -927,6 +933,8 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
     void set_irq_num(unsigned i) { mcause_max_irq = std::max(1u << util::ilog2(i), 16u); }
 
 protected:
+    util::InstanceLogger<logging::disass> disasslogger;
+    util::InstanceLogger<logging::dbt_rise_iss> isslogger;
     hart_state<reg_t> state;
 
     mem::memory_if memory;
diff --git a/src/sysc/core2sc_adapter.h b/src/sysc/core2sc_adapter.h
index 368a5ac..00fc052 100644
--- a/src/sysc/core2sc_adapter.h
+++ b/src/sysc/core2sc_adapter.h
@@ -36,13 +36,17 @@
 #define _SYSC_CORE2SC_ADAPTER_H_
 
 #include "core_complex.h"
+#include "iss/log_categories.h"
 #include "sc2core_if.h"
+#include "util/delegate.h"
+#include "util/logging.h"
 #include <iostream>
 #include <iss/arch/riscv_hart_common.h>
 #include <iss/iss.h>
 #include <iss/mem/memory_if.h>
 #include <iss/vm_types.h>
 #include <scc/report.h>
+#include <util/instance_logger.h>
 #include <util/ities.h>
 namespace sysc {
 template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if {
@@ -51,6 +55,7 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
     using core = typename PLAT::core;
     using reg_t = typename PLAT::reg_t;
     using phys_addr_t = typename PLAT::phys_addr_t;
+
     core2sc_adapter(sysc::riscv::core_complex_if* owner)
     : owner(owner) {
         this->csr_rd_cb[iss::arch::time] = MK_CSR_RD_CB(read_time);
@@ -66,6 +71,11 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
         this->local_irq = util::delegate<void(short, bool)>::from<this_class, &this_class::_local_irq>(this);
         this->register_csr_rd = util::delegate<void(unsigned, rd_csr_f)>::from<this_class, &this_class::_register_csr_rd>(this);
         this->register_csr_wr = util::delegate<void(unsigned, wr_csr_f)>::from<this_class, &this_class::_register_csr_wr>(this);
+
+        log_delegate.log = util::delegate<util::LoggerDelegate::delegate_fn>(*this, &core2sc_adapter::log);
+        log_delegate.level = static_cast<logging::log_level>(scc::get_logging_level());
+        this->disasslogger.set_logger(log_delegate);
+        this->isslogger.set_logger(log_delegate);
     }
 
     virtual ~core2sc_adapter() {}
@@ -82,14 +92,53 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
 
     iss::sync_type needed_sync() const { return iss::PRE_SYNC; }
 
+    void log(logging::log_level lvl, std::string const& msg_type, std::string const& msg, unsigned line, char const* file) {
+        switch(lvl) {
+        case logging::log_level::FATAL:
+            ::scc ::ScLogger<::sc_core ::SC_FATAL>(file, line, sc_core ::SC_MEDIUM).type(owner->hier_name()).get()
+                << "[" << msg_type << "] " << msg;
+            break;
+        case logging::log_level::ERR:
+            ::scc ::ScLogger<::sc_core ::SC_ERROR>(file, line, sc_core ::SC_MEDIUM).type(owner->hier_name()).get() << msg;
+            break;
+        case logging::log_level::WARN:
+            if(::scc ::get_log_verbosity(msg_type) >= sc_core ::SC_LOW)
+                ::scc ::ScLogger<::sc_core ::SC_WARNING>(file, line, sc_core ::SC_MEDIUM).type(owner->hier_name()).get()
+                    << "[" << msg_type << "] " << msg;
+            break;
+        case logging::log_level::INFO:
+            if(::scc ::get_log_verbosity(msg_type) >= sc_core ::SC_MEDIUM)
+                ::scc ::ScLogger<::sc_core ::SC_INFO>(file, line, sc_core ::SC_MEDIUM).type(owner->hier_name()).get()
+                    << "[" << msg_type << "] " << msg;
+            break;
+        case logging::log_level::DEBUG:
+            if(::scc ::get_log_verbosity(msg_type) >= sc_core ::SC_HIGH)
+                ::scc ::ScLogger<::sc_core ::SC_INFO>(file, line, sc_core ::SC_HIGH).type(owner->hier_name()).get()
+                    << "[" << msg_type << "] " << msg;
+            break;
+        case logging::log_level::TRACE:
+            if(::scc ::get_log_verbosity(msg_type) >= sc_core ::SC_FULL)
+                ::scc ::ScLogger<::sc_core ::SC_INFO>(file, line, sc_core ::SC_FULL).type(owner->hier_name()).get()
+                    << "[" << msg_type << "] " << msg;
+            break;
+        case logging::log_level::TRACEALL:
+            if(::scc ::get_log_verbosity(msg_type) >= sc_core ::SC_DEBUG)
+                ::scc ::ScLogger<::sc_core ::SC_INFO>(file, line, sc_core ::SC_DEBUG).type(owner->hier_name()).get()
+                    << "[" << msg_type << "] " << msg;
+            break;
+        default:
+            break;
+        }
+    }
+
     void disass_output(uint64_t pc, const std::string instr) {
         static constexpr std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
         if(!owner->disass_output(pc, instr)) {
             std::stringstream s;
             s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0') << std::setw(sizeof(reg_t) * 2)
               << (reg_t)this->state.mstatus << std::dec << ";c:" << this->reg.icount + this->cycle_offset << "]";
-            SCCDEBUG(owner->hier_name()) << "disass: " << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc
-                                         << "\t\t" << std::setw(40) << std::setfill(' ') << std::left << instr << s.str();
+            SCCINFO(owner->hier_name()) << "[disass] " << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc
+                                        << "\t\t" << std::setw(40) << std::setfill(' ') << std::left << instr << s.str();
         }
     };
 
@@ -231,6 +280,7 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
     }
 
     sysc::riscv::core_complex_if* const owner{nullptr};
+    util::LoggerDelegate log_delegate;
     sc_core::sc_event wfi_evt;
     unsigned to_host_wr_cnt = 0;
     bool first{true};

From beb2b8fcdb3837315b5544b985029f4593e61cf9 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Thu, 6 Nov 2025 12:46:55 +0100
Subject: [PATCH 09/77] adds hello_world example for riscv-sim

---
 contrib/fw/.gitignore                     |   1 +
 contrib/fw/hello-world/.gitignore         |   5 +++++
 contrib/fw/hello-world/Makefile           |  19 +++++++++++++++++
 contrib/fw/hello-world/hello.c            |  24 ++++++++++++++++++++++
 contrib/fw/hello-world/prebuilt/hello.elf | Bin 0 -> 53996 bytes
 5 files changed, 49 insertions(+)
 create mode 100644 contrib/fw/.gitignore
 create mode 100644 contrib/fw/hello-world/.gitignore
 create mode 100644 contrib/fw/hello-world/Makefile
 create mode 100644 contrib/fw/hello-world/hello.c
 create mode 100755 contrib/fw/hello-world/prebuilt/hello.elf

diff --git a/contrib/fw/.gitignore b/contrib/fw/.gitignore
new file mode 100644
index 0000000..105c692
--- /dev/null
+++ b/contrib/fw/.gitignore
@@ -0,0 +1 @@
+/bsp
diff --git a/contrib/fw/hello-world/.gitignore b/contrib/fw/hello-world/.gitignore
new file mode 100644
index 0000000..39c65a2
--- /dev/null
+++ b/contrib/fw/hello-world/.gitignore
@@ -0,0 +1,5 @@
+/*.elf
+/*.dis
+/*.map
+/*.a
+/*.o
diff --git a/contrib/fw/hello-world/Makefile b/contrib/fw/hello-world/Makefile
new file mode 100644
index 0000000..d8c8601
--- /dev/null
+++ b/contrib/fw/hello-world/Makefile
@@ -0,0 +1,19 @@
+
+TARGET  = hello
+C_SRCS  = $(wildcard *.c) 
+HEADERS = $(wildcard *.h)
+CFLAGS += -Og -g 
+
+BOARD=iss
+LINK_TARGET=link
+RISCV_ARCH:=rv32imc
+RISCV_ABI:=ilp32
+#RISCV_ARCH:=rv64imc
+#RISCV_ABI:=lp64
+LDFLAGS := -g -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI)
+
+compiler := $(shell which riscv64-unknown-elf-gcc)
+TOOL_DIR=$(dir $(compiler))
+
+BSP_BASE ?= ../bsp
+include $(BSP_BASE)/env/common-gcc.mk
diff --git a/contrib/fw/hello-world/hello.c b/contrib/fw/hello-world/hello.c
new file mode 100644
index 0000000..91bf133
--- /dev/null
+++ b/contrib/fw/hello-world/hello.c
@@ -0,0 +1,24 @@
+#include <stdint.h>
+#include <stdio.h>
+#include <unistd.h>
+
+#include <platform.h>
+#include "encoding.h"
+
+int factorial(int i){
+
+	volatile int result = 1;
+	for (int ii = 1; ii <= i; ii++) {
+		result = result * ii;
+	}
+	return result;
+
+}
+
+int main()
+{
+	volatile int result = factorial (10);
+	printf("Factorial is %d\n", result);
+	printf("End of execution");
+	return 0;
+}
diff --git a/contrib/fw/hello-world/prebuilt/hello.elf b/contrib/fw/hello-world/prebuilt/hello.elf
new file mode 100755
index 0000000000000000000000000000000000000000..95b04ade9f03c1c844f9a23cdc71b5225e71823a
GIT binary patch
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HcmV?d00001


From a6fa46361214b043bc3b572e1840024a05f1747c Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Thu, 6 Nov 2025 17:00:07 +0100
Subject: [PATCH 10/77] changes logging to use instance logger of SCC/common

---
 src/iss/arch/riscv_hart_common.h | 21 +++++++++------
 src/iss/arch/riscv_hart_m_p.h    | 42 +++++++++++++++--------------
 src/iss/arch/riscv_hart_msu_vp.h | 45 +++++++++++++++++---------------
 src/iss/arch/riscv_hart_mu_p.h   | 45 +++++++++++++++++---------------
 src/sysc/core2sc_adapter.h       |  8 ++----
 src/sysc/core_complex.cpp        |  2 +-
 src/sysc/core_complex.h          |  2 +-
 src/sysc/core_complex_if.h       |  2 +-
 8 files changed, 89 insertions(+), 78 deletions(-)

diff --git a/src/iss/arch/riscv_hart_common.h b/src/iss/arch/riscv_hart_common.h
index eeec825..9efa5ee 100644
--- a/src/iss/arch/riscv_hart_common.h
+++ b/src/iss/arch/riscv_hart_common.h
@@ -36,8 +36,6 @@
 #define _RISCV_HART_COMMON
 
 #include "mstatus.h"
-#include "util/delegate.h"
-#include "util/logging.h"
 #include <array>
 #include <cstdint>
 #include <elfio/elf_types.hpp>
@@ -53,7 +51,10 @@
 #include <sstream>
 #include <string>
 #include <unordered_map>
+#include <util/delegate.h>
 #include <util/instance_logger.h>
+#include <util/ities.h>
+#include <util/logging.h>
 #include <util/sparse_array.h>
 
 #if defined(__GNUC__)
@@ -544,10 +545,13 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
 
     constexpr reg_t get_pc_mask() { return has_compressed() ? (reg_t)~1 : (reg_t)~3; }
 
-    void disass_output(uint64_t pc, const std::string instr) override {
-        if(::logging ::INFO <= disasslogger.get_log_level())
-            ILOG(disasslogger, ::logging ::INFO,
-                 fmt::format("0x{:016x}    {:40} [p:{};c:{}]", pc, instr, lvl[this->reg.PRIV], this->reg.cycle + cycle_offset));
+    void disass_output(uint64_t pc, std::string const& instr) override {
+        static CONSTEXPR char const* fmt_str =
+            sizeof(reg_t) == 4 ? "0x{:08x}    {:40} [p:{};s:{:08};i:{};c:{}]" : "0x{:016x}    {:40} [p:{};s:{:016};i:{};c:{}]";
+        if(::logging::DEBUG <= disasslogger.get_log_level())
+            ILOG(disasslogger, ::logging::DEBUG,
+                 fmt::format(fmt_str, pc, instr, lvl[this->reg.PRIV], (reg_t)this->state.mstatus, this->reg.icount,
+                             this->reg.cycle + cycle_offset));
     };
 
     void register_csr(unsigned addr, rd_csr_f f) { csr_rd_cb[addr] = f; }
@@ -888,12 +892,13 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
         // Extract payload (bits 47:0)
         uint64_t payload_data = cur_data & 0xFFFFFFFFFFFFULL;
         if(payload_data & 1) {
-            if(payload_data & ~1)
+            if(payload_data & ~1) {
                 ILOG(isslogger, logging::FATAL,
                      fmt::format("this->tohost value is 0x{:x} ({}), stopping simulation", payload_data, payload_data));
-            else
+            } else {
                 ILOG(isslogger, logging::INFO,
                      fmt::format("this->tohost value is 0x{:x} ({}), stopping simulation", payload_data, payload_data));
+            }
             this->reg.trap_state = std::numeric_limits<uint32_t>::max();
             this->interrupt_sim = payload_data;
             return iss::Ok;
diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h
index ef7f96a..c3ae9e6 100644
--- a/src/iss/arch/riscv_hart_m_p.h
+++ b/src/iss/arch/riscv_hart_m_p.h
@@ -166,11 +166,11 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read(const address_type type, co
                                                      const uint64_t addr, const unsigned length, uint8_t* const data) {
 #ifndef NDEBUG
     if(access && iss::access_type::DEBUG) {
-        CPPLOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
+        ILOG(isslogger, logging::TRACEALL, fmt::format("debug read of {} bytes @addr 0x{:x}", length, addr));
     } else if(is_fetch(access)) {
-        CPPLOG(TRACEALL) << "fetch of " << length << " bytes  @addr 0x" << std::hex << addr;
+        ILOG(isslogger, logging::TRACEALL, fmt::format("fetch of {} bytes @addr 0x{:x}", length, addr));
     } else {
-        CPPLOG(TRACE) << "read of " << length << " bytes  @addr 0x" << std::hex << addr;
+        ILOG(isslogger, logging::TRACEALL, fmt::format("read of {} bytes @addr 0x{:x}", length, addr));
     }
 #endif
     try {
@@ -252,23 +252,23 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
     const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
     switch(length) {
     case 8:
-        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x"
-                      << std::hex << addr;
+        ILOG(isslogger, logging::TRACEALL,
+             fmt::format("{}write of {} bytes (0x{:x}) @addr 0x{:x}", prefix, length, *reinterpret_cast<const uint64_t*>(&data[0]), addr));
         break;
     case 4:
-        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x"
-                      << std::hex << addr;
+        ILOG(isslogger, logging::TRACEALL,
+             fmt::format("{}write of {} bytes (0x{:x}) @addr 0x{:x}", prefix, length, *reinterpret_cast<const uint32_t*>(&data[0]), addr));
         break;
     case 2:
-        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x"
-                      << std::hex << addr;
+        ILOG(isslogger, logging::TRACEALL,
+             fmt::format("{}write of {} bytes (0x{:x}) @addr 0x{:x}", prefix, length, *reinterpret_cast<const uint16_t*>(&data[0]), addr));
         break;
     case 1:
-        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x"
-                      << std::hex << addr;
+        ILOG(isslogger, logging::TRACEALL,
+             fmt::format("{}write of {} bytes (0x{:x}) @addr 0x{:x}", prefix, length, (uint16_t)data[0], addr));
         break;
     default:
-        CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr 0x" << std::hex << addr;
+        ILOG(isslogger, logging::TRACEALL, fmt::format("{}write of {} bytes @addr 0x{:x}", prefix, length, addr));
     }
 #endif
     try {
@@ -452,8 +452,7 @@ uint64_t riscv_hart_m_p<BASE, FEAT, LOGCAT>::enter_trap(uint64_t flags, uint64_t
 #else
                     sprintf(buffer.data(), "0x%016lx", addr);
 #endif
-                    NSCLOG(INFO, LOGCAT) << "Semihosting call at address " << buffer.data() << " occurred ";
-
+                    ILOG(disasslogger, logging::INFO, fmt::format("Semihosting call at address {} occurred ", buffer.data()));
                     this->semihosting_cb(this, &(this->reg.X10) /*a0*/, &(this->reg.X11) /*a1*/);
                     return this->reg.NEXT_PC;
                 }
@@ -508,10 +507,15 @@ uint64_t riscv_hart_m_p<BASE, FEAT, LOGCAT>::enter_trap(uint64_t flags, uint64_t
 #else
     sprintf(buffer.data(), "0x%016lx", addr);
 #endif
-    if((flags & 0xffffffff) != 0xffffffff)
-        NSCLOG(DEBUG, LOGCAT) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
-                              << (trap_id ? this->irq_str[cause] : this->trap_str[cause]) << "' (" << cause << ")" << " at address "
-                              << buffer.data() << " occurred";
+    if((flags & 0xffffffff) != 0xffffffff) {
+        if(trap_id) {
+            ILOG(disasslogger, logging::DEBUG,
+                 fmt::format("Interrupt with cause '{}' ({}) occurred  at address {}", this->irq_str[cause], cause, buffer.data()));
+        } else {
+            ILOG(disasslogger, logging::DEBUG,
+                 fmt::format("Trap with cause '{}' ({}) occurred  at address {}", this->trap_str[cause], cause, buffer.data()));
+        }
+    }
     // reset trap state
     this->reg.PRIV = new_priv;
     this->reg.trap_state = 0;
@@ -523,7 +527,7 @@ template <typename BASE, features_e FEAT, typename LOGCAT> uint64_t riscv_hart_m
     this->state.mstatus.MPIE = 1;
     // sets the pc to the value stored in the x epc register.
     this->reg.NEXT_PC = this->csr[mepc] & this->get_pc_mask();
-    NSCLOG(INFO, LOGCAT) << "Executing xRET";
+    ILOG(disasslogger, logging::DEBUG, "Executing xRET");
     check_interrupt();
     this->reg.trap_state = this->reg.pending_trap;
     return this->reg.NEXT_PC;
diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h
index f398e75..33fbfa6 100644
--- a/src/iss/arch/riscv_hart_msu_vp.h
+++ b/src/iss/arch/riscv_hart_msu_vp.h
@@ -243,11 +243,11 @@ iss::status riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::read(const address_type type,
                                                         const uint64_t addr, const unsigned length, uint8_t* const data) {
 #ifndef NDEBUG
     if(access && iss::access_type::DEBUG) {
-        CPPLOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
+        ILOG(isslogger, logging::TRACEALL, fmt::format("debug read of {} bytes @addr 0x{:x}", length, addr));
     } else if(is_fetch(access)) {
-        CPPLOG(TRACEALL) << "fetch of " << length << " bytes  @addr 0x" << std::hex << addr;
+        ILOG(isslogger, logging::TRACEALL, fmt::format("fetch of {} bytes @addr 0x{:x}", length, addr));
     } else {
-        CPPLOG(TRACE) << "read of " << length << " bytes  @addr 0x" << std::hex << addr;
+        ILOG(isslogger, logging::TRACEALL, fmt::format("read of {} bytes @addr 0x{:x}", length, addr));
     }
 #endif
     try {
@@ -332,23 +332,23 @@ iss::status riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::write(const address_type type
     const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
     switch(length) {
     case 8:
-        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x"
-                      << std::hex << addr;
+        ILOG(isslogger, logging::TRACEALL,
+             fmt::format("{}write of {} bytes (0x{:x}) @addr 0x{:x}", prefix, length, *reinterpret_cast<const uint64_t*>(&data[0]), addr));
         break;
     case 4:
-        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x"
-                      << std::hex << addr;
+        ILOG(isslogger, logging::TRACEALL,
+             fmt::format("{}write of {} bytes (0x{:x}) @addr 0x{:x}", prefix, length, *reinterpret_cast<const uint32_t*>(&data[0]), addr));
         break;
     case 2:
-        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x"
-                      << std::hex << addr;
+        ILOG(isslogger, logging::TRACEALL,
+             fmt::format("{}write of {} bytes (0x{:x}) @addr 0x{:x}", prefix, length, *reinterpret_cast<const uint16_t*>(&data[0]), addr));
         break;
     case 1:
-        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x"
-                      << std::hex << addr;
+        ILOG(isslogger, logging::TRACEALL,
+             fmt::format("{}write of {} bytes (0x{:x}) @addr 0x{:x}", prefix, length, (uint16_t)data[0], addr));
         break;
     default:
-        CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
+        ILOG(isslogger, logging::TRACEALL, fmt::format("{}write of {} bytes @addr 0x{:x}", prefix, length, addr));
     }
 #endif
     try {
@@ -613,8 +613,7 @@ uint64_t riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::enter_trap(uint64_t flags, uint6
 #else
                     sprintf(buffer.data(), "0x%016lx", addr);
 #endif
-                    NSCLOG(INFO, LOGCAT) << "Semihosting call at address " << buffer.data() << " occurred ";
-
+                    ILOG(disasslogger, logging::INFO, fmt::format("Semihosting call at address {} occurred ", buffer.data()));
                     this->semihosting_cb(this, &(this->reg.X10) /*a0*/, &(this->reg.X11) /*a1*/);
                     return this->reg.NEXT_PC;
                 }
@@ -689,11 +688,15 @@ uint64_t riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::enter_trap(uint64_t flags, uint6
 #else
     sprintf(buffer.data(), "0x%016lx", addr);
 #endif
-    if((flags & 0xffffffff) != 0xffffffff)
-        NSCLOG(DEBUG, LOGCAT) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
-                              << (trap_id ? this->irq_str[cause] : this->trap_str[cause]) << "' (" << cause << ")" << " at address "
-                              << buffer.data() << " occurred, changing privilege level from " << this->lvl[this->reg.PRIV] << " to "
-                              << this->lvl[new_priv];
+    if((flags & 0xffffffff) != 0xffffffff) {
+        if(trap_id) {
+            ILOG(disasslogger, logging::DEBUG,
+                 fmt::format("Interrupt with cause '{}' ({}) occurred  at address {}", this->irq_str[cause], cause, buffer.data()));
+        } else {
+            ILOG(disasslogger, logging::DEBUG,
+                 fmt::format("Trap with cause '{}' ({}) occurred  at address {}", this->trap_str[cause], cause, buffer.data()));
+        }
+    }
     // reset trap this->state
     this->reg.PRIV = new_priv;
     this->reg.trap_state = 0;
@@ -733,8 +736,8 @@ template <typename BASE, features_e FEAT, typename LOGCAT> uint64_t riscv_hart_m
         }
         // sets the pc to the value stored in the x epc register.
         this->reg.NEXT_PC = this->csr[uepc | inst_priv << 8];
-        NSCLOG(DEBUG, LOGCAT) << "Executing xRET , changing privilege level from " << this->lvl[cur_priv] << " to "
-                              << this->lvl[this->reg.PRIV];
+        ILOG(disasslogger, logging::DEBUG,
+             fmt::format("Executing xRET, changing privilege level from {} to {}", this->lvl[cur_priv], this->lvl[this->reg.PRIV]));
         check_interrupt();
     }
     this->reg.trap_state = this->reg.pending_trap;
diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h
index bf5ae73..2957d78 100644
--- a/src/iss/arch/riscv_hart_mu_p.h
+++ b/src/iss/arch/riscv_hart_mu_p.h
@@ -210,11 +210,11 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::read(const address_type type, c
                                                       const uint64_t addr, const unsigned length, uint8_t* const data) {
 #ifndef NDEBUG
     if(access && iss::access_type::DEBUG) {
-        CPPLOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
+        ILOG(isslogger, logging::TRACEALL, fmt::format("debug read of {} bytes @addr 0x{:x}", length, addr));
     } else if(is_fetch(access)) {
-        CPPLOG(TRACEALL) << "fetch of " << length << " bytes  @addr 0x" << std::hex << addr;
+        ILOG(isslogger, logging::TRACEALL, fmt::format("fetch of {} bytes @addr 0x{:x}", length, addr));
     } else {
-        CPPLOG(TRACE) << "read of " << length << " bytes  @addr 0x" << std::hex << addr;
+        ILOG(isslogger, logging::TRACEALL, fmt::format("read of {} bytes @addr 0x{:x}", length, addr));
     }
 #endif
     try {
@@ -296,23 +296,23 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write(const address_type type,
     const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
     switch(length) {
     case 8:
-        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x"
-                      << std::hex << addr;
+        ILOG(isslogger, logging::TRACEALL,
+             fmt::format("{}write of {} bytes (0x{:x}) @addr 0x{:x}", prefix, length, *reinterpret_cast<const uint64_t*>(&data[0]), addr));
         break;
     case 4:
-        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x"
-                      << std::hex << addr;
+        ILOG(isslogger, logging::TRACEALL,
+             fmt::format("{}write of {} bytes (0x{:x}) @addr 0x{:x}", prefix, length, *reinterpret_cast<const uint32_t*>(&data[0]), addr));
         break;
     case 2:
-        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x"
-                      << std::hex << addr;
+        ILOG(isslogger, logging::TRACEALL,
+             fmt::format("{}write of {} bytes (0x{:x}) @addr 0x{:x}", prefix, length, *reinterpret_cast<const uint16_t*>(&data[0]), addr));
         break;
     case 1:
-        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x"
-                      << std::hex << addr;
+        ILOG(isslogger, logging::TRACEALL,
+             fmt::format("{}write of {} bytes (0x{:x}) @addr 0x{:x}", prefix, length, (uint16_t)data[0], addr));
         break;
     default:
-        CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr 0x" << std::hex << addr;
+        ILOG(isslogger, logging::TRACEALL, fmt::format("{}write of {} bytes @addr 0x{:x}", prefix, length, addr));
     }
 #endif
     try {
@@ -499,8 +499,7 @@ uint64_t riscv_hart_mu_p<BASE, FEAT, LOGCAT>::enter_trap(uint64_t flags, uint64_
 #else
                     sprintf(buffer.data(), "0x%016lx", addr);
 #endif
-                    NSCLOG(INFO, LOGCAT) << "Semihosting call at address " << buffer.data() << " occurred ";
-
+                    ILOG(disasslogger, logging::INFO, fmt::format("Semihosting call at address {} occurred ", buffer.data()));
                     this->semihosting_cb(this, &(this->reg.X10) /*a0*/, &(this->reg.X11) /*a1*/);
                     return this->reg.NEXT_PC;
                 }
@@ -565,11 +564,15 @@ uint64_t riscv_hart_mu_p<BASE, FEAT, LOGCAT>::enter_trap(uint64_t flags, uint64_
 #else
     sprintf(buffer.data(), "0x%016lx", addr);
 #endif
-    if((flags & 0xffffffff) != 0xffffffff)
-        NSCLOG(DEBUG, LOGCAT) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
-                              << (trap_id ? this->irq_str[cause] : this->trap_str[cause]) << "' (" << cause << ")" << " at address "
-                              << buffer.data() << " occurred, changing privilege level from " << this->lvl[this->reg.PRIV] << " to "
-                              << this->lvl[new_priv];
+    if((flags & 0xffffffff) != 0xffffffff) {
+        if(trap_id) {
+            ILOG(disasslogger, logging::DEBUG,
+                 fmt::format("Interrupt with cause '{}' ({}) occurred  at address {}", this->irq_str[cause], cause, buffer.data()));
+        } else {
+            ILOG(disasslogger, logging::DEBUG,
+                 fmt::format("Trap with cause '{}' ({}) occurred  at address {}", this->trap_str[cause], cause, buffer.data()));
+        }
+    }
     // reset trap state
     this->reg.PRIV = new_priv;
     this->reg.trap_state = 0;
@@ -601,8 +604,8 @@ template <typename BASE, features_e FEAT, typename LOGCAT> uint64_t riscv_hart_m
         }
         // sets the pc to the value stored in the x epc register.
         this->reg.NEXT_PC = this->csr[uepc | inst_priv << 8];
-        NSCLOG(DEBUG, LOGCAT) << "Executing xRET , changing privilege level from " << this->lvl[cur_priv] << " to "
-                              << this->lvl[this->reg.PRIV];
+        ILOG(disasslogger, logging::DEBUG,
+             fmt::format("Executing xRET, changing privilege level from {} to {}", this->lvl[cur_priv], this->lvl[this->reg.PRIV]));
         check_interrupt();
     }
     this->reg.trap_state = this->reg.pending_trap;
diff --git a/src/sysc/core2sc_adapter.h b/src/sysc/core2sc_adapter.h
index 00fc052..b2193f9 100644
--- a/src/sysc/core2sc_adapter.h
+++ b/src/sysc/core2sc_adapter.h
@@ -131,14 +131,10 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
         }
     }
 
-    void disass_output(uint64_t pc, const std::string instr) {
+    void disass_output(uint64_t pc, std::string const& instr) {
         static constexpr std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
         if(!owner->disass_output(pc, instr)) {
-            std::stringstream s;
-            s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0') << std::setw(sizeof(reg_t) * 2)
-              << (reg_t)this->state.mstatus << std::dec << ";c:" << this->reg.icount + this->cycle_offset << "]";
-            SCCINFO(owner->hier_name()) << "[disass] " << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc
-                                        << "\t\t" << std::setw(40) << std::setfill(' ') << std::left << instr << s.str();
+            PLAT::disass_output(pc, instr);
         }
     };
 
diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index 6c77742..441ff32 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -347,7 +347,7 @@ template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::start_of_simulatio
     }
 }
 
-template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::disass_output(uint64_t pc, const std::string instr_str) {
+template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::disass_output(uint64_t pc, std::string const& instr_str) {
     if(trc.m_db == nullptr)
         return false;
     if(trc.tr_handle.is_active())
diff --git a/src/sysc/core_complex.h b/src/sysc/core_complex.h
index 910f836..0643f09 100644
--- a/src/sysc/core_complex.h
+++ b/src/sysc/core_complex.h
@@ -198,7 +198,7 @@ template <unsigned int BUSWIDTH = scc::LT> class core_complex : public sc_core::
 
     void trace(sc_core::sc_trace_file* trf) const override;
 
-    bool disass_output(uint64_t pc, const std::string instr) override;
+    bool disass_output(uint64_t pc, std::string const& instr) override;
 
     void set_clock_period(sc_core::sc_time period);
 
diff --git a/src/sysc/core_complex_if.h b/src/sysc/core_complex_if.h
index d96ccaa..36b2fa9 100644
--- a/src/sysc/core_complex_if.h
+++ b/src/sysc/core_complex_if.h
@@ -49,7 +49,7 @@ struct core_complex_if {
 
     virtual bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) = 0;
 
-    virtual bool disass_output(uint64_t pc, const std::string instr) = 0;
+    virtual bool disass_output(uint64_t pc, std::string const& instr) = 0;
 
     virtual unsigned get_last_bus_cycles() = 0;
 

From 5c7bd9e7735889f1585ae34aab81b95f19fdbd0c Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Thu, 6 Nov 2025 17:35:33 +0100
Subject: [PATCH 11/77] adapts to changes in SCC

---
 src/main.cpp | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/src/main.cpp b/src/main.cpp
index 6fc75a6..b55de4e 100644
--- a/src/main.cpp
+++ b/src/main.cpp
@@ -104,10 +104,10 @@ int main(int argc, char* argv[]) {
     LOGGER(dbt_rise_iss)::print_time() = false;
     LOGGER(disass)::print_time() = false;
     auto l = logging::as_log_level(clim["verbose"].as<int>());
-    LOGGER(DEFAULT)::reporting_level() = l;
-    LOGGER(connection)::reporting_level() = l;
-    LOGGER(dbt_rise_iss)::reporting_level() = l;
-    LOGGER(disass)::reporting_level() = l;
+    LOGGER(DEFAULT)::set_reporting_level(l);
+    LOGGER(connection)::set_reporting_level(l);
+    LOGGER(dbt_rise_iss)::set_reporting_level(l);
+    LOGGER(disass)::set_reporting_level(l);
     if(clim.count("logfile")) {
         // configure the connection logger
         auto f = fopen(clim["logfile"].as<std::string>().c_str(), "w");
@@ -210,7 +210,8 @@ int main(int argc, char* argv[]) {
         }
         if(clim.count("disass")) {
             vm->setDisassEnabled(true);
-            LOGGER(disass)::reporting_level() = logging::INFO;
+            LOGGER(disass)::set_reporting_level(logging::DEBUG);
+            auto lvl = LOGGER(disass)::get_reporting_level();
             LOGGER(disass)::print_time() = false;
             auto file_name = clim["disass"].as<std::string>();
             if(file_name.length() > 0) {
@@ -276,7 +277,7 @@ int main(int argc, char* argv[]) {
                 LOG(ERR) << "Error opening file " << filename << std::endl;
                 return 1;
             }
-            LOGGER(DEFAULT)::reporting_level() = logging::ERR;
+            LOGGER(DEFAULT)::set_reporting_level(logging::ERR);
             for(auto addr = start_addr; addr < end_addr; addr += data.size()) {
                 vm->get_arch()->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0 /*MEM*/, addr, data.size(),
                                      data.data()); // FIXME: get space from iss::arch::traits<ARCH>::mem_type_e::MEM

From e64499d0cae134f3ccfee130553b010d133fc522 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Fri, 7 Nov 2025 11:25:01 +0100
Subject: [PATCH 12/77] implements #24

---
 gen_input/templates/interp/CORENAME.cpp.gtl | 7 +++++++
 src/sysc/core2sc_adapter.h                  | 6 ++++++
 src/sysc/sc2core_if.h                       | 2 ++
 src/vm/interp/vm_rv32gc.cpp                 | 9 ++++++++-
 src/vm/interp/vm_rv32gcv.cpp                | 9 ++++++++-
 src/vm/interp/vm_rv32i.cpp                  | 9 ++++++++-
 src/vm/interp/vm_rv32imac.cpp               | 9 ++++++++-
 src/vm/interp/vm_rv64gc.cpp                 | 9 ++++++++-
 src/vm/interp/vm_rv64gcv.cpp                | 9 ++++++++-
 src/vm/interp/vm_rv64i.cpp                  | 9 ++++++++-
 src/vm/interp/vm_tgc5c.cpp                  | 9 ++++++++-
 11 files changed, 79 insertions(+), 8 deletions(-)

diff --git a/gen_input/templates/interp/CORENAME.cpp.gtl b/gen_input/templates/interp/CORENAME.cpp.gtl
index 0d088c3..879141c 100644
--- a/gen_input/templates/interp/CORENAME.cpp.gtl
+++ b/gen_input/templates/interp/CORENAME.cpp.gtl
@@ -399,6 +399,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     break;
                 }// @suppress("No break at end of case")<%}%>
                 default: {
+                    if(this->core.can_handle_unknown_instruction()) {
+                        auto res = this->core.handle_unknown_instruction(pc.val, sizeof(instr), reinterpret_cast<uint8_t*>(&instr));
+                        if(std::get<0>(res)) {
+                            *NEXT_PC = std::get<1>(res);
+                            break;
+                        }
+                    }
                     if(this->disass_enabled){
                         std::string mnemonic = "Illegal Instruction";
                         this->core.disass_output(pc.val, mnemonic);
diff --git a/src/sysc/core2sc_adapter.h b/src/sysc/core2sc_adapter.h
index b2193f9..d48ddf3 100644
--- a/src/sysc/core2sc_adapter.h
+++ b/src/sysc/core2sc_adapter.h
@@ -80,6 +80,10 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
 
     virtual ~core2sc_adapter() {}
 
+    void register_unknown_instr_handler(util::delegate<iss::arch_if::unknown_instr_cb_t> handler) override {
+        PLAT::unknown_instr_cb = handler;
+    };
+
     void notify_phase(iss::arch_if::exec_phase p) {
         if(p == iss::arch_if::ISTART && !first) {
             auto cycle_incr = owner->get_last_bus_cycles();
@@ -262,6 +266,7 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
     }
 
     void _register_csr_rd(unsigned addr, rd_csr_f cb) {
+        // we need to remap the callback as the cores expects reg_t size datat
         std::function<iss::status(unsigned addr, reg_t&)> lambda = [cb](unsigned addr, reg_t& r) -> iss::status {
             uint64_t temp = r;
             auto ret = cb(addr, temp);
@@ -271,6 +276,7 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
         this->register_csr(addr, lambda);
     }
     void _register_csr_wr(unsigned addr, wr_csr_f cb) {
+        // we need to remap the callback as the cores expects reg_t size datat
         std::function<iss::status(unsigned addr, reg_t)> lambda = [cb](unsigned addr, reg_t r) -> iss::status { return cb(addr, r); };
         this->register_csr(addr, lambda);
     }
diff --git a/src/sysc/sc2core_if.h b/src/sysc/sc2core_if.h
index 7626334..1216174 100644
--- a/src/sysc/sc2core_if.h
+++ b/src/sysc/sc2core_if.h
@@ -35,6 +35,7 @@
 #ifndef _SYSC_SC2CORE_IF_H_
 #define _SYSC_SC2CORE_IF_H_
 
+#include "iss/arch_if.h"
 #include <iss/iss.h>
 #include <iss/vm_types.h>
 #include <scc/report.h>
@@ -60,6 +61,7 @@ struct sc2core_if {
     //! sets a callback for CSR write requests. The callback gets always 64bit data passed no matter what size the actual CSR has
     using wr_csr_f = std::function<iss::status(unsigned addr, uint64_t)>;
     util::delegate<void(unsigned, wr_csr_f)> register_csr_wr;
+    virtual void register_unknown_instr_handler(util::delegate<iss::arch_if::unknown_instr_cb_t>) = 0;
 };
 } // namespace sysc
 #endif /* _SYSC_SC2CORE_IF_H_ */
diff --git a/src/vm/interp/vm_rv32gc.cpp b/src/vm/interp/vm_rv32gc.cpp
index 9e78a1f..68cc80c 100644
--- a/src/vm/interp/vm_rv32gc.cpp
+++ b/src/vm/interp/vm_rv32gc.cpp
@@ -4876,6 +4876,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     break;
                 }// @suppress("No break at end of case")
                 default: {
+                    if(this->core.can_handle_unknown_instruction()) {
+                        auto res = this->core.handle_unknown_instruction(pc.val, sizeof(instr), reinterpret_cast<uint8_t*>(&instr));
+                        if(std::get<0>(res)) {
+                            *NEXT_PC = std::get<1>(res);
+                            break;
+                        }
+                    }
                     if(this->disass_enabled){
                         std::string mnemonic = "Illegal Instruction";
                         this->core.disass_output(pc.val, mnemonic);
@@ -4920,8 +4927,8 @@ std::unique_ptr<vm_if> create<arch::rv32gc>(arch::rv32gc *core, unsigned short p
 } // namespace iss
 
 #include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
 #include <iss/arch/riscv_hart_msu_vp.h>
+#include <iss/arch/riscv_hart_mu_p.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {
diff --git a/src/vm/interp/vm_rv32gcv.cpp b/src/vm/interp/vm_rv32gcv.cpp
index d0499c4..ca6fa66 100644
--- a/src/vm/interp/vm_rv32gcv.cpp
+++ b/src/vm/interp/vm_rv32gcv.cpp
@@ -29760,6 +29760,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     break;
                 }// @suppress("No break at end of case")
                 default: {
+                    if(this->core.can_handle_unknown_instruction()) {
+                        auto res = this->core.handle_unknown_instruction(pc.val, sizeof(instr), reinterpret_cast<uint8_t*>(&instr));
+                        if(std::get<0>(res)) {
+                            *NEXT_PC = std::get<1>(res);
+                            break;
+                        }
+                    }
                     if(this->disass_enabled){
                         std::string mnemonic = "Illegal Instruction";
                         this->core.disass_output(pc.val, mnemonic);
@@ -29804,8 +29811,8 @@ std::unique_ptr<vm_if> create<arch::rv32gcv>(arch::rv32gcv *core, unsigned short
 } // namespace iss
 
 #include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
 #include <iss/arch/riscv_hart_msu_vp.h>
+#include <iss/arch/riscv_hart_mu_p.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {
diff --git a/src/vm/interp/vm_rv32i.cpp b/src/vm/interp/vm_rv32i.cpp
index fe29de5..d57b9ce 100644
--- a/src/vm/interp/vm_rv32i.cpp
+++ b/src/vm/interp/vm_rv32i.cpp
@@ -1743,6 +1743,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     break;
                 }// @suppress("No break at end of case")
                 default: {
+                    if(this->core.can_handle_unknown_instruction()) {
+                        auto res = this->core.handle_unknown_instruction(pc.val, sizeof(instr), reinterpret_cast<uint8_t*>(&instr));
+                        if(std::get<0>(res)) {
+                            *NEXT_PC = std::get<1>(res);
+                            break;
+                        }
+                    }
                     if(this->disass_enabled){
                         std::string mnemonic = "Illegal Instruction";
                         this->core.disass_output(pc.val, mnemonic);
@@ -1787,8 +1794,8 @@ std::unique_ptr<vm_if> create<arch::rv32i>(arch::rv32i *core, unsigned short por
 } // namespace iss
 
 #include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
 #include <iss/arch/riscv_hart_msu_vp.h>
+#include <iss/arch/riscv_hart_mu_p.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {
diff --git a/src/vm/interp/vm_rv32imac.cpp b/src/vm/interp/vm_rv32imac.cpp
index 49d201e..4f6ab93 100644
--- a/src/vm/interp/vm_rv32imac.cpp
+++ b/src/vm/interp/vm_rv32imac.cpp
@@ -3145,6 +3145,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     break;
                 }// @suppress("No break at end of case")
                 default: {
+                    if(this->core.can_handle_unknown_instruction()) {
+                        auto res = this->core.handle_unknown_instruction(pc.val, sizeof(instr), reinterpret_cast<uint8_t*>(&instr));
+                        if(std::get<0>(res)) {
+                            *NEXT_PC = std::get<1>(res);
+                            break;
+                        }
+                    }
                     if(this->disass_enabled){
                         std::string mnemonic = "Illegal Instruction";
                         this->core.disass_output(pc.val, mnemonic);
@@ -3189,8 +3196,8 @@ std::unique_ptr<vm_if> create<arch::rv32imac>(arch::rv32imac *core, unsigned sho
 } // namespace iss
 
 #include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
 #include <iss/arch/riscv_hart_msu_vp.h>
+#include <iss/arch/riscv_hart_mu_p.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {
diff --git a/src/vm/interp/vm_rv64gc.cpp b/src/vm/interp/vm_rv64gc.cpp
index 1619acb..3e31536 100644
--- a/src/vm/interp/vm_rv64gc.cpp
+++ b/src/vm/interp/vm_rv64gc.cpp
@@ -6219,6 +6219,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     break;
                 }// @suppress("No break at end of case")
                 default: {
+                    if(this->core.can_handle_unknown_instruction()) {
+                        auto res = this->core.handle_unknown_instruction(pc.val, sizeof(instr), reinterpret_cast<uint8_t*>(&instr));
+                        if(std::get<0>(res)) {
+                            *NEXT_PC = std::get<1>(res);
+                            break;
+                        }
+                    }
                     if(this->disass_enabled){
                         std::string mnemonic = "Illegal Instruction";
                         this->core.disass_output(pc.val, mnemonic);
@@ -6263,8 +6270,8 @@ std::unique_ptr<vm_if> create<arch::rv64gc>(arch::rv64gc *core, unsigned short p
 } // namespace iss
 
 #include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
 #include <iss/arch/riscv_hart_msu_vp.h>
+#include <iss/arch/riscv_hart_mu_p.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {
diff --git a/src/vm/interp/vm_rv64gcv.cpp b/src/vm/interp/vm_rv64gcv.cpp
index 738a282..a1afbf7 100644
--- a/src/vm/interp/vm_rv64gcv.cpp
+++ b/src/vm/interp/vm_rv64gcv.cpp
@@ -31103,6 +31103,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     break;
                 }// @suppress("No break at end of case")
                 default: {
+                    if(this->core.can_handle_unknown_instruction()) {
+                        auto res = this->core.handle_unknown_instruction(pc.val, sizeof(instr), reinterpret_cast<uint8_t*>(&instr));
+                        if(std::get<0>(res)) {
+                            *NEXT_PC = std::get<1>(res);
+                            break;
+                        }
+                    }
                     if(this->disass_enabled){
                         std::string mnemonic = "Illegal Instruction";
                         this->core.disass_output(pc.val, mnemonic);
@@ -31147,8 +31154,8 @@ std::unique_ptr<vm_if> create<arch::rv64gcv>(arch::rv64gcv *core, unsigned short
 } // namespace iss
 
 #include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
 #include <iss/arch/riscv_hart_msu_vp.h>
+#include <iss/arch/riscv_hart_mu_p.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {
diff --git a/src/vm/interp/vm_rv64i.cpp b/src/vm/interp/vm_rv64i.cpp
index 0e75e45..bbf20d6 100644
--- a/src/vm/interp/vm_rv64i.cpp
+++ b/src/vm/interp/vm_rv64i.cpp
@@ -2109,6 +2109,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     break;
                 }// @suppress("No break at end of case")
                 default: {
+                    if(this->core.can_handle_unknown_instruction()) {
+                        auto res = this->core.handle_unknown_instruction(pc.val, sizeof(instr), reinterpret_cast<uint8_t*>(&instr));
+                        if(std::get<0>(res)) {
+                            *NEXT_PC = std::get<1>(res);
+                            break;
+                        }
+                    }
                     if(this->disass_enabled){
                         std::string mnemonic = "Illegal Instruction";
                         this->core.disass_output(pc.val, mnemonic);
@@ -2153,8 +2160,8 @@ std::unique_ptr<vm_if> create<arch::rv64i>(arch::rv64i *core, unsigned short por
 } // namespace iss
 
 #include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
 #include <iss/arch/riscv_hart_msu_vp.h>
+#include <iss/arch/riscv_hart_mu_p.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {
diff --git a/src/vm/interp/vm_tgc5c.cpp b/src/vm/interp/vm_tgc5c.cpp
index 779d616..b47787a 100644
--- a/src/vm/interp/vm_tgc5c.cpp
+++ b/src/vm/interp/vm_tgc5c.cpp
@@ -2730,6 +2730,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     break;
                 }// @suppress("No break at end of case")
                 default: {
+                    if(this->core.can_handle_unknown_instruction()) {
+                        auto res = this->core.handle_unknown_instruction(pc.val, sizeof(instr), reinterpret_cast<uint8_t*>(&instr));
+                        if(std::get<0>(res)) {
+                            *NEXT_PC = std::get<1>(res);
+                            break;
+                        }
+                    }
                     if(this->disass_enabled){
                         std::string mnemonic = "Illegal Instruction";
                         this->core.disass_output(pc.val, mnemonic);
@@ -2774,8 +2781,8 @@ std::unique_ptr<vm_if> create<arch::tgc5c>(arch::tgc5c *core, unsigned short por
 } // namespace iss
 
 #include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
 #include <iss/arch/riscv_hart_msu_vp.h>
+#include <iss/arch/riscv_hart_mu_p.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {

From c0737a2f0096f48380238ff321a8aef1dc6432d8 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Fri, 7 Nov 2025 11:50:39 +0100
Subject: [PATCH 13/77] fixes #25

---
 src/iss/arch/riscv_hart_common.h |  8 ++--
 src/iss/arch/riscv_hart_m_p.h    | 45 ++++++++++------------
 src/iss/arch/riscv_hart_msu_vp.h | 64 +++++++++++++-------------------
 src/iss/arch/riscv_hart_mu_p.h   | 47 ++++++++++-------------
 4 files changed, 69 insertions(+), 95 deletions(-)

diff --git a/src/iss/arch/riscv_hart_common.h b/src/iss/arch/riscv_hart_common.h
index 9efa5ee..d5eb06b 100644
--- a/src/iss/arch/riscv_hart_common.h
+++ b/src/iss/arch/riscv_hart_common.h
@@ -307,7 +307,7 @@ template <typename WORD_TYPE> struct priv_if {
     unsigned& max_irq;
 };
 
-template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_common : public BASE, public mem::memory_elem {
+template <typename BASE = logging::disass> struct riscv_hart_common : public BASE, public mem::memory_elem {
     const std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
     const std::array<const char*, 16> trap_str = {{""
                                                    "Instruction address misaligned", // 0
@@ -333,7 +333,7 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
     constexpr static unsigned MEM = traits<BASE>::MEM;
 
     using core = BASE;
-    using this_class = riscv_hart_common<BASE, LOGCAT>;
+    using this_class = riscv_hart_common<BASE>;
     using reg_t = typename core::reg_t;
 
     using rd_csr_f = std::function<iss::status(unsigned addr, reg_t&)>;
@@ -945,7 +945,7 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
     mem::memory_if memory;
     struct riscv_instrumentation_if : public iss::instrumentation_if {
 
-        riscv_instrumentation_if(riscv_hart_common<BASE, LOGCAT>& arch)
+        riscv_instrumentation_if(riscv_hart_common<BASE>& arch)
         : arch(arch) {}
         /**
          * get the name of this architecture
@@ -976,7 +976,7 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
 
         std::unordered_map<std::string, uint64_t> const& get_symbol_table(std::string name) override { return arch.symbol_table; }
 
-        riscv_hart_common<BASE, LOGCAT>& arch;
+        riscv_hart_common<BASE>& arch;
     };
 
     friend struct riscv_instrumentation_if;
diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h
index c3ae9e6..3bf66b0 100644
--- a/src/iss/arch/riscv_hart_m_p.h
+++ b/src/iss/arch/riscv_hart_m_p.h
@@ -55,12 +55,11 @@
 namespace iss {
 namespace arch {
 
-template <typename BASE, features_e FEAT = FEAT_NONE, typename LOGCAT = logging::disass>
-class riscv_hart_m_p : public riscv_hart_common<BASE> {
+template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_m_p : public riscv_hart_common<BASE> {
 public:
     using core = BASE;
     using base = riscv_hart_common<BASE>;
-    using this_class = riscv_hart_m_p<BASE, FEAT, LOGCAT>;
+    using this_class = riscv_hart_m_p<BASE, FEAT>;
     using reg_t = typename core::reg_t;
     using phys_addr_t = typename core::phys_addr_t;
 
@@ -142,8 +141,8 @@ class riscv_hart_m_p : public riscv_hart_common<BASE> {
     mem::memory_with_htif<reg_t> default_mem;
 };
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-riscv_hart_m_p<BASE, FEAT, LOGCAT>::riscv_hart_m_p()
+template <typename BASE, features_e FEAT>
+riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p()
 : default_mem(base::get_priv_if()) {
     this->csr_rd_cb[mstatus] = MK_CSR_RD_CB(read_status);
     this->csr_wr_cb[mstatus] = MK_CSR_WR_CB(write_status);
@@ -161,9 +160,9 @@ riscv_hart_m_p<BASE, FEAT, LOGCAT>::riscv_hart_m_p()
     this->memories.append(default_mem);
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read(const address_type type, const access_type access, const uint32_t space,
-                                                     const uint64_t addr, const unsigned length, uint8_t* const data) {
+template <typename BASE, features_e FEAT>
+iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr,
+                                             const unsigned length, uint8_t* const data) {
 #ifndef NDEBUG
     if(access && iss::access_type::DEBUG) {
         ILOG(isslogger, logging::TRACEALL, fmt::format("debug read of {} bytes @addr 0x{:x}", length, addr));
@@ -245,9 +244,9 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read(const address_type type, co
     }
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, const access_type access, const uint32_t space,
-                                                      const uint64_t addr, const unsigned length, const uint8_t* const data) {
+template <typename BASE, features_e FEAT>
+iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr,
+                                              const unsigned length, const uint8_t* const data) {
 #ifndef NDEBUG
     const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
     switch(length) {
@@ -336,47 +335,42 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
     }
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read_status(unsigned addr, reg_t& val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_status(unsigned addr, reg_t& val) {
     val = this->state.mstatus & get_mstatus_mask();
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write_status(unsigned addr, reg_t val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_status(unsigned addr, reg_t val) {
     write_mstatus(val);
     check_interrupt();
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read_ie(unsigned addr, reg_t& val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_ie(unsigned addr, reg_t& val) {
     auto mask = riscv_hart_common<BASE>::get_irq_mask(3);
     val = this->csr[mie] & mask;
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write_ie(unsigned addr, reg_t val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_ie(unsigned addr, reg_t val) {
     auto mask = riscv_hart_common<BASE>::get_irq_mask(3);
     this->csr[mie] = (this->csr[mie] & ~mask) | (val & mask);
     check_interrupt();
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read_ip(unsigned addr, reg_t& val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_ip(unsigned addr, reg_t& val) {
     auto mask = riscv_hart_common<BASE>::get_irq_mask(3);
     val = this->csr[mip] & mask;
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT> inline void riscv_hart_m_p<BASE, FEAT, LOGCAT>::reset(uint64_t address) {
+template <typename BASE, features_e FEAT> inline void riscv_hart_m_p<BASE, FEAT>::reset(uint64_t address) {
     BASE::reset(address);
     this->state.mstatus = hart_state<reg_t>::mstatus_reset_val;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT> void riscv_hart_m_p<BASE, FEAT, LOGCAT>::check_interrupt() {
+template <typename BASE, features_e FEAT> void riscv_hart_m_p<BASE, FEAT>::check_interrupt() {
     // Multiple simultaneous interrupts and traps at the same privilege level are
     // handled in the following decreasing priority order:
     // external interrupts, software interrupts, timer interrupts, then finally
@@ -397,8 +391,7 @@ template <typename BASE, features_e FEAT, typename LOGCAT> void riscv_hart_m_p<B
     }
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-uint64_t riscv_hart_m_p<BASE, FEAT, LOGCAT>::enter_trap(uint64_t flags, uint64_t addr, uint64_t tval) {
+template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr, uint64_t tval) {
     // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
     // calculate and write mcause val
     auto const trap_id = bit_sub<0, 16>(flags);
@@ -522,7 +515,7 @@ uint64_t riscv_hart_m_p<BASE, FEAT, LOGCAT>::enter_trap(uint64_t flags, uint64_t
     return this->reg.NEXT_PC;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT> uint64_t riscv_hart_m_p<BASE, FEAT, LOGCAT>::leave_trap(uint64_t flags) {
+template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::leave_trap(uint64_t flags) {
     this->state.mstatus.MIE = this->state.mstatus.MPIE;
     this->state.mstatus.MPIE = 1;
     // sets the pc to the value stored in the x epc register.
diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h
index 33fbfa6..115a95c 100644
--- a/src/iss/arch/riscv_hart_msu_vp.h
+++ b/src/iss/arch/riscv_hart_msu_vp.h
@@ -59,8 +59,7 @@
 namespace iss {
 namespace arch {
 
-template <typename BASE, features_e FEAT = FEAT_NONE, typename LOGCAT = logging::disass>
-class riscv_hart_msu_vp : public riscv_hart_common<BASE> {
+template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_msu_vp : public riscv_hart_common<BASE> {
 public:
     using core = BASE;
     using base = riscv_hart_common<BASE>;
@@ -174,8 +173,8 @@ class riscv_hart_msu_vp : public riscv_hart_common<BASE> {
     mem::memory_with_htif<reg_t> default_mem;
 };
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::riscv_hart_msu_vp()
+template <typename BASE, features_e FEAT>
+riscv_hart_msu_vp<BASE, FEAT>::riscv_hart_msu_vp()
 : mmu(base::get_priv_if())
 , default_mem(base::get_priv_if()) {
     // common regs
@@ -238,9 +237,9 @@ riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::riscv_hart_msu_vp()
     this->csr[misa] |= (extension_encoding::S | extension_encoding::U);
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::read(const address_type type, const access_type access, const uint32_t space,
-                                                        const uint64_t addr, const unsigned length, uint8_t* const data) {
+template <typename BASE, features_e FEAT>
+iss::status riscv_hart_msu_vp<BASE, FEAT>::read(const address_type type, const access_type access, const uint32_t space,
+                                                const uint64_t addr, const unsigned length, uint8_t* const data) {
 #ifndef NDEBUG
     if(access && iss::access_type::DEBUG) {
         ILOG(isslogger, logging::TRACEALL, fmt::format("debug read of {} bytes @addr 0x{:x}", length, addr));
@@ -325,9 +324,9 @@ iss::status riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::read(const address_type type,
     }
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::write(const address_type type, const access_type access, const uint32_t space,
-                                                         const uint64_t addr, const unsigned length, const uint8_t* const data) {
+template <typename BASE, features_e FEAT>
+iss::status riscv_hart_msu_vp<BASE, FEAT>::write(const address_type type, const access_type access, const uint32_t space,
+                                                 const uint64_t addr, const unsigned length, const uint8_t* const data) {
 #ifndef NDEBUG
     const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
     switch(length) {
@@ -427,34 +426,29 @@ iss::status riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::write(const address_type type
     }
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::read_status(unsigned addr, reg_t& val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_msu_vp<BASE, FEAT>::read_status(unsigned addr, reg_t& val) {
     auto req_priv_lvl = (addr >> 8) & 0x3;
     val = this->state.mstatus & get_mstatus_rd_mask(req_priv_lvl);
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::write_status(unsigned addr, reg_t val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_msu_vp<BASE, FEAT>::write_status(unsigned addr, reg_t val) {
     auto req_priv_lvl = (addr >> 8) & 0x3;
     write_mstatus(val, req_priv_lvl);
     check_interrupt();
     return iss::Ok;
 }
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::read_statush(unsigned addr, reg_t& val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_msu_vp<BASE, FEAT>::read_statush(unsigned addr, reg_t& val) {
     val = this->csr[mstatush] & 0b11'1111'1000;
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::write_statush(unsigned addr, reg_t val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_msu_vp<BASE, FEAT>::write_statush(unsigned addr, reg_t val) {
     this->csr[mstatush] = val & 0b11'1111'1000;
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::read_ie(unsigned addr, reg_t& val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_msu_vp<BASE, FEAT>::read_ie(unsigned addr, reg_t& val) {
     val = this->csr[mie];
     if(addr < mie)
         val &= this->csr[mideleg];
@@ -463,16 +457,14 @@ iss::status riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::read_ie(unsigned addr, reg_t&
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::write_ie(unsigned addr, reg_t val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_msu_vp<BASE, FEAT>::write_ie(unsigned addr, reg_t val) {
     auto mask = riscv_hart_common<BASE>::get_irq_mask((addr >> 8) & 0x3);
     this->csr[mie] = (this->csr[mie] & ~mask) | (val & mask);
     check_interrupt();
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::read_ip(unsigned addr, reg_t& val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_msu_vp<BASE, FEAT>::read_ip(unsigned addr, reg_t& val) {
     val = this->csr[mip];
     if(addr < mip)
         val &= this->csr[mideleg];
@@ -481,24 +473,21 @@ iss::status riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::read_ip(unsigned addr, reg_t&
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::write_ideleg(unsigned addr, reg_t val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_msu_vp<BASE, FEAT>::write_ideleg(unsigned addr, reg_t val) {
     // only U and S mode interrupts can be delegated
     auto mask = 0b0011'0011'0011;
     this->csr[mideleg] = (this->csr[mideleg] & ~mask) | (val & mask);
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::write_edeleg(unsigned addr, uint32_t val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_msu_vp<BASE, FEAT>::write_edeleg(unsigned addr, uint32_t val) {
     // bit 3 (break), bit 10 (reserved), bit 11 (Ecall from M) bit 14 (reserved), bit 16-17 (reserved), bit 20-23 (reserved)
     uint32_t mask = 0b1111'1111'0000'1100'1011'0011'1111'0111;
     this->csr[arch::riscv_csr::medeleg] = (this->csr[arch::riscv_csr::medeleg] & ~mask) | (val & mask);
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::write_edeleg(unsigned addr, uint64_t val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_msu_vp<BASE, FEAT>::write_edeleg(unsigned addr, uint64_t val) {
     // bit 3 (break), bit 10 (reserved), bit 11 (Ecall from M) bit 14 (reserved), bit 16-17 (reserved), bit 20-23 (reserved)
     uint32_t mask_lower = 0b1111'1111'0000'1100'1011'0011'1111'0111;
     // bit 32-47(reserved)
@@ -507,22 +496,21 @@ iss::status riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::write_edeleg(unsigned addr, u
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::write_edelegh(unsigned addr, uint32_t val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_msu_vp<BASE, FEAT>::write_edelegh(unsigned addr, uint32_t val) {
     // bit 32-47(reserved)
     auto mask = 0b1111'1111'1111'1111'0000'0000'0000'0000;
     this->csr[medelegh] = (this->csr[medelegh] & ~mask) | (val & mask);
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT> inline void riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::reset(uint64_t address) {
+template <typename BASE, features_e FEAT> inline void riscv_hart_msu_vp<BASE, FEAT>::reset(uint64_t address) {
     BASE::reset(address);
     this->state.mstatus = hart_state<reg_t>::mstatus_reset_val;
     if(sizeof(reg_t) == 8) // Set UXLEN and SXLEN to 64
         this->state.mstatus |= static_cast<reg_t>(0xa00000000ULL);
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT> void riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::check_interrupt() {
+template <typename BASE, features_e FEAT> void riscv_hart_msu_vp<BASE, FEAT>::check_interrupt() {
     auto status = this->state.mstatus;
     auto ip = this->csr[mip];
     auto ie = this->csr[mie];
@@ -550,8 +538,8 @@ template <typename BASE, features_e FEAT, typename LOGCAT> void riscv_hart_msu_v
     }
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-uint64_t riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) {
+template <typename BASE, features_e FEAT>
+uint64_t riscv_hart_msu_vp<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) {
     // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
     // calculate and write mcause val
     if(flags == std::numeric_limits<uint32_t>::max())
@@ -703,7 +691,7 @@ uint64_t riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::enter_trap(uint64_t flags, uint6
     return this->reg.NEXT_PC;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT> uint64_t riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::leave_trap(uint64_t flags) {
+template <typename BASE, features_e FEAT> uint64_t riscv_hart_msu_vp<BASE, FEAT>::leave_trap(uint64_t flags) {
     auto cur_priv = this->reg.PRIV;
     auto inst_priv = flags & 0x3;
 
@@ -744,7 +732,7 @@ template <typename BASE, features_e FEAT, typename LOGCAT> uint64_t riscv_hart_m
     return this->reg.NEXT_PC;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT> void riscv_hart_msu_vp<BASE, FEAT, LOGCAT>::wait_until(uint64_t flags) {
+template <typename BASE, features_e FEAT> void riscv_hart_msu_vp<BASE, FEAT>::wait_until(uint64_t flags) {
     auto status = this->state.mstatus;
     auto tw = status.TW;
     if(this->reg.PRIV < PRIV_M && tw != 0) {
diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h
index 2957d78..8262c51 100644
--- a/src/iss/arch/riscv_hart_mu_p.h
+++ b/src/iss/arch/riscv_hart_mu_p.h
@@ -56,12 +56,11 @@
 namespace iss {
 namespace arch {
 
-template <typename BASE, features_e FEAT = FEAT_NONE, typename LOGCAT = logging::disass>
-class riscv_hart_mu_p : public riscv_hart_common<BASE> {
+template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_mu_p : public riscv_hart_common<BASE> {
 public:
     using core = BASE;
     using base = riscv_hart_common<BASE>;
-    using this_class = riscv_hart_mu_p<BASE, FEAT, LOGCAT>;
+    using this_class = riscv_hart_mu_p<BASE, FEAT>;
     using reg_t = typename core::reg_t;
     using phys_addr_t = typename core::phys_addr_t;
 
@@ -163,8 +162,8 @@ class riscv_hart_mu_p : public riscv_hart_common<BASE> {
     mem::memory_with_htif<reg_t> default_mem;
 };
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-riscv_hart_mu_p<BASE, FEAT, LOGCAT>::riscv_hart_mu_p()
+template <typename BASE, features_e FEAT>
+riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
 : state()
 , default_mem(base::get_priv_if()) {
     this->csr_rd_cb[mstatus] = MK_CSR_RD_CB(read_status);
@@ -205,9 +204,9 @@ riscv_hart_mu_p<BASE, FEAT, LOGCAT>::riscv_hart_mu_p()
     this->csr[misa] |= extension_encoding::U;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::read(const address_type type, const access_type access, const uint32_t space,
-                                                      const uint64_t addr, const unsigned length, uint8_t* const data) {
+template <typename BASE, features_e FEAT>
+iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr,
+                                              const unsigned length, uint8_t* const data) {
 #ifndef NDEBUG
     if(access && iss::access_type::DEBUG) {
         ILOG(isslogger, logging::TRACEALL, fmt::format("debug read of {} bytes @addr 0x{:x}", length, addr));
@@ -289,9 +288,9 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::read(const address_type type, c
     }
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write(const address_type type, const access_type access, const uint32_t space,
-                                                       const uint64_t addr, const unsigned length, const uint8_t* const data) {
+template <typename BASE, features_e FEAT>
+iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr,
+                                               const unsigned length, const uint8_t* const data) {
 #ifndef NDEBUG
     const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
     switch(length) {
@@ -380,47 +379,42 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write(const address_type type,
     }
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::read_status(unsigned addr, reg_t& val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_status(unsigned addr, reg_t& val) {
     val = state.mstatus & get_mstatus_mask((addr >> 8) & 0x3);
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write_status(unsigned addr, reg_t val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_status(unsigned addr, reg_t val) {
     write_mstatus(val, (addr >> 8) & 0x3);
     check_interrupt();
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::read_ie(unsigned addr, reg_t& val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_ie(unsigned addr, reg_t& val) {
     auto mask = riscv_hart_common<BASE>::get_irq_mask((addr >> 8) & 0x3);
     val = this->csr[mie] & mask;
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write_ie(unsigned addr, reg_t val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_ie(unsigned addr, reg_t val) {
     auto mask = riscv_hart_common<BASE>::get_irq_mask((addr >> 8) & 0x3);
     this->csr[mie] = (this->csr[mie] & ~mask) | (val & mask);
     check_interrupt();
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::read_ip(unsigned addr, reg_t& val) {
+template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_ip(unsigned addr, reg_t& val) {
     auto mask = riscv_hart_common<BASE>::get_irq_mask((addr >> 8) & 0x3);
     val = this->csr[mip] & mask;
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT> inline void riscv_hart_mu_p<BASE, FEAT, LOGCAT>::reset(uint64_t address) {
+template <typename BASE, features_e FEAT> inline void riscv_hart_mu_p<BASE, FEAT>::reset(uint64_t address) {
     BASE::reset(address);
     state.mstatus = hart_state<reg_t>::mstatus_reset_val;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT> void riscv_hart_mu_p<BASE, FEAT, LOGCAT>::check_interrupt() {
+template <typename BASE, features_e FEAT> void riscv_hart_mu_p<BASE, FEAT>::check_interrupt() {
     // TODO: Implement CLIC functionality
     // Multiple simultaneous interrupts and traps at the same privilege level are
     // handled in the following decreasing priority order:
@@ -442,8 +436,7 @@ template <typename BASE, features_e FEAT, typename LOGCAT> void riscv_hart_mu_p<
     }
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT>
-uint64_t riscv_hart_mu_p<BASE, FEAT, LOGCAT>::enter_trap(uint64_t flags, uint64_t addr, uint64_t tval) {
+template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr, uint64_t tval) {
     // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
     // calculate and write mcause val
     if(flags == std::numeric_limits<uint64_t>::max())
@@ -579,7 +572,7 @@ uint64_t riscv_hart_mu_p<BASE, FEAT, LOGCAT>::enter_trap(uint64_t flags, uint64_
     return this->reg.NEXT_PC;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT> uint64_t riscv_hart_mu_p<BASE, FEAT, LOGCAT>::leave_trap(uint64_t flags) {
+template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::leave_trap(uint64_t flags) {
     auto cur_priv = this->reg.PRIV;
     auto inst_priv = (flags & 0x3) ? 3 : 0;
     if(inst_priv > cur_priv) {
@@ -612,7 +605,7 @@ template <typename BASE, features_e FEAT, typename LOGCAT> uint64_t riscv_hart_m
     return this->reg.NEXT_PC;
 }
 
-template <typename BASE, features_e FEAT, typename LOGCAT> void riscv_hart_mu_p<BASE, FEAT, LOGCAT>::wait_until(uint64_t flags) {
+template <typename BASE, features_e FEAT> void riscv_hart_mu_p<BASE, FEAT>::wait_until(uint64_t flags) {
     auto status = state.mstatus;
     auto tw = status.TW;
     if(this->reg.PRIV == PRIV_S && tw != 0) {

From 692a04a56bbea540346b85f392ba7c40ac4547cb Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Fri, 14 Nov 2025 21:21:15 +0100
Subject: [PATCH 14/77] cleans build dependencies

---
 CMakeLists.txt    | 2 +-
 CMakePresets.json | 5 +++--
 conanfile.py      | 1 -
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 377c6fd..d93cef4 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -20,7 +20,7 @@ if(NOT TARGET dbt-rise-core)
         dbt_rise_core_git
         GIT_REPOSITORY "https://github.com/Minres/DBT-RISE-Core.git"
         #GIT_TAG         "origin/develop"
-        GIT_TAG 0c7532f6
+        GIT_TAG ef3134b
         GIT_SHALLOW OFF
         UPDATE_DISCONNECTED NOT ${UPDATE_EXTERNAL_PROJECT} # When enabled, this option causes the update step to be skipped.
     )
diff --git a/CMakePresets.json b/CMakePresets.json
index 6079f1b..412e6ec 100644
--- a/CMakePresets.json
+++ b/CMakePresets.json
@@ -20,7 +20,8 @@
                 "CMAKE_INSTALL_PREFIX": "${sourceDir}/install/${presetName}",
                 "CMAKE_EXPORT_COMPILE_COMMANDS": "ON",
                 "CMAKE_PROJECT_TOP_LEVEL_INCLUDES": "contrib/cmake/conan_provider.cmake",
-                "CONAN_BUILD_PROFILE": "auto-cmake",
+                "CONAN_HOST_PROFILE": "auto-cmake",
+                "CONAN_BUILD_PROFILE": "conan_host_profile",
                 "WITH_TCC": "OFF"
             }
         },
@@ -49,4 +50,4 @@
             }
         }
     ]
-}
\ No newline at end of file
+}
diff --git a/conanfile.py b/conanfile.py
index e87df7a..76ba146 100644
--- a/conanfile.py
+++ b/conanfile.py
@@ -39,7 +39,6 @@ def requirements(self):
         self.requires("fmt/8.0.1")
         self.requires("spdlog/1.9.2")
         self.requires("boost/1.85.0")
-        self.requires("abseil/20250127.0")
         self.requires("elfio/3.11")
         self.requires("lz4/1.9.3")
         self.requires("yaml-cpp/0.7.0")

From c971b3ceac856cff9586b40242233805cbc2e321 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Sat, 15 Nov 2025 12:27:25 +0100
Subject: [PATCH 15/77] updates version number and adds github ci action

---
 .github/workflows/ci-compile.yml | 49 ++++++++++++++++++++++++++++++++
 CMakeLists.txt                   |  2 +-
 2 files changed, 50 insertions(+), 1 deletion(-)
 create mode 100644 .github/workflows/ci-compile.yml

diff --git a/.github/workflows/ci-compile.yml b/.github/workflows/ci-compile.yml
new file mode 100644
index 0000000..c6547f0
--- /dev/null
+++ b/.github/workflows/ci-compile.yml
@@ -0,0 +1,49 @@
+name: CI C++ Std compliance
+
+on:
+  push:
+    paths:
+      - '**.hpp'
+      - '**.cpp'
+      - '**.h'
+      - '**.c'
+      - '**CMakeLists.txt'
+      - '.github/workflows/**'
+      - 'conanfile.py'
+  pull_request:
+    paths:
+      - '**.hpp'
+      - '**.cpp'
+      - '**.h'
+      - '**.c'
+      - '**CMakeLists.txt'
+      - '.github/workflows/**'
+      - 'conanfile.py'
+
+jobs:
+  build-and-test:
+    runs-on: ubuntu-latest
+    strategy:
+      matrix:
+        cpp_std: [11, 14, 17, 20]
+    steps:
+      - uses: actions/checkout@v4
+
+      - name: Update submodules
+        run: git submodule update --init --recursive
+
+      - name: Install dependencies
+        run: |
+          sudo apt-get update
+          sudo apt-get install -y g++ python3-pip cmake
+          pip3 install conan
+          cmake --version
+
+      - name: Configure
+        run: cmake --preset Debug -B build -DCMAKE_CXX_STANDARD=${{ matrix.cpp_std }}
+
+      - name: Build
+        run: cmake --build build -j
+
+      - name: Run smoke test
+        run: ./build/riscv-sim -h
diff --git a/CMakeLists.txt b/CMakeLists.txt
index d93cef4..0ad2d56 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -4,7 +4,7 @@ list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/cmake)
 ###############################################################################
 #
 ###############################################################################
-project(dbt-rise-riscv VERSION 2.0.0 LANGUAGES C CXX)
+project(dbt-rise-riscv VERSION 2.1.0 LANGUAGES C CXX)
 
 option(UPDATE_EXTERNAL_PROJECT "Whether to pull changes in external projects" ON)
 

From 05f7051db2886ddc94cb8b6573f6b6cd6b995cb3 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Sat, 15 Nov 2025 12:30:53 +0100
Subject: [PATCH 16/77] removes out-dated cppstd levels

---
 .github/workflows/ci-compile.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/ci-compile.yml b/.github/workflows/ci-compile.yml
index c6547f0..b5971c4 100644
--- a/.github/workflows/ci-compile.yml
+++ b/.github/workflows/ci-compile.yml
@@ -25,7 +25,7 @@ jobs:
     runs-on: ubuntu-latest
     strategy:
       matrix:
-        cpp_std: [11, 14, 17, 20]
+        cpp_std: [17, 20]
     steps:
       - uses: actions/checkout@v4
 

From b64add3d949c7a042e5adf991c3ae35cc5819851 Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Fri, 14 Nov 2025 09:33:45 +0100
Subject: [PATCH 17/77] updates dbt-rise-core version

---
 CMakeLists.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 0ad2d56..e5fc71e 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -20,7 +20,7 @@ if(NOT TARGET dbt-rise-core)
         dbt_rise_core_git
         GIT_REPOSITORY "https://github.com/Minres/DBT-RISE-Core.git"
         #GIT_TAG         "origin/develop"
-        GIT_TAG ef3134b
+        GIT_TAG 6f2d15ec
         GIT_SHALLOW OFF
         UPDATE_DISCONNECTED NOT ${UPDATE_EXTERNAL_PROJECT} # When enabled, this option causes the update step to be skipped.
     )

From 0dd45aa328f7a129ecceb1cac24104f695851c04 Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Sat, 15 Nov 2025 15:23:34 +0100
Subject: [PATCH 18/77] changes memory_elems to take PLAT as template argument
 this allows the memory_elems to access traits

---
 src/iss/arch/riscv_hart_m_p.h    |  2 +-
 src/iss/arch/riscv_hart_msu_vp.h |  4 ++--
 src/iss/arch/riscv_hart_mu_p.h   |  2 +-
 src/iss/mem/memory_with_htif.h   | 11 ++++++-----
 src/iss/mem/mmu.h                | 12 ++++++------
 src/iss/mem/pmp.h                | 15 +++++++--------
 6 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h
index 3bf66b0..b180579 100644
--- a/src/iss/arch/riscv_hart_m_p.h
+++ b/src/iss/arch/riscv_hart_m_p.h
@@ -138,7 +138,7 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_m_p : pub
     iss::status read_ip(unsigned addr, reg_t& val);
 
     void check_interrupt();
-    mem::memory_with_htif<reg_t> default_mem;
+    mem::memory_with_htif<BASE> default_mem;
 };
 
 template <typename BASE, features_e FEAT>
diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h
index 115a95c..70dd92d 100644
--- a/src/iss/arch/riscv_hart_msu_vp.h
+++ b/src/iss/arch/riscv_hart_msu_vp.h
@@ -169,8 +169,8 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_msu_vp :
     iss::status write_edelegh(unsigned addr, uint32_t val);
 
     void check_interrupt();
-    mem::mmu<reg_t> mmu;
-    mem::memory_with_htif<reg_t> default_mem;
+    mem::mmu<BASE> mmu;
+    mem::memory_with_htif<BASE> default_mem;
 };
 
 template <typename BASE, features_e FEAT>
diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h
index 8262c51..a8ae18f 100644
--- a/src/iss/arch/riscv_hart_mu_p.h
+++ b/src/iss/arch/riscv_hart_mu_p.h
@@ -159,7 +159,7 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_mu_p : pu
     iss::status read_ip(unsigned addr, reg_t& val);
 
     void check_interrupt();
-    mem::memory_with_htif<reg_t> default_mem;
+    mem::memory_with_htif<BASE> default_mem;
 };
 
 template <typename BASE, features_e FEAT>
diff --git a/src/iss/mem/memory_with_htif.h b/src/iss/mem/memory_with_htif.h
index 47b021f..7a381ed 100644
--- a/src/iss/mem/memory_with_htif.h
+++ b/src/iss/mem/memory_with_htif.h
@@ -44,11 +44,12 @@
 
 namespace iss {
 namespace mem {
-template <typename WORD_TYPE> struct memory_with_htif : public memory_elem {
-    using this_class = memory_with_htif<WORD_TYPE>;
-    constexpr static unsigned WORD_LEN = sizeof(WORD_TYPE) * 8;
+template <typename PLAT> struct memory_with_htif : public memory_elem {
+    using this_class = memory_with_htif<PLAT>;
+    using reg_t = typename PLAT::reg_t;
+    constexpr static unsigned WORD_LEN = sizeof(PLAT::reg_t) * 8;
 
-    memory_with_htif(arch::priv_if<WORD_TYPE> hart_if)
+    memory_with_htif(arch::priv_if<reg_t> hart_if)
     : hart_if(hart_if) {}
 
     ~memory_with_htif() = default;
@@ -108,7 +109,7 @@ template <typename WORD_TYPE> struct memory_with_htif : public memory_elem {
 protected:
     using mem_type = util::sparse_array<uint8_t, 1ULL << 32>;
     mem_type mem;
-    arch::priv_if<WORD_TYPE> hart_if;
+    arch::priv_if<reg_t> hart_if;
 };
 } // namespace mem
 } // namespace iss
diff --git a/src/iss/mem/mmu.h b/src/iss/mem/mmu.h
index 93e18e0..d945e6f 100644
--- a/src/iss/mem/mmu.h
+++ b/src/iss/mem/mmu.h
@@ -68,14 +68,14 @@ struct vm_info {
     uint64_t ptbase;
 };
 
-template <typename WORD_TYPE> struct mmu : public memory_elem {
-    using this_class = mmu<WORD_TYPE>;
-    using reg_t = WORD_TYPE;
+template <typename PLAT> struct mmu : public memory_elem {
+    using this_class = mmu<PLAT>;
+    using reg_t = typename PLAT::reg_t;
 
     constexpr static reg_t PGSIZE = 1 << PGSHIFT;
     constexpr static reg_t PGMASK = PGSIZE - 1;
 
-    mmu(arch::priv_if<WORD_TYPE> hart_if)
+    mmu(arch::priv_if<reg_t> hart_if)
     : hart_if(hart_if) {
         hart_if.csr_rd_cb[arch::riscv_csr::satp] = MK_CSR_RD_CB(read_satp);
         hart_if.csr_wr_cb[arch::riscv_csr::satp] = MK_CSR_WR_CB(write_satp);
@@ -215,11 +215,11 @@ template <typename WORD_TYPE> struct mmu : public memory_elem {
     reg_t satp;
     std::unordered_map<reg_t, uint64_t> tlb;
     vm_info vm_setting{0, 0, 0, 0};
-    arch::priv_if<WORD_TYPE> hart_if;
+    arch::priv_if<reg_t> hart_if;
     memory_if down_stream_mem;
 };
 
-template <typename WORD_TYPE> uint64_t mmu<WORD_TYPE>::virt2phys(iss::access_type access, uint64_t addr) {
+template <typename PLAT> uint64_t mmu<PLAT>::virt2phys(iss::access_type access, uint64_t addr) {
     const auto type = access & iss::access_type::FUNC;
     reg_t pte{0};
     if(auto it = tlb.find(addr >> PGSHIFT); it != tlb.end()) {
diff --git a/src/iss/mem/pmp.h b/src/iss/mem/pmp.h
index 6056c44..062828e 100644
--- a/src/iss/mem/pmp.h
+++ b/src/iss/mem/pmp.h
@@ -32,9 +32,9 @@
  *       eyck@minres.com - initial implementation
  ******************************************************************************/
 
-#include "memory_if.h"
 #include "iss/arch/riscv_hart_common.h"
 #include "iss/vm_types.h"
+#include "memory_if.h"
 #include <util/logging.h>
 
 namespace iss {
@@ -89,12 +89,11 @@ inline void write_reg_with_offset(uint32_t& reg, uint8_t offs, const uint8_t* co
     }
 }
 
-template <typename WORD_TYPE> struct pmp : public memory_elem {
-    using this_class = pmp<WORD_TYPE>;
-    using reg_t = WORD_TYPE;
-    constexpr static unsigned WORD_LEN = sizeof(WORD_TYPE) * 8;
+template <typename PLAT> struct pmp : public memory_elem {
+    using this_class = pmp<PLAT>;
+    using reg_t = typename PLAT::reg_t;
 
-    pmp(arch::priv_if<WORD_TYPE> hart_if)
+    pmp(arch::priv_if<reg_t> hart_if)
     : hart_if(hart_if) {
         for(size_t i = arch::pmpaddr0; i <= arch::pmpaddr15; ++i) {
             hart_if.csr_rd_cb[i] = MK_CSR_RD_CB(read_plain);
@@ -156,11 +155,11 @@ template <typename WORD_TYPE> struct pmp : public memory_elem {
     bool pmp_check(const access_type type, const uint64_t addr, const unsigned len);
 
 protected:
-    arch::priv_if<WORD_TYPE> hart_if;
+    arch::priv_if<reg_t> hart_if;
     memory_if down_stream_mem;
 };
 
-template <typename WORD_TYPE> bool pmp<WORD_TYPE>::pmp_check(const access_type type, const uint64_t addr, const unsigned len) {
+template <typename PLAT> bool pmp<PLAT>::pmp_check(const access_type type, const uint64_t addr, const unsigned len) {
     constexpr auto PMP_SHIFT = 2U;
     constexpr auto PMP_R = 0x1U;
     constexpr auto PMP_W = 0x2U;

From 3d0b54c430e86636d18a67de120bc36e2de3d7b9 Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Sat, 15 Nov 2025 15:23:57 +0100
Subject: [PATCH 19/77] corrects typo

---
 src/iss/mem/memory_with_htif.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/iss/mem/memory_with_htif.h b/src/iss/mem/memory_with_htif.h
index 7a381ed..95a0673 100644
--- a/src/iss/mem/memory_with_htif.h
+++ b/src/iss/mem/memory_with_htif.h
@@ -60,7 +60,7 @@ template <typename PLAT> struct memory_with_htif : public memory_elem {
     }
 
     void set_next(memory_if) override {
-        // intenrionally left empty, leaf element
+        // intentionally left empty, leaf element
     }
 
 private:

From 71e5ce596428d5ea9e165743c87ed183fae49a93 Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Sat, 15 Nov 2025 15:26:15 +0100
Subject: [PATCH 20/77] updates gitignore to include more artifacts

---
 .gitignore | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.gitignore b/.gitignore
index b189e80..8120c73 100644
--- a/.gitignore
+++ b/.gitignore
@@ -38,3 +38,4 @@
 build
 contrib/instr/*_fast.yaml
 contrib/instr/*_slow.yaml
+.cache

From 49ebce23e56413c09f0c2d7c7b17bceb7e42f073 Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Sat, 15 Nov 2025 15:27:59 +0100
Subject: [PATCH 21/77] removes unused expr

---
 src/iss/mem/memory_with_htif.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/iss/mem/memory_with_htif.h b/src/iss/mem/memory_with_htif.h
index 95a0673..1d2b769 100644
--- a/src/iss/mem/memory_with_htif.h
+++ b/src/iss/mem/memory_with_htif.h
@@ -47,7 +47,6 @@ namespace mem {
 template <typename PLAT> struct memory_with_htif : public memory_elem {
     using this_class = memory_with_htif<PLAT>;
     using reg_t = typename PLAT::reg_t;
-    constexpr static unsigned WORD_LEN = sizeof(PLAT::reg_t) * 8;
 
     memory_with_htif(arch::priv_if<reg_t> hart_if)
     : hart_if(hart_if) {}

From 526e06aeb0f9b7b6a062913f9a9e8e2a63cf108a Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Sat, 15 Nov 2025 15:51:19 +0100
Subject: [PATCH 22/77] changes memory_if for rd and wr to take space as an
 argument

---
 src/iss/arch/riscv_hart_common.h |  2 +-
 src/iss/arch/riscv_hart_m_p.h    | 12 ++++++------
 src/iss/arch/riscv_hart_msu_vp.h |  8 ++++----
 src/iss/arch/riscv_hart_mu_p.h   |  8 ++++----
 src/iss/mem/memory_if.h          |  8 ++++----
 src/iss/mem/memory_with_htif.h   |  4 ++--
 src/iss/mem/mmu.h                | 20 ++++++++++----------
 src/iss/mem/pmp.h                |  8 ++++----
 8 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/src/iss/arch/riscv_hart_common.h b/src/iss/arch/riscv_hart_common.h
index d5eb06b..621f081 100644
--- a/src/iss/arch/riscv_hart_common.h
+++ b/src/iss/arch/riscv_hart_common.h
@@ -904,7 +904,7 @@ template <typename BASE = logging::disass> struct riscv_hart_common : public BAS
             return iss::Ok;
         } else if(device == 0 && command == 0) {
             std::array<uint64_t, 8> loaded_payload;
-            if(memory.rd_mem(access_type::DEBUG_READ, payload_data, 8 * sizeof(uint64_t),
+            if(memory.rd_mem(access_type::DEBUG_READ, traits<BASE>::MEM, payload_data, 8 * sizeof(uint64_t),
                              reinterpret_cast<uint8_t*>(loaded_payload.data())) == iss::Err)
                 ILOG(isslogger, logging::ERR, "Syscall read went wrong");
             uint64_t syscall_num = loaded_payload.at(0);
diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h
index b180579..4aa852f 100644
--- a/src/iss/arch/riscv_hart_m_p.h
+++ b/src/iss/arch/riscv_hart_m_p.h
@@ -189,7 +189,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
                     this->fault_data = addr;
                     return iss::Err;
                 }
-                auto res = this->memory.rd_mem(access, addr, length, data);
+                auto res = this->memory.rd_mem(access, space, addr, length, data);
                 if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
                     this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_LOAD_ACCESS << 16;
                     this->fault_data = addr;
@@ -287,7 +287,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
                     this->fault_data = addr;
                     return iss::Err;
                 }
-                auto res = this->memory.wr_mem(access, addr, length, data);
+                auto res = this->memory.wr_mem(access, space, addr, length, data);
                 if(unlikely(res != iss::Ok && !is_debug(access))) {
                     this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_STORE_ACCESS << 16;
                     this->fault_data = addr;
@@ -431,9 +431,9 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
                 // Check for semihosting call
                 std::array<uint8_t, 8> data;
                 // check for SLLI_X0_X0_0X1F and SRAI_X0_X0_0X07
-                this->memory.rd_mem(iss::access_type::DEBUG_READ, addr - 4, 4, data.data());
+                this->memory.rd_mem(iss::access_type::DEBUG_READ, traits<BASE>::IMEM, addr - 4, 4, data.data());
                 addr += 8;
-                this->memory.rd_mem(iss::access_type::DEBUG_READ, addr - 4, 4, data.data() + 4);
+                this->memory.rd_mem(iss::access_type::DEBUG_READ, traits<BASE>::IMEM, addr - 4, 4, data.data() + 4);
 
                 const std::array<uint8_t, 8> ref_data = {0x13, 0x10, 0xf0, 0x01, 0x13, 0x50, 0x70, 0x40};
                 if(data == ref_data) {
@@ -483,8 +483,8 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
     // calculate adds// set NEXT_PC to trap addressess to jump to based on MODE
     if(trap_id != 0 && (xtvec & 0x3UL) == 3UL) {
         reg_t data;
-        auto ret =
-            this->memory.rd_mem(iss::access_type::DEBUG_READ, this->csr[arch::mtvt], sizeof(reg_t), reinterpret_cast<uint8_t*>(&data));
+        auto ret = this->memory.rd_mem(access_type::DEBUG_READ, traits<BASE>::MEM, this->csr[arch::mtvt], sizeof(reg_t),
+                                       reinterpret_cast<uint8_t*>(&data));
         if(ret == iss::Err)
             return this->reg.PC;
         this->reg.NEXT_PC = data;
diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h
index 70dd92d..25cfe8e 100644
--- a/src/iss/arch/riscv_hart_msu_vp.h
+++ b/src/iss/arch/riscv_hart_msu_vp.h
@@ -266,7 +266,7 @@ iss::status riscv_hart_msu_vp<BASE, FEAT>::read(const address_type type, const a
                     this->fault_data = addr;
                     return iss::Err;
                 }
-                auto res = this->memory.rd_mem(access, addr, length, data);
+                auto res = this->memory.rd_mem(access, space, addr, length, data);
                 if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
                     this->reg.trap_state = (1UL << 31) | (traits<BASE>::RV_CAUSE_LOAD_ACCESS << 16);
                     this->fault_data = addr;
@@ -367,7 +367,7 @@ iss::status riscv_hart_msu_vp<BASE, FEAT>::write(const address_type type, const
                     this->fault_data = addr;
                     return iss::Err;
                 }
-                auto res = this->memory.wr_mem(access, addr, length, data);
+                auto res = this->memory.wr_mem(access, space, addr, length, data);
                 if(unlikely(res != iss::Ok && !is_debug(access))) {
                     this->reg.trap_state = (1UL << 31) | (traits<BASE>::RV_CAUSE_STORE_ACCESS << 16);
                     this->fault_data = addr;
@@ -587,9 +587,9 @@ uint64_t riscv_hart_msu_vp<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr
                 // Check for semihosting call
                 std::array<uint8_t, 8> data;
                 // check for SLLI_X0_X0_0X1F and SRAI_X0_X0_0X07
-                this->memory.rd_mem(iss::access_type::DEBUG_READ, addr - 4, 4, data.data());
+                this->memory.rd_mem(iss::access_type::DEBUG_READ, traits<BASE>::IMEM, addr - 4, 4, data.data());
                 addr += 8;
-                this->memory.rd_mem(iss::access_type::DEBUG_READ, addr - 4, 4, data.data() + 4);
+                this->memory.rd_mem(iss::access_type::DEBUG_READ, traits<BASE>::IMEM, addr - 4, 4, data.data() + 4);
 
                 const std::array<uint8_t, 8> ref_data = {0x13, 0x10, 0xf0, 0x01, 0x13, 0x50, 0x70, 0x40};
                 if(data == ref_data) {
diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h
index a8ae18f..182ca4b 100644
--- a/src/iss/arch/riscv_hart_mu_p.h
+++ b/src/iss/arch/riscv_hart_mu_p.h
@@ -233,7 +233,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
                     this->fault_data = addr;
                     return iss::Err;
                 }
-                auto res = this->memory.rd_mem(access, addr, length, data);
+                auto res = this->memory.rd_mem(access, space, addr, length, data);
                 if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
                     this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_LOAD_ACCESS << 16;
                     this->fault_data = addr;
@@ -331,7 +331,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
                     this->fault_data = addr;
                     return iss::Err;
                 }
-                auto res = this->memory.wr_mem(access, addr, length, data);
+                auto res = this->memory.wr_mem(access, space, addr, length, data);
                 if(unlikely(res != iss::Ok && !is_debug(access))) {
                     this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_STORE_ACCESS << 16;
                     this->fault_data = addr;
@@ -478,9 +478,9 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
                 // Check for semihosting call
                 std::array<uint8_t, 8> data;
                 // check for SLLI_X0_X0_0X1F and SRAI_X0_X0_0X07
-                this->memory.rd_mem(iss::access_type::DEBUG_READ, addr - 4, 4, data.data());
+                this->memory.rd_mem(iss::access_type::DEBUG_READ, traits<BASE>::IMEM, addr - 4, 4, data.data());
                 addr += 8;
-                this->memory.rd_mem(iss::access_type::DEBUG_READ, addr - 4, 4, data.data() + 4);
+                this->memory.rd_mem(iss::access_type::DEBUG_READ, traits<BASE>::IMEM, addr - 4, 4, data.data() + 4);
 
                 const std::array<uint8_t, 8> ref_data = {0x13, 0x10, 0xf0, 0x01, 0x13, 0x50, 0x70, 0x40};
                 if(data == ref_data) {
diff --git a/src/iss/mem/memory_if.h b/src/iss/mem/memory_if.h
index 8d6e8b7..e459a87 100644
--- a/src/iss/mem/memory_if.h
+++ b/src/iss/mem/memory_if.h
@@ -46,12 +46,12 @@
 namespace iss {
 namespace mem {
 
-using rd_mem_func_sig = iss::status(iss::access_type, uint64_t, unsigned, uint8_t*);
-using wr_mem_func_sig = iss::status(iss::access_type, uint64_t, unsigned, uint8_t const*);
+using rd_mem_func_sig = iss::status(iss::access_type, uint32_t space, uint64_t addr, unsigned length, uint8_t* data);
+using wr_mem_func_sig = iss::status(iss::access_type, uint32_t space, uint64_t addr, unsigned length, uint8_t const* data);
 
 struct memory_if {
-    util::delegate<iss::status(access_type, uint64_t, unsigned, uint8_t*)> rd_mem;
-    util::delegate<iss::status(access_type, uint64_t, unsigned, uint8_t const*)> wr_mem;
+    util::delegate<rd_mem_func_sig> rd_mem;
+    util::delegate<wr_mem_func_sig> wr_mem;
 };
 
 struct memory_elem {
diff --git a/src/iss/mem/memory_with_htif.h b/src/iss/mem/memory_with_htif.h
index 1d2b769..43b94fb 100644
--- a/src/iss/mem/memory_with_htif.h
+++ b/src/iss/mem/memory_with_htif.h
@@ -63,7 +63,7 @@ template <typename PLAT> struct memory_with_htif : public memory_elem {
     }
 
 private:
-    iss::status read_mem(iss::access_type access, uint64_t addr, unsigned length, uint8_t* data) {
+    iss::status read_mem(iss::access_type access, uint32_t space, uint64_t addr, unsigned length, uint8_t* data) {
         // for(auto offs = 0U; offs < length; ++offs) {
         //     *(data + offs) = mem[(addr + offs) % mem.size()];
         // }
@@ -86,7 +86,7 @@ template <typename PLAT> struct memory_with_htif : public memory_elem {
         return iss::Ok;
     }
 
-    iss::status write_mem(iss::access_type access, uint64_t addr, unsigned length, uint8_t const* data) {
+    iss::status write_mem(iss::access_type access, uint32_t space, uint64_t addr, unsigned length, uint8_t const* data) {
         auto& p = mem(addr / mem.page_size);
         auto offs = addr & mem.page_addr_mask;
         if((offs + length) > mem.page_size) {
diff --git a/src/iss/mem/mmu.h b/src/iss/mem/mmu.h
index d945e6f..1f4f7c9 100644
--- a/src/iss/mem/mmu.h
+++ b/src/iss/mem/mmu.h
@@ -107,28 +107,28 @@ template <typename PLAT> struct mmu : public memory_elem {
         return (effective_priv(type) == arch::PRIV_U || effective_priv(type) == arch::PRIV_S) && vm_setting.levels;
     }
 
-    iss::status read_mem(iss::access_type access, uint64_t addr, unsigned length, uint8_t* data) {
+    iss::status read_mem(iss::access_type access, uint32_t space, uint64_t addr, unsigned length, uint8_t* data) {
         if(unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK) && needs_translation(access))) { // we may cross a page boundary
             auto split_addr = (addr + length) & ~PGMASK;
             auto len1 = split_addr - addr;
-            auto res = down_stream_mem.rd_mem(access, virt2phys(access, addr), len1, data);
+            auto res = down_stream_mem.rd_mem(access, space, virt2phys(access, addr), len1, data);
             if(res == iss::Ok)
-                res = down_stream_mem.rd_mem(access, virt2phys(access, split_addr), length - len1, data + len1);
+                res = down_stream_mem.rd_mem(access, space, virt2phys(access, split_addr), length - len1, data + len1);
             return res;
         }
-        return down_stream_mem.rd_mem(access, needs_translation(access) ? virt2phys(access, addr) : addr, length, data);
+        return down_stream_mem.rd_mem(access, space, needs_translation(access) ? virt2phys(access, addr) : addr, length, data);
     }
 
-    iss::status write_mem(iss::access_type access, uint64_t addr, unsigned length, uint8_t const* data) {
+    iss::status write_mem(iss::access_type access, uint32_t space, uint64_t addr, unsigned length, uint8_t const* data) {
         if(unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK) && needs_translation(access))) { // we may cross a page boundary
             auto split_addr = (addr + length) & ~PGMASK;
             auto len1 = split_addr - addr;
-            auto res = down_stream_mem.wr_mem(access, virt2phys(access, addr), len1, data);
+            auto res = down_stream_mem.wr_mem(access, space, virt2phys(access, addr), len1, data);
             if(res == iss::Ok)
-                res = down_stream_mem.wr_mem(access, virt2phys(access, split_addr), length - len1, data + len1);
+                res = down_stream_mem.wr_mem(access, space, virt2phys(access, split_addr), length - len1, data + len1);
             return res;
         }
-        return down_stream_mem.wr_mem(access, needs_translation(access) ? virt2phys(access, addr) : addr, length, data);
+        return down_stream_mem.wr_mem(access, space, needs_translation(access) ? virt2phys(access, addr) : addr, length, data);
     }
 
     iss::status read_plain(unsigned addr, reg_t& val) {
@@ -237,8 +237,8 @@ template <typename PLAT> uint64_t mmu<PLAT>::virt2phys(iss::access_type access,
         for(int i = vm_setting.levels - 1; i >= 0; i--) {
             const int ptshift = i * vm_setting.idxbits;
             const reg_t idx = (addr >> (PGSHIFT + ptshift)) & ((1 << vm_setting.idxbits) - 1);
-            const iss::status res =
-                down_stream_mem.rd_mem(iss::access_type::READ, base + idx * vm_setting.ptesize, vm_setting.ptesize, (uint8_t*)&pte);
+            const iss::status res = down_stream_mem.rd_mem(iss::access_type::READ, arch::traits<PLAT>::MEM, base + idx * vm_setting.ptesize,
+                                                           vm_setting.ptesize, (uint8_t*)&pte);
             if(res != iss::status::Ok) {
                 CPPLOG(DEBUG) << "Access fault when trying to read next pte";
                 switch(type) {
diff --git a/src/iss/mem/pmp.h b/src/iss/mem/pmp.h
index 062828e..e60be5b 100644
--- a/src/iss/mem/pmp.h
+++ b/src/iss/mem/pmp.h
@@ -115,7 +115,7 @@ template <typename PLAT> struct pmp : public memory_elem {
     void set_next(memory_if mem) override { down_stream_mem = mem; }
 
 private:
-    iss::status read_mem(iss::access_type access, uint64_t addr, unsigned length, uint8_t* data) {
+    iss::status read_mem(iss::access_type access, uint32_t space, uint64_t addr, unsigned length, uint8_t* data) {
         if(!pmp_check(access, addr, length) && !is_debug(access)) {
             hart_if.fault_data = addr;
             if(is_debug(access))
@@ -123,10 +123,10 @@ template <typename PLAT> struct pmp : public memory_elem {
             hart_if.reg.trap_state = (1UL << 31) | ((access == access_type::FETCH ? 1 : 5) << 16); // issue trap 1
             return iss::Err;
         }
-        return down_stream_mem.rd_mem(access, addr, length, data);
+        return down_stream_mem.rd_mem(access, space, addr, length, data);
     }
 
-    iss::status write_mem(iss::access_type access, uint64_t addr, unsigned length, uint8_t const* data) {
+    iss::status write_mem(iss::access_type access, uint32_t space, uint64_t addr, unsigned length, uint8_t const* data) {
         if(!pmp_check(access, addr, length) && !is_debug(access)) {
             hart_if.fault_data = addr;
             if(is_debug(access))
@@ -134,7 +134,7 @@ template <typename PLAT> struct pmp : public memory_elem {
             hart_if.reg.trap_state = (1UL << 31) | (7 << 16); // issue trap 1
             return iss::Err;
         }
-        return down_stream_mem.wr_mem(access, addr, length, data);
+        return down_stream_mem.wr_mem(access, space, addr, length, data);
     }
 
     iss::status read_plain(unsigned addr, reg_t& val) {

From cf39936a89f31de2cd02a3517c4aa69bf22434ef Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Sat, 15 Nov 2025 16:01:02 +0100
Subject: [PATCH 23/77] adds space behavior for mmu and pmp Incase space is not
 MEM hands it to the downstream mem

---
 src/iss/mem/mmu.h | 16 ++++++++++------
 src/iss/mem/pmp.h |  5 +++--
 2 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/src/iss/mem/mmu.h b/src/iss/mem/mmu.h
index 1f4f7c9..9889814 100644
--- a/src/iss/mem/mmu.h
+++ b/src/iss/mem/mmu.h
@@ -33,6 +33,7 @@
  ******************************************************************************/
 
 #include "iss/arch/riscv_hart_common.h"
+#include "iss/arch/traits.h"
 #include "iss/arch_if.h"
 #include "iss/vm_types.h"
 #include "memory_if.h"
@@ -103,12 +104,14 @@ template <typename PLAT> struct mmu : public memory_elem {
         return priv;
     }
 
-    bool needs_translation(iss::access_type type) {
-        return (effective_priv(type) == arch::PRIV_U || effective_priv(type) == arch::PRIV_S) && vm_setting.levels;
+    bool needs_translation(iss::access_type type, uint32_t space) {
+        return likely(space == arch::traits<PLAT>::MEM) && (effective_priv(type) == arch::PRIV_U || effective_priv(type) == arch::PRIV_S) &&
+               vm_setting.levels;
     }
 
     iss::status read_mem(iss::access_type access, uint32_t space, uint64_t addr, unsigned length, uint8_t* data) {
-        if(unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK) && needs_translation(access))) { // we may cross a page boundary
+        if(unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK) &&
+                    needs_translation(access, space))) { // we may cross a page boundary
             auto split_addr = (addr + length) & ~PGMASK;
             auto len1 = split_addr - addr;
             auto res = down_stream_mem.rd_mem(access, space, virt2phys(access, addr), len1, data);
@@ -116,11 +119,12 @@ template <typename PLAT> struct mmu : public memory_elem {
                 res = down_stream_mem.rd_mem(access, space, virt2phys(access, split_addr), length - len1, data + len1);
             return res;
         }
-        return down_stream_mem.rd_mem(access, space, needs_translation(access) ? virt2phys(access, addr) : addr, length, data);
+        return down_stream_mem.rd_mem(access, space, needs_translation(access, space) ? virt2phys(access, addr) : addr, length, data);
     }
 
     iss::status write_mem(iss::access_type access, uint32_t space, uint64_t addr, unsigned length, uint8_t const* data) {
-        if(unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK) && needs_translation(access))) { // we may cross a page boundary
+        if(unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK) &&
+                    needs_translation(access, space))) { // we may cross a page boundary
             auto split_addr = (addr + length) & ~PGMASK;
             auto len1 = split_addr - addr;
             auto res = down_stream_mem.wr_mem(access, space, virt2phys(access, addr), len1, data);
@@ -128,7 +132,7 @@ template <typename PLAT> struct mmu : public memory_elem {
                 res = down_stream_mem.wr_mem(access, space, virt2phys(access, split_addr), length - len1, data + len1);
             return res;
         }
-        return down_stream_mem.wr_mem(access, space, needs_translation(access) ? virt2phys(access, addr) : addr, length, data);
+        return down_stream_mem.wr_mem(access, space, needs_translation(access, space) ? virt2phys(access, addr) : addr, length, data);
     }
 
     iss::status read_plain(unsigned addr, reg_t& val) {
diff --git a/src/iss/mem/pmp.h b/src/iss/mem/pmp.h
index e60be5b..0487424 100644
--- a/src/iss/mem/pmp.h
+++ b/src/iss/mem/pmp.h
@@ -33,6 +33,7 @@
  ******************************************************************************/
 
 #include "iss/arch/riscv_hart_common.h"
+#include "iss/arch/traits.h"
 #include "iss/vm_types.h"
 #include "memory_if.h"
 #include <util/logging.h>
@@ -116,7 +117,7 @@ template <typename PLAT> struct pmp : public memory_elem {
 
 private:
     iss::status read_mem(iss::access_type access, uint32_t space, uint64_t addr, unsigned length, uint8_t* data) {
-        if(!pmp_check(access, addr, length) && !is_debug(access)) {
+        if(!pmp_check(access, addr, length) && space != arch::traits<PLAT>::MEM && !is_debug(access)) {
             hart_if.fault_data = addr;
             if(is_debug(access))
                 throw trap_access(0, addr);
@@ -127,7 +128,7 @@ template <typename PLAT> struct pmp : public memory_elem {
     }
 
     iss::status write_mem(iss::access_type access, uint32_t space, uint64_t addr, unsigned length, uint8_t const* data) {
-        if(!pmp_check(access, addr, length) && !is_debug(access)) {
+        if(!pmp_check(access, addr, length) && space != arch::traits<PLAT>::MEM && !is_debug(access)) {
             hart_if.fault_data = addr;
             if(is_debug(access))
                 throw trap_access(0, addr);

From 6b75a4ddc40b59f59406d0d8bc0cc6b28fd82c80 Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Sun, 16 Nov 2025 17:32:14 +0100
Subject: [PATCH 24/77] introduces mem space sizes to CORENAME.h, updates
 generated files technically the mem size is off by one for 64 bit cores

---
 gen_input/templates/CORENAME.h.gtl | 15 +++++++++++++++
 src/iss/arch/rv32gc.h              | 17 +++++++++++++----
 src/iss/arch/rv32gcv.h             | 17 +++++++++++++----
 src/iss/arch/rv32i.h               | 17 +++++++++++++----
 src/iss/arch/rv32imac.h            | 17 +++++++++++++----
 src/iss/arch/rv64gc.h              | 17 +++++++++++++----
 src/iss/arch/rv64gcv.h             | 17 +++++++++++++----
 src/iss/arch/rv64i.h               | 17 +++++++++++++----
 src/iss/arch/tgc5c.h               | 17 +++++++++++++----
 src/vm/interp/vm_rv32gc.cpp        |  2 +-
 src/vm/interp/vm_rv32gcv.cpp       |  2 +-
 src/vm/interp/vm_rv32i.cpp         |  2 +-
 src/vm/interp/vm_rv32imac.cpp      |  2 +-
 src/vm/interp/vm_rv64gc.cpp        |  2 +-
 src/vm/interp/vm_rv64gcv.cpp       |  2 +-
 src/vm/interp/vm_rv64i.cpp         |  2 +-
 src/vm/interp/vm_tgc5c.cpp         |  2 +-
 17 files changed, 127 insertions(+), 40 deletions(-)

diff --git a/gen_input/templates/CORENAME.h.gtl b/gen_input/templates/CORENAME.h.gtl
index f9e729f..53f5d41 100644
--- a/gen_input/templates/CORENAME.h.gtl
+++ b/gen_input/templates/CORENAME.h.gtl
@@ -46,6 +46,15 @@ def nativeSize(int size){
 def getCString(def val){
     return val.toString()+'ULL'
 }
+def overflowsafeSize(BigInteger val){
+    switch(val) {
+        //case 256:                   return "std::numeric_limits<uint8_t>::max()";
+        //case 65536:                 return "std::numeric_limits<uint16_t>::max()";
+        //case 4294967296:            return "std::numeric_limits<uint32_t>::max()";
+        case 18446744073709551616:  return "std::numeric_limits<uint64_t>::max()";
+        default: return val;
+    }
+}
 %>
 #ifndef _${coreDef.name.toUpperCase()}_H_
 #define _${coreDef.name.toUpperCase()}_H_
@@ -202,6 +211,12 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
 
     enum mem_type_e { ${spaces.collect{it.name}.join(', ')}, IMEM = MEM };
     
+    static constexpr std::array<const uint64_t, ${spaces.size()}> mem_sizes{{
+        ${spaces.collect{overflowsafeSize(it.value)}.join(',\n        ')}
+    }};
+
+    static constexpr uint64_t max_mem_size =  ${overflowsafeSize(spaces.collect{it.value}.max())};
+
     enum class opcode_e {<%instructions.eachWithIndex{instr, index -> %>
         ${instr.instruction.name} = ${index},<%}%>
         MAX_OPCODE
diff --git a/src/iss/arch/rv32gc.h b/src/iss/arch/rv32gc.h
index 453139f..f105c10 100644
--- a/src/iss/arch/rv32gc.h
+++ b/src/iss/arch/rv32gc.h
@@ -287,10 +287,10 @@ template <> struct traits<rv32gc> {
         RV_IRQ_VS_SOFT=2ULL, RV_IRQ_M_SOFT=3ULL, RV_IRQ_U_TIMER=4ULL, RV_IRQ_S_TIMER=5ULL,
         RV_IRQ_VS_TIMER=6ULL, RV_IRQ_M_TIMER=7ULL, RV_IRQ_U_EXT=8ULL, RV_IRQ_S_EXT=9ULL,
         RV_IRQ_VS_EXT=10ULL, RV_IRQ_M_EXT=11ULL, RV_IRQ_S_GEXT=12ULL, RV_IRQ_COP=12ULL,
-        RV_IRQ_LCOF=13ULL, RV_MIP_USIP=1ULL, RV_MIP_SSIP=1ULL, RV_MIP_VSSIP=1ULL,
-        RV_MIP_MSIP=1ULL, RV_MIP_UTIP=1ULL, RV_MIP_STIP=1ULL, RV_MIP_VSTIP=1ULL,
-        RV_MIP_MTIP=1ULL, RV_MIP_UEIP=1ULL, RV_MIP_SEIP=1ULL, RV_MIP_VSEIP=1ULL,
-        RV_MIP_MEIP=1ULL, RV_MIP_SGEIP=1ULL, RV_MIP_LCOFIP=1ULL, XLEN=32ULL,
+        RV_IRQ_LCOF=13ULL, RV_MIP_USIP=1ULL, RV_MIP_SSIP=2ULL, RV_MIP_VSSIP=4ULL,
+        RV_MIP_MSIP=8ULL, RV_MIP_UTIP=16ULL, RV_MIP_STIP=32ULL, RV_MIP_VSTIP=64ULL,
+        RV_MIP_MTIP=128ULL, RV_MIP_UEIP=256ULL, RV_MIP_SEIP=512ULL, RV_MIP_VSEIP=1024ULL,
+        RV_MIP_MEIP=2048ULL, RV_MIP_SGEIP=4096ULL, RV_MIP_LCOFIP=8192ULL, XLEN=32ULL,
         FLEN=64ULL, INSTR_ALIGNMENT=2ULL, RFS=32ULL, fence=0ULL,
         fencei=1ULL, fencevma=2ULL, CSR_SIZE=4096ULL, MUL_LEN=64ULL,
         FFLAG_MASK=31ULL, MISA_VAL=1073746221ULL, MARCHID_VAL=0ULL, CLIC_NUM_IRQ=0ULL
@@ -479,6 +479,15 @@ template <> struct traits<rv32gc> {
 
     enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = MEM };
     
+    static constexpr std::array<const uint64_t, 4> mem_sizes{{
+        4294967296,
+        8,
+        8,
+        4096
+    }};
+
+    static constexpr uint64_t max_mem_size =  4294967296;
+
     enum class opcode_e {
         LUI = 0,
         AUIPC = 1,
diff --git a/src/iss/arch/rv32gcv.h b/src/iss/arch/rv32gcv.h
index cb17465..dca317e 100644
--- a/src/iss/arch/rv32gcv.h
+++ b/src/iss/arch/rv32gcv.h
@@ -324,10 +324,10 @@ template <> struct traits<rv32gcv> {
         RV_IRQ_VS_SOFT=2ULL, RV_IRQ_M_SOFT=3ULL, RV_IRQ_U_TIMER=4ULL, RV_IRQ_S_TIMER=5ULL,
         RV_IRQ_VS_TIMER=6ULL, RV_IRQ_M_TIMER=7ULL, RV_IRQ_U_EXT=8ULL, RV_IRQ_S_EXT=9ULL,
         RV_IRQ_VS_EXT=10ULL, RV_IRQ_M_EXT=11ULL, RV_IRQ_S_GEXT=12ULL, RV_IRQ_COP=12ULL,
-        RV_IRQ_LCOF=13ULL, RV_MIP_USIP=1ULL, RV_MIP_SSIP=1ULL, RV_MIP_VSSIP=1ULL,
-        RV_MIP_MSIP=1ULL, RV_MIP_UTIP=1ULL, RV_MIP_STIP=1ULL, RV_MIP_VSTIP=1ULL,
-        RV_MIP_MTIP=1ULL, RV_MIP_UEIP=1ULL, RV_MIP_SEIP=1ULL, RV_MIP_VSEIP=1ULL,
-        RV_MIP_MEIP=1ULL, RV_MIP_SGEIP=1ULL, RV_MIP_LCOFIP=1ULL, XLEN=32ULL,
+        RV_IRQ_LCOF=13ULL, RV_MIP_USIP=1ULL, RV_MIP_SSIP=2ULL, RV_MIP_VSSIP=4ULL,
+        RV_MIP_MSIP=8ULL, RV_MIP_UTIP=16ULL, RV_MIP_STIP=32ULL, RV_MIP_VSTIP=64ULL,
+        RV_MIP_MTIP=128ULL, RV_MIP_UEIP=256ULL, RV_MIP_SEIP=512ULL, RV_MIP_VSEIP=1024ULL,
+        RV_MIP_MEIP=2048ULL, RV_MIP_SGEIP=4096ULL, RV_MIP_LCOFIP=8192ULL, XLEN=32ULL,
         FLEN=64ULL, INSTR_ALIGNMENT=2ULL, RFS=32ULL, fence=0ULL,
         fencei=1ULL, fencevma=2ULL, CSR_SIZE=4096ULL, MUL_LEN=64ULL,
         FFLAG_MASK=31ULL, VLEN=256ULL, ELEN=32ULL, EEW_MAX=32ULL,
@@ -593,6 +593,15 @@ template <> struct traits<rv32gcv> {
 
     enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = MEM };
     
+    static constexpr std::array<const uint64_t, 4> mem_sizes{{
+        4294967296,
+        8,
+        8,
+        4096
+    }};
+
+    static constexpr uint64_t max_mem_size =  4294967296;
+
     enum class opcode_e {
         LUI = 0,
         AUIPC = 1,
diff --git a/src/iss/arch/rv32i.h b/src/iss/arch/rv32i.h
index 42d507f..0d074be 100644
--- a/src/iss/arch/rv32i.h
+++ b/src/iss/arch/rv32i.h
@@ -254,10 +254,10 @@ template <> struct traits<rv32i> {
         RV_IRQ_VS_SOFT=2ULL, RV_IRQ_M_SOFT=3ULL, RV_IRQ_U_TIMER=4ULL, RV_IRQ_S_TIMER=5ULL,
         RV_IRQ_VS_TIMER=6ULL, RV_IRQ_M_TIMER=7ULL, RV_IRQ_U_EXT=8ULL, RV_IRQ_S_EXT=9ULL,
         RV_IRQ_VS_EXT=10ULL, RV_IRQ_M_EXT=11ULL, RV_IRQ_S_GEXT=12ULL, RV_IRQ_COP=12ULL,
-        RV_IRQ_LCOF=13ULL, RV_MIP_USIP=1ULL, RV_MIP_SSIP=1ULL, RV_MIP_VSSIP=1ULL,
-        RV_MIP_MSIP=1ULL, RV_MIP_UTIP=1ULL, RV_MIP_STIP=1ULL, RV_MIP_VSTIP=1ULL,
-        RV_MIP_MTIP=1ULL, RV_MIP_UEIP=1ULL, RV_MIP_SEIP=1ULL, RV_MIP_VSEIP=1ULL,
-        RV_MIP_MEIP=1ULL, RV_MIP_SGEIP=1ULL, RV_MIP_LCOFIP=1ULL, XLEN=32ULL,
+        RV_IRQ_LCOF=13ULL, RV_MIP_USIP=1ULL, RV_MIP_SSIP=2ULL, RV_MIP_VSSIP=4ULL,
+        RV_MIP_MSIP=8ULL, RV_MIP_UTIP=16ULL, RV_MIP_STIP=32ULL, RV_MIP_VSTIP=64ULL,
+        RV_MIP_MTIP=128ULL, RV_MIP_UEIP=256ULL, RV_MIP_SEIP=512ULL, RV_MIP_VSEIP=1024ULL,
+        RV_MIP_MEIP=2048ULL, RV_MIP_SGEIP=4096ULL, RV_MIP_LCOFIP=8192ULL, XLEN=32ULL,
         FLEN=0ULL, INSTR_ALIGNMENT=4ULL, RFS=32ULL, fence=0ULL,
         fencei=1ULL, fencevma=2ULL, CSR_SIZE=4096ULL, MISA_VAL=1073742080ULL,
         MARCHID_VAL=0ULL, CLIC_NUM_IRQ=0ULL
@@ -380,6 +380,15 @@ template <> struct traits<rv32i> {
 
     enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = MEM };
     
+    static constexpr std::array<const uint64_t, 4> mem_sizes{{
+        4294967296,
+        8,
+        8,
+        4096
+    }};
+
+    static constexpr uint64_t max_mem_size =  4294967296;
+
     enum class opcode_e {
         LUI = 0,
         AUIPC = 1,
diff --git a/src/iss/arch/rv32imac.h b/src/iss/arch/rv32imac.h
index 1e0bdb9..71825c4 100644
--- a/src/iss/arch/rv32imac.h
+++ b/src/iss/arch/rv32imac.h
@@ -254,10 +254,10 @@ template <> struct traits<rv32imac> {
         RV_IRQ_VS_SOFT=2ULL, RV_IRQ_M_SOFT=3ULL, RV_IRQ_U_TIMER=4ULL, RV_IRQ_S_TIMER=5ULL,
         RV_IRQ_VS_TIMER=6ULL, RV_IRQ_M_TIMER=7ULL, RV_IRQ_U_EXT=8ULL, RV_IRQ_S_EXT=9ULL,
         RV_IRQ_VS_EXT=10ULL, RV_IRQ_M_EXT=11ULL, RV_IRQ_S_GEXT=12ULL, RV_IRQ_COP=12ULL,
-        RV_IRQ_LCOF=13ULL, RV_MIP_USIP=1ULL, RV_MIP_SSIP=1ULL, RV_MIP_VSSIP=1ULL,
-        RV_MIP_MSIP=1ULL, RV_MIP_UTIP=1ULL, RV_MIP_STIP=1ULL, RV_MIP_VSTIP=1ULL,
-        RV_MIP_MTIP=1ULL, RV_MIP_UEIP=1ULL, RV_MIP_SEIP=1ULL, RV_MIP_VSEIP=1ULL,
-        RV_MIP_MEIP=1ULL, RV_MIP_SGEIP=1ULL, RV_MIP_LCOFIP=1ULL, XLEN=32ULL,
+        RV_IRQ_LCOF=13ULL, RV_MIP_USIP=1ULL, RV_MIP_SSIP=2ULL, RV_MIP_VSSIP=4ULL,
+        RV_MIP_MSIP=8ULL, RV_MIP_UTIP=16ULL, RV_MIP_STIP=32ULL, RV_MIP_VSTIP=64ULL,
+        RV_MIP_MTIP=128ULL, RV_MIP_UEIP=256ULL, RV_MIP_SEIP=512ULL, RV_MIP_VSEIP=1024ULL,
+        RV_MIP_MEIP=2048ULL, RV_MIP_SGEIP=4096ULL, RV_MIP_LCOFIP=8192ULL, XLEN=32ULL,
         FLEN=0ULL, INSTR_ALIGNMENT=2ULL, RFS=32ULL, fence=0ULL,
         fencei=1ULL, fencevma=2ULL, CSR_SIZE=4096ULL, MUL_LEN=64ULL,
         MISA_VAL=1073746181ULL, MARCHID_VAL=0ULL, CLIC_NUM_IRQ=0ULL
@@ -380,6 +380,15 @@ template <> struct traits<rv32imac> {
 
     enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = MEM };
     
+    static constexpr std::array<const uint64_t, 4> mem_sizes{{
+        4294967296,
+        8,
+        8,
+        4096
+    }};
+
+    static constexpr uint64_t max_mem_size =  4294967296;
+
     enum class opcode_e {
         LUI = 0,
         AUIPC = 1,
diff --git a/src/iss/arch/rv64gc.h b/src/iss/arch/rv64gc.h
index d76cdd2..7081f29 100644
--- a/src/iss/arch/rv64gc.h
+++ b/src/iss/arch/rv64gc.h
@@ -287,10 +287,10 @@ template <> struct traits<rv64gc> {
         RV_IRQ_VS_SOFT=2ULL, RV_IRQ_M_SOFT=3ULL, RV_IRQ_U_TIMER=4ULL, RV_IRQ_S_TIMER=5ULL,
         RV_IRQ_VS_TIMER=6ULL, RV_IRQ_M_TIMER=7ULL, RV_IRQ_U_EXT=8ULL, RV_IRQ_S_EXT=9ULL,
         RV_IRQ_VS_EXT=10ULL, RV_IRQ_M_EXT=11ULL, RV_IRQ_S_GEXT=12ULL, RV_IRQ_COP=12ULL,
-        RV_IRQ_LCOF=13ULL, RV_MIP_USIP=1ULL, RV_MIP_SSIP=1ULL, RV_MIP_VSSIP=1ULL,
-        RV_MIP_MSIP=1ULL, RV_MIP_UTIP=1ULL, RV_MIP_STIP=1ULL, RV_MIP_VSTIP=1ULL,
-        RV_MIP_MTIP=1ULL, RV_MIP_UEIP=1ULL, RV_MIP_SEIP=1ULL, RV_MIP_VSEIP=1ULL,
-        RV_MIP_MEIP=1ULL, RV_MIP_SGEIP=1ULL, RV_MIP_LCOFIP=1ULL, XLEN=64ULL,
+        RV_IRQ_LCOF=13ULL, RV_MIP_USIP=1ULL, RV_MIP_SSIP=2ULL, RV_MIP_VSSIP=4ULL,
+        RV_MIP_MSIP=8ULL, RV_MIP_UTIP=16ULL, RV_MIP_STIP=32ULL, RV_MIP_VSTIP=64ULL,
+        RV_MIP_MTIP=128ULL, RV_MIP_UEIP=256ULL, RV_MIP_SEIP=512ULL, RV_MIP_VSEIP=1024ULL,
+        RV_MIP_MEIP=2048ULL, RV_MIP_SGEIP=4096ULL, RV_MIP_LCOFIP=8192ULL, XLEN=64ULL,
         FLEN=64ULL, INSTR_ALIGNMENT=2ULL, RFS=32ULL, fence=0ULL,
         fencei=1ULL, fencevma=2ULL, CSR_SIZE=4096ULL, MUL_LEN=128ULL,
         FFLAG_MASK=31ULL, MISA_VAL=9223372036854780205ULL, MARCHID_VAL=0ULL, CLIC_NUM_IRQ=0ULL
@@ -479,6 +479,15 @@ template <> struct traits<rv64gc> {
 
     enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = MEM };
     
+    static constexpr std::array<const uint64_t, 4> mem_sizes{{
+        std::numeric_limits<uint64_t>::max(),
+        8,
+        8,
+        4096
+    }};
+
+    static constexpr uint64_t max_mem_size =  std::numeric_limits<uint64_t>::max();
+
     enum class opcode_e {
         LUI = 0,
         AUIPC = 1,
diff --git a/src/iss/arch/rv64gcv.h b/src/iss/arch/rv64gcv.h
index fc8f49a..5a70c40 100644
--- a/src/iss/arch/rv64gcv.h
+++ b/src/iss/arch/rv64gcv.h
@@ -324,10 +324,10 @@ template <> struct traits<rv64gcv> {
         RV_IRQ_VS_SOFT=2ULL, RV_IRQ_M_SOFT=3ULL, RV_IRQ_U_TIMER=4ULL, RV_IRQ_S_TIMER=5ULL,
         RV_IRQ_VS_TIMER=6ULL, RV_IRQ_M_TIMER=7ULL, RV_IRQ_U_EXT=8ULL, RV_IRQ_S_EXT=9ULL,
         RV_IRQ_VS_EXT=10ULL, RV_IRQ_M_EXT=11ULL, RV_IRQ_S_GEXT=12ULL, RV_IRQ_COP=12ULL,
-        RV_IRQ_LCOF=13ULL, RV_MIP_USIP=1ULL, RV_MIP_SSIP=1ULL, RV_MIP_VSSIP=1ULL,
-        RV_MIP_MSIP=1ULL, RV_MIP_UTIP=1ULL, RV_MIP_STIP=1ULL, RV_MIP_VSTIP=1ULL,
-        RV_MIP_MTIP=1ULL, RV_MIP_UEIP=1ULL, RV_MIP_SEIP=1ULL, RV_MIP_VSEIP=1ULL,
-        RV_MIP_MEIP=1ULL, RV_MIP_SGEIP=1ULL, RV_MIP_LCOFIP=1ULL, XLEN=64ULL,
+        RV_IRQ_LCOF=13ULL, RV_MIP_USIP=1ULL, RV_MIP_SSIP=2ULL, RV_MIP_VSSIP=4ULL,
+        RV_MIP_MSIP=8ULL, RV_MIP_UTIP=16ULL, RV_MIP_STIP=32ULL, RV_MIP_VSTIP=64ULL,
+        RV_MIP_MTIP=128ULL, RV_MIP_UEIP=256ULL, RV_MIP_SEIP=512ULL, RV_MIP_VSEIP=1024ULL,
+        RV_MIP_MEIP=2048ULL, RV_MIP_SGEIP=4096ULL, RV_MIP_LCOFIP=8192ULL, XLEN=64ULL,
         FLEN=64ULL, INSTR_ALIGNMENT=2ULL, RFS=32ULL, fence=0ULL,
         fencei=1ULL, fencevma=2ULL, CSR_SIZE=4096ULL, MUL_LEN=128ULL,
         FFLAG_MASK=31ULL, VLEN=512ULL, ELEN=64ULL, EEW_MAX=64ULL,
@@ -593,6 +593,15 @@ template <> struct traits<rv64gcv> {
 
     enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = MEM };
     
+    static constexpr std::array<const uint64_t, 4> mem_sizes{{
+        std::numeric_limits<uint64_t>::max(),
+        8,
+        8,
+        4096
+    }};
+
+    static constexpr uint64_t max_mem_size =  std::numeric_limits<uint64_t>::max();
+
     enum class opcode_e {
         LUI = 0,
         AUIPC = 1,
diff --git a/src/iss/arch/rv64i.h b/src/iss/arch/rv64i.h
index 664f28c..a5d1afd 100644
--- a/src/iss/arch/rv64i.h
+++ b/src/iss/arch/rv64i.h
@@ -254,10 +254,10 @@ template <> struct traits<rv64i> {
         RV_IRQ_VS_SOFT=2ULL, RV_IRQ_M_SOFT=3ULL, RV_IRQ_U_TIMER=4ULL, RV_IRQ_S_TIMER=5ULL,
         RV_IRQ_VS_TIMER=6ULL, RV_IRQ_M_TIMER=7ULL, RV_IRQ_U_EXT=8ULL, RV_IRQ_S_EXT=9ULL,
         RV_IRQ_VS_EXT=10ULL, RV_IRQ_M_EXT=11ULL, RV_IRQ_S_GEXT=12ULL, RV_IRQ_COP=12ULL,
-        RV_IRQ_LCOF=13ULL, RV_MIP_USIP=1ULL, RV_MIP_SSIP=1ULL, RV_MIP_VSSIP=1ULL,
-        RV_MIP_MSIP=1ULL, RV_MIP_UTIP=1ULL, RV_MIP_STIP=1ULL, RV_MIP_VSTIP=1ULL,
-        RV_MIP_MTIP=1ULL, RV_MIP_UEIP=1ULL, RV_MIP_SEIP=1ULL, RV_MIP_VSEIP=1ULL,
-        RV_MIP_MEIP=1ULL, RV_MIP_SGEIP=1ULL, RV_MIP_LCOFIP=1ULL, XLEN=64ULL,
+        RV_IRQ_LCOF=13ULL, RV_MIP_USIP=1ULL, RV_MIP_SSIP=2ULL, RV_MIP_VSSIP=4ULL,
+        RV_MIP_MSIP=8ULL, RV_MIP_UTIP=16ULL, RV_MIP_STIP=32ULL, RV_MIP_VSTIP=64ULL,
+        RV_MIP_MTIP=128ULL, RV_MIP_UEIP=256ULL, RV_MIP_SEIP=512ULL, RV_MIP_VSEIP=1024ULL,
+        RV_MIP_MEIP=2048ULL, RV_MIP_SGEIP=4096ULL, RV_MIP_LCOFIP=8192ULL, XLEN=64ULL,
         FLEN=0ULL, INSTR_ALIGNMENT=4ULL, RFS=32ULL, fence=0ULL,
         fencei=1ULL, fencevma=2ULL, CSR_SIZE=4096ULL, MISA_VAL=2147483904ULL,
         MARCHID_VAL=0ULL, CLIC_NUM_IRQ=0ULL
@@ -380,6 +380,15 @@ template <> struct traits<rv64i> {
 
     enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = MEM };
     
+    static constexpr std::array<const uint64_t, 4> mem_sizes{{
+        std::numeric_limits<uint64_t>::max(),
+        8,
+        8,
+        4096
+    }};
+
+    static constexpr uint64_t max_mem_size =  std::numeric_limits<uint64_t>::max();
+
     enum class opcode_e {
         LUI = 0,
         AUIPC = 1,
diff --git a/src/iss/arch/tgc5c.h b/src/iss/arch/tgc5c.h
index 3ce02ec..f96f115 100644
--- a/src/iss/arch/tgc5c.h
+++ b/src/iss/arch/tgc5c.h
@@ -254,10 +254,10 @@ template <> struct traits<tgc5c> {
         RV_IRQ_VS_SOFT=2ULL, RV_IRQ_M_SOFT=3ULL, RV_IRQ_U_TIMER=4ULL, RV_IRQ_S_TIMER=5ULL,
         RV_IRQ_VS_TIMER=6ULL, RV_IRQ_M_TIMER=7ULL, RV_IRQ_U_EXT=8ULL, RV_IRQ_S_EXT=9ULL,
         RV_IRQ_VS_EXT=10ULL, RV_IRQ_M_EXT=11ULL, RV_IRQ_S_GEXT=12ULL, RV_IRQ_COP=12ULL,
-        RV_IRQ_LCOF=13ULL, RV_MIP_USIP=1ULL, RV_MIP_SSIP=1ULL, RV_MIP_VSSIP=1ULL,
-        RV_MIP_MSIP=1ULL, RV_MIP_UTIP=1ULL, RV_MIP_STIP=1ULL, RV_MIP_VSTIP=1ULL,
-        RV_MIP_MTIP=1ULL, RV_MIP_UEIP=1ULL, RV_MIP_SEIP=1ULL, RV_MIP_VSEIP=1ULL,
-        RV_MIP_MEIP=1ULL, RV_MIP_SGEIP=1ULL, RV_MIP_LCOFIP=1ULL, XLEN=32ULL,
+        RV_IRQ_LCOF=13ULL, RV_MIP_USIP=1ULL, RV_MIP_SSIP=2ULL, RV_MIP_VSSIP=4ULL,
+        RV_MIP_MSIP=8ULL, RV_MIP_UTIP=16ULL, RV_MIP_STIP=32ULL, RV_MIP_VSTIP=64ULL,
+        RV_MIP_MTIP=128ULL, RV_MIP_UEIP=256ULL, RV_MIP_SEIP=512ULL, RV_MIP_VSEIP=1024ULL,
+        RV_MIP_MEIP=2048ULL, RV_MIP_SGEIP=4096ULL, RV_MIP_LCOFIP=8192ULL, XLEN=32ULL,
         FLEN=0ULL, INSTR_ALIGNMENT=2ULL, RFS=32ULL, fence=0ULL,
         fencei=1ULL, fencevma=2ULL, CSR_SIZE=4096ULL, MUL_LEN=64ULL,
         MISA_VAL=1073746180ULL, MARCHID_VAL=2147483651ULL, CLIC_NUM_IRQ=0ULL
@@ -380,6 +380,15 @@ template <> struct traits<tgc5c> {
 
     enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = MEM };
     
+    static constexpr std::array<const uint64_t, 4> mem_sizes{{
+        4294967296,
+        8,
+        8,
+        4096
+    }};
+
+    static constexpr uint64_t max_mem_size =  4294967296;
+
     enum class opcode_e {
         LUI = 0,
         AUIPC = 1,
diff --git a/src/vm/interp/vm_rv32gc.cpp b/src/vm/interp/vm_rv32gc.cpp
index 68cc80c..f03c301 100644
--- a/src/vm/interp/vm_rv32gc.cpp
+++ b/src/vm/interp/vm_rv32gc.cpp
@@ -4927,8 +4927,8 @@ std::unique_ptr<vm_if> create<arch::rv32gc>(arch::rv32gc *core, unsigned short p
 } // namespace iss
 
 #include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {
diff --git a/src/vm/interp/vm_rv32gcv.cpp b/src/vm/interp/vm_rv32gcv.cpp
index ca6fa66..95c7ebf 100644
--- a/src/vm/interp/vm_rv32gcv.cpp
+++ b/src/vm/interp/vm_rv32gcv.cpp
@@ -29811,8 +29811,8 @@ std::unique_ptr<vm_if> create<arch::rv32gcv>(arch::rv32gcv *core, unsigned short
 } // namespace iss
 
 #include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {
diff --git a/src/vm/interp/vm_rv32i.cpp b/src/vm/interp/vm_rv32i.cpp
index d57b9ce..cde4275 100644
--- a/src/vm/interp/vm_rv32i.cpp
+++ b/src/vm/interp/vm_rv32i.cpp
@@ -1794,8 +1794,8 @@ std::unique_ptr<vm_if> create<arch::rv32i>(arch::rv32i *core, unsigned short por
 } // namespace iss
 
 #include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {
diff --git a/src/vm/interp/vm_rv32imac.cpp b/src/vm/interp/vm_rv32imac.cpp
index 4f6ab93..1a09e34 100644
--- a/src/vm/interp/vm_rv32imac.cpp
+++ b/src/vm/interp/vm_rv32imac.cpp
@@ -3196,8 +3196,8 @@ std::unique_ptr<vm_if> create<arch::rv32imac>(arch::rv32imac *core, unsigned sho
 } // namespace iss
 
 #include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {
diff --git a/src/vm/interp/vm_rv64gc.cpp b/src/vm/interp/vm_rv64gc.cpp
index 3e31536..641d3d0 100644
--- a/src/vm/interp/vm_rv64gc.cpp
+++ b/src/vm/interp/vm_rv64gc.cpp
@@ -6270,8 +6270,8 @@ std::unique_ptr<vm_if> create<arch::rv64gc>(arch::rv64gc *core, unsigned short p
 } // namespace iss
 
 #include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {
diff --git a/src/vm/interp/vm_rv64gcv.cpp b/src/vm/interp/vm_rv64gcv.cpp
index a1afbf7..a930efe 100644
--- a/src/vm/interp/vm_rv64gcv.cpp
+++ b/src/vm/interp/vm_rv64gcv.cpp
@@ -31154,8 +31154,8 @@ std::unique_ptr<vm_if> create<arch::rv64gcv>(arch::rv64gcv *core, unsigned short
 } // namespace iss
 
 #include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {
diff --git a/src/vm/interp/vm_rv64i.cpp b/src/vm/interp/vm_rv64i.cpp
index bbf20d6..828fdef 100644
--- a/src/vm/interp/vm_rv64i.cpp
+++ b/src/vm/interp/vm_rv64i.cpp
@@ -2160,8 +2160,8 @@ std::unique_ptr<vm_if> create<arch::rv64i>(arch::rv64i *core, unsigned short por
 } // namespace iss
 
 #include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {
diff --git a/src/vm/interp/vm_tgc5c.cpp b/src/vm/interp/vm_tgc5c.cpp
index b47787a..ea25afd 100644
--- a/src/vm/interp/vm_tgc5c.cpp
+++ b/src/vm/interp/vm_tgc5c.cpp
@@ -2781,8 +2781,8 @@ std::unique_ptr<vm_if> create<arch::tgc5c>(arch::tgc5c *core, unsigned short por
 } // namespace iss
 
 #include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {

From 58384aa3e8b4b166f68f43e2b4c18c4eead69dee Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Mon, 17 Nov 2025 08:29:00 +0100
Subject: [PATCH 25/77] adds a memory for each space to memory_with_htif

---
 src/iss/mem/memory_with_htif.h | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/iss/mem/memory_with_htif.h b/src/iss/mem/memory_with_htif.h
index 43b94fb..ec57b08 100644
--- a/src/iss/mem/memory_with_htif.h
+++ b/src/iss/mem/memory_with_htif.h
@@ -36,8 +36,10 @@
 #define _MEMORY_WITH_HTIF_
 
 #include "iss/arch/riscv_hart_common.h"
+#include "iss/arch/traits.h"
 #include "iss/vm_types.h"
 #include "memory_if.h"
+#include <array>
 #include <cstdlib>
 #include <util/logging.h>
 #include <util/sparse_array.h>
@@ -67,6 +69,7 @@ template <typename PLAT> struct memory_with_htif : public memory_elem {
         // for(auto offs = 0U; offs < length; ++offs) {
         //     *(data + offs) = mem[(addr + offs) % mem.size()];
         // }
+        mem_type mem = memories[space];
         if(mem.is_allocated(addr)) {
             const auto& p = mem(addr / mem.page_size);
             auto offs = addr & mem.page_addr_mask;
@@ -87,6 +90,7 @@ template <typename PLAT> struct memory_with_htif : public memory_elem {
     }
 
     iss::status write_mem(iss::access_type access, uint32_t space, uint64_t addr, unsigned length, uint8_t const* data) {
+        mem_type mem = memories[space];
         auto& p = mem(addr / mem.page_size);
         auto offs = addr & mem.page_addr_mask;
         if((offs + length) > mem.page_size) {
@@ -106,8 +110,11 @@ template <typename PLAT> struct memory_with_htif : public memory_elem {
     }
 
 protected:
-    using mem_type = util::sparse_array<uint8_t, 1ULL << 32>;
-    mem_type mem;
+    // Currently no type erasure for the sparse_array is available, so all memories
+    // have the largest possible size. Memory footprint should still be small as it
+    // a sparse array
+    using mem_type = util::sparse_array<uint8_t, arch::traits<PLAT>::max_mem_size>;
+    std::array<mem_type, arch::traits<PLAT>::mem_sizes.size()> memories;
     arch::priv_if<reg_t> hart_if;
 };
 } // namespace mem

From bd9125a4701eacdd9ec1048740066f30a4b8a547 Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Mon, 17 Nov 2025 08:38:03 +0100
Subject: [PATCH 26/77] corrects pmp behavior wrt space

---
 src/iss/mem/pmp.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/iss/mem/pmp.h b/src/iss/mem/pmp.h
index 0487424..2946666 100644
--- a/src/iss/mem/pmp.h
+++ b/src/iss/mem/pmp.h
@@ -117,7 +117,7 @@ template <typename PLAT> struct pmp : public memory_elem {
 
 private:
     iss::status read_mem(iss::access_type access, uint32_t space, uint64_t addr, unsigned length, uint8_t* data) {
-        if(!pmp_check(access, addr, length) && space != arch::traits<PLAT>::MEM && !is_debug(access)) {
+        if(likely(space == arch::traits<PLAT>::MEM) && !pmp_check(access, addr, length) && !is_debug(access)) {
             hart_if.fault_data = addr;
             if(is_debug(access))
                 throw trap_access(0, addr);
@@ -128,7 +128,7 @@ template <typename PLAT> struct pmp : public memory_elem {
     }
 
     iss::status write_mem(iss::access_type access, uint32_t space, uint64_t addr, unsigned length, uint8_t const* data) {
-        if(!pmp_check(access, addr, length) && space != arch::traits<PLAT>::MEM && !is_debug(access)) {
+        if(likely(space == arch::traits<PLAT>::MEM) && !pmp_check(access, addr, length) && !is_debug(access)) {
             hart_if.fault_data = addr;
             if(is_debug(access))
                 throw trap_access(0, addr);

From 2ffcd78f65e7640dcf2df3f43ef30431a3eebafb Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Tue, 18 Nov 2025 16:53:55 +0100
Subject: [PATCH 27/77] corrects memory to actually work now this was a huge
 oversight causing the memory to return random data when read

---
 src/iss/mem/memory_with_htif.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/iss/mem/memory_with_htif.h b/src/iss/mem/memory_with_htif.h
index ec57b08..d005b1b 100644
--- a/src/iss/mem/memory_with_htif.h
+++ b/src/iss/mem/memory_with_htif.h
@@ -69,7 +69,7 @@ template <typename PLAT> struct memory_with_htif : public memory_elem {
         // for(auto offs = 0U; offs < length; ++offs) {
         //     *(data + offs) = mem[(addr + offs) % mem.size()];
         // }
-        mem_type mem = memories[space];
+        mem_type& mem = memories[space];
         if(mem.is_allocated(addr)) {
             const auto& p = mem(addr / mem.page_size);
             auto offs = addr & mem.page_addr_mask;
@@ -90,7 +90,7 @@ template <typename PLAT> struct memory_with_htif : public memory_elem {
     }
 
     iss::status write_mem(iss::access_type access, uint32_t space, uint64_t addr, unsigned length, uint8_t const* data) {
-        mem_type mem = memories[space];
+        mem_type& mem = memories[space];
         auto& p = mem(addr / mem.page_size);
         auto offs = addr & mem.page_addr_mask;
         if((offs + length) > mem.page_size) {
@@ -114,7 +114,7 @@ template <typename PLAT> struct memory_with_htif : public memory_elem {
     // have the largest possible size. Memory footprint should still be small as it
     // a sparse array
     using mem_type = util::sparse_array<uint8_t, arch::traits<PLAT>::max_mem_size>;
-    std::array<mem_type, arch::traits<PLAT>::mem_sizes.size()> memories;
+    std::array<mem_type, arch::traits<PLAT>::mem_sizes.size()> memories{};
     arch::priv_if<reg_t> hart_if;
 };
 } // namespace mem

From 88614bef604de3cec80a0c9bcb0277ad365abb5f Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Fri, 21 Nov 2025 18:07:07 +0100
Subject: [PATCH 28/77] adds logginf for DMI access in core_complex

---
 gen_input/ISA             |  2 +-
 src/sysc/core_complex.cpp | 22 ++++++++++++++++++----
 2 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/gen_input/ISA b/gen_input/ISA
index 785b339..c59cf8b 160000
--- a/gen_input/ISA
+++ b/gen_input/ISA
@@ -1 +1 @@
-Subproject commit 785b339d8f124c608f4c7d5e985df98a72fb7459
+Subproject commit c59cf8b79ddba1d43720960b37db52f9cbd13c7b
diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index 441ff32..ffd5f8b 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -425,6 +425,13 @@ template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::read_mem(uint64_t
             ibus_inc += lut_entry.get_read_latency() / curr_clk;
         else
             dbus_inc += lut_entry.get_read_latency() / curr_clk;
+#ifndef NDEBUG
+        SCCTRACE(this->name()) << "[local time: " << quantum_keeper.get_local_time() << "]: finish dmi_read_mem(0x" << std::hex << addr
+                               << ") : 0x"
+                               << (length == 4   ? *(uint32_t*)data
+                                   : length == 2 ? *(uint16_t*)data
+                                                 : (unsigned)*data);
+#endif
         return true;
     } else {
         auto& sckt = is_fetch ? ibus : dbus;
@@ -479,6 +486,13 @@ template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::write_mem(uint64_t
         auto offset = addr - lut_entry.get_start_address();
         std::copy(data, data + length, lut_entry.get_dmi_ptr() + offset);
         dbus_inc += lut_entry.get_write_latency() / curr_clk;
+#ifndef NDEBUG
+        SCCTRACE(this->name()) << "[local time: " << quantum_keeper.get_local_time() << "]: finish dmi_write_mem(0x" << std::hex << addr
+                               << ") : 0x"
+                               << (length == 4   ? *(uint32_t*)data
+                                   : length == 2 ? *(uint16_t*)data
+                                                 : (unsigned)*data);
+#endif
         return true;
     } else {
         write_buf.resize(length);
@@ -500,10 +514,10 @@ template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::write_mem(uint64_t
             quantum_keeper.reset();
         else
             dbus_inc += (delay - quantum_keeper.get_local_time()) / curr_clk;
-        SCCTRACE() << "[local time: " << delay << "]: finish write_mem(0x" << std::hex << addr << ") : 0x"
-                   << (length == 4   ? *(uint32_t*)data
-                       : length == 2 ? *(uint16_t*)data
-                                     : (unsigned)*data);
+        SCCTRACE(this->name()) << "[local time: " << delay << "]: finish write_mem(0x" << std::hex << addr << ") : 0x"
+                               << (length == 4   ? *(uint32_t*)data
+                                   : length == 2 ? *(uint16_t*)data
+                                                 : (unsigned)*data);
         if(gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
             return false;
         }

From a0ff1294e35d2616291462001d7be693c5032380 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Fri, 21 Nov 2025 18:10:39 +0100
Subject: [PATCH 29/77] fixes core2sc adapter to comply to changed read/write
 if

---
 src/sysc/core2sc_adapter.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/sysc/core2sc_adapter.h b/src/sysc/core2sc_adapter.h
index d48ddf3..71b17eb 100644
--- a/src/sysc/core2sc_adapter.h
+++ b/src/sysc/core2sc_adapter.h
@@ -147,7 +147,7 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
                                    .wr_mem{util::delegate<iss::mem::wr_mem_func_sig>::from<this_class, &this_class::write_mem>(this)}};
     }
 
-    iss::status read_mem(iss::access_type access, uint64_t addr, unsigned length, uint8_t* data) {
+    iss::status read_mem(iss::access_type access, uint32_t space, uint64_t addr, unsigned length, uint8_t* data) {
         if(access && iss::access_type::DEBUG)
             return owner->read_mem_dbg(addr, length, data) ? iss::Ok : iss::Err;
         else {
@@ -155,7 +155,7 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
         }
     }
 
-    iss::status write_mem(iss::access_type access, uint64_t addr, unsigned length, uint8_t const* data) {
+    iss::status write_mem(iss::access_type access, uint32_t space, uint64_t addr, unsigned length, uint8_t const* data) {
         if(access && iss::access_type::DEBUG)
             return owner->write_mem_dbg(addr, length, data) ? iss::Ok : iss::Err;
         if(addr == this->tohost) {

From 98236705f95979eb4436d2388a7ccf5ba6f5d05b Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Sat, 22 Nov 2025 16:38:23 +0100
Subject: [PATCH 30/77] update dbt-rise-core and adjusts components accordingly
 These changes address memory interactions: VMs now only use LOGICAL addresses
 addr_t is used everywhere mem components are aware of the address types and
 react accordingly memory_with_htif now clearly implements von neumann
 architecture

---
 CMakeLists.txt                          |  2 +-
 src/iss/arch/riscv_hart_common.h        | 12 +++---
 src/iss/arch/riscv_hart_m_p.h           | 36 +++++++++--------
 src/iss/arch/riscv_hart_msu_vp.h        | 31 +++++++++------
 src/iss/arch/riscv_hart_mu_p.h          | 33 +++++++++------
 src/iss/debugger/riscv_target_adapter.h | 10 ++---
 src/iss/mem/memory_if.h                 |  4 +-
 src/iss/mem/memory_with_htif.h          | 44 ++++++++++----------
 src/iss/mem/mmu.h                       | 53 +++++++++++++++----------
 src/iss/mem/pmp.h                       | 24 ++++++-----
 src/iss/semihosting/semihosting.cpp     | 10 ++---
 src/main.cpp                            |  4 +-
 src/vm/vector_functions.h               |  8 ++--
 13 files changed, 150 insertions(+), 121 deletions(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index e5fc71e..0d242f7 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -20,7 +20,7 @@ if(NOT TARGET dbt-rise-core)
         dbt_rise_core_git
         GIT_REPOSITORY "https://github.com/Minres/DBT-RISE-Core.git"
         #GIT_TAG         "origin/develop"
-        GIT_TAG 6f2d15ec
+        GIT_TAG 874d3241
         GIT_SHALLOW OFF
         UPDATE_DISCONNECTED NOT ${UPDATE_EXTERNAL_PROJECT} # When enabled, this option causes the update step to be skipped.
     )
diff --git a/src/iss/arch/riscv_hart_common.h b/src/iss/arch/riscv_hart_common.h
index 621f081..b480cfc 100644
--- a/src/iss/arch/riscv_hart_common.h
+++ b/src/iss/arch/riscv_hart_common.h
@@ -474,8 +474,9 @@ template <typename BASE = logging::disass> struct riscv_hart_common : public BAS
                 const auto seg_data = pseg->get_data();
                 const auto type = pseg->get_type();
                 if(type == ELFIO::PT_LOAD && fsize > 0) {
-                    auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM,
-                                           pseg->get_physical_address(), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
+                    auto res = this->write(
+                        {iss::address_type::LOGICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::IMEM, pseg->get_physical_address()},
+                        fsize, reinterpret_cast<const uint8_t* const>(seg_data));
                     if(res != iss::Ok)
                         ILOG(isslogger, logging::ERR,
                              fmt::format("problem writing {} bytes to 0x{:x}", fsize, pseg->get_physical_address()));
@@ -518,7 +519,7 @@ template <typename BASE = logging::disass> struct riscv_hart_common : public BAS
         uint64_t buf_ptr = loaded_payload[2];
         uint64_t len = loaded_payload[3];
         std::vector<char> buf(len);
-        if(aif->read(address_type::PHYSICAL, access_type::DEBUG_READ, mem_type, buf_ptr, len, reinterpret_cast<uint8_t*>(buf.data()))) {
+        if(aif->read({address_type::LOGICAL, access_type::DEBUG_READ, mem_type, buf_ptr}, len, reinterpret_cast<uint8_t*>(buf.data()))) {
             ILOG(isslogger, logging::ERR, "SYS_WRITE buffer read went wrong");
             return iss::Err;
         }
@@ -534,7 +535,7 @@ template <typename BASE = logging::disass> struct riscv_hart_common : public BAS
         // Not sure what the correct return value should be
         uint8_t ret_val = 1;
         if(fromhost != std::numeric_limits<uint64_t>::max())
-            if(aif->write(address_type::PHYSICAL, access_type::DEBUG_WRITE, mem_type, fromhost, 1, &ret_val)) {
+            if(aif->write({address_type::LOGICAL, access_type::DEBUG_WRITE, mem_type, fromhost}, 1, &ret_val) != iss::Ok) {
                 ILOG(isslogger, logging::ERR, "Fromhost write went wrong");
                 return iss::Err;
             }
@@ -885,6 +886,7 @@ template <typename BASE = logging::disass> struct riscv_hart_common : public BAS
     iss::status execute_htif(uint8_t const* data, unsigned length) {
         reg_t cur_data{0};
         memcpy(&cur_data, data, length);
+        // according to https://github.com/riscv-software-src/riscv-isa-sim/issues/364#issuecomment-607657754:
         // Extract Device (bits 63:56)
         uint8_t device = traits<BASE>::XLEN == 32 ? 0 : (cur_data >> 56) & 0xFF;
         // Extract Command (bits 55:48)
@@ -904,7 +906,7 @@ template <typename BASE = logging::disass> struct riscv_hart_common : public BAS
             return iss::Ok;
         } else if(device == 0 && command == 0) {
             std::array<uint64_t, 8> loaded_payload;
-            if(memory.rd_mem(access_type::DEBUG_READ, traits<BASE>::MEM, payload_data, 8 * sizeof(uint64_t),
+            if(memory.rd_mem({address_type::LOGICAL, access_type::DEBUG_READ, traits<BASE>::MEM, payload_data}, 8 * sizeof(uint64_t),
                              reinterpret_cast<uint8_t*>(loaded_payload.data())) == iss::Err)
                 ILOG(isslogger, logging::ERR, "Syscall read went wrong");
             uint64_t syscall_num = loaded_payload.at(0);
diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h
index 4aa852f..2c09e7b 100644
--- a/src/iss/arch/riscv_hart_m_p.h
+++ b/src/iss/arch/riscv_hart_m_p.h
@@ -112,10 +112,8 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_m_p : pub
 
     void reset(uint64_t address) override;
 
-    iss::status read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length,
-                     uint8_t* const data);
-    iss::status write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length,
-                      const uint8_t* const data);
+    iss::status read(const addr_t& addr, const unsigned length, uint8_t* const data);
+    iss::status write(const addr_t& addr, const unsigned length, const uint8_t* const data);
 
     uint64_t enter_trap(uint64_t flags) override { return riscv_hart_m_p::enter_trap(flags, this->fault_data, this->fault_data); }
     uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
@@ -124,9 +122,6 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_m_p : pub
     void set_csr(unsigned addr, reg_t val) { this->csr[addr & this->csr.page_addr_mask] = val; }
 
 protected:
-    using mem_read_f = iss::status(iss::phys_addr_t addr, unsigned, uint8_t* const);
-    using mem_write_f = iss::status(iss::phys_addr_t addr, unsigned, uint8_t const* const);
-
     hart_state<reg_t> state;
 
     std::unordered_map<uint64_t, uint8_t> atomic_reservation;
@@ -161,8 +156,12 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p()
 }
 
 template <typename BASE, features_e FEAT>
-iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr,
-                                             const unsigned length, uint8_t* const data) {
+iss::status riscv_hart_m_p<BASE, FEAT>::read(const addr_t& a, const unsigned length, uint8_t* const data) {
+    auto& addr = a.val;
+    auto& space = a.space;
+    auto& access = a.access;
+    auto& type = a.type;
+
 #ifndef NDEBUG
     if(access && iss::access_type::DEBUG) {
         ILOG(isslogger, logging::TRACEALL, fmt::format("debug read of {} bytes @addr 0x{:x}", length, addr));
@@ -189,7 +188,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
                     this->fault_data = addr;
                     return iss::Err;
                 }
-                auto res = this->memory.rd_mem(access, space, addr, length, data);
+                auto res = this->memory.rd_mem({address_type::PHYSICAL, a.access, a.space, a.val}, length, data);
                 if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
                     this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_LOAD_ACCESS << 16;
                     this->fault_data = addr;
@@ -245,8 +244,11 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
 }
 
 template <typename BASE, features_e FEAT>
-iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr,
-                                              const unsigned length, const uint8_t* const data) {
+iss::status riscv_hart_m_p<BASE, FEAT>::write(const addr_t& addr_, const unsigned length, const uint8_t* const data) {
+    auto& addr = addr_.val;
+    auto& space = addr_.space;
+    auto& access = addr_.access;
+    auto& type = addr_.type;
 #ifndef NDEBUG
     const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
     switch(length) {
@@ -287,7 +289,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
                     this->fault_data = addr;
                     return iss::Err;
                 }
-                auto res = this->memory.wr_mem(access, space, addr, length, data);
+                auto res = this->memory.wr_mem({address_type::PHYSICAL, addr_.access, addr_.space, addr_.val}, length, data);
                 if(unlikely(res != iss::Ok && !is_debug(access))) {
                     this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_STORE_ACCESS << 16;
                     this->fault_data = addr;
@@ -431,9 +433,9 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
                 // Check for semihosting call
                 std::array<uint8_t, 8> data;
                 // check for SLLI_X0_X0_0X1F and SRAI_X0_X0_0X07
-                this->memory.rd_mem(iss::access_type::DEBUG_READ, traits<BASE>::IMEM, addr - 4, 4, data.data());
+                this->memory.rd_mem({address_type::PHYSICAL, access_type::DEBUG_READ, traits<BASE>::IMEM, addr - 4}, 4, data.data());
                 addr += 8;
-                this->memory.rd_mem(iss::access_type::DEBUG_READ, traits<BASE>::IMEM, addr - 4, 4, data.data() + 4);
+                this->memory.rd_mem({address_type::PHYSICAL, access_type::DEBUG_READ, traits<BASE>::IMEM, addr - 4}, 4, data.data() + 4);
 
                 const std::array<uint8_t, 8> ref_data = {0x13, 0x10, 0xf0, 0x01, 0x13, 0x50, 0x70, 0x40};
                 if(data == ref_data) {
@@ -483,8 +485,8 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
     // calculate adds// set NEXT_PC to trap addressess to jump to based on MODE
     if(trap_id != 0 && (xtvec & 0x3UL) == 3UL) {
         reg_t data;
-        auto ret = this->memory.rd_mem(access_type::DEBUG_READ, traits<BASE>::MEM, this->csr[arch::mtvt], sizeof(reg_t),
-                                       reinterpret_cast<uint8_t*>(&data));
+        auto ret = this->memory.rd_mem({address_type::PHYSICAL, access_type::DEBUG_READ, traits<BASE>::MEM, this->csr[arch::mtvt]},
+                                       sizeof(reg_t), reinterpret_cast<uint8_t*>(&data));
         if(ret == iss::Err)
             return this->reg.PC;
         this->reg.NEXT_PC = data;
diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h
index 25cfe8e..5371c91 100644
--- a/src/iss/arch/riscv_hart_msu_vp.h
+++ b/src/iss/arch/riscv_hart_msu_vp.h
@@ -138,10 +138,8 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_msu_vp :
 
     void reset(uint64_t address) override;
 
-    iss::status read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length,
-                     uint8_t* const data);
-    iss::status write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length,
-                      const uint8_t* const data);
+    iss::status read(const addr_t& addr, const unsigned length, uint8_t* const data);
+    iss::status write(const addr_t& addr, const unsigned length, const uint8_t* const data);
 
     uint64_t enter_trap(uint64_t flags) override { return riscv_hart_msu_vp::enter_trap(flags, this->fault_data, this->fault_data); }
     uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
@@ -238,8 +236,11 @@ riscv_hart_msu_vp<BASE, FEAT>::riscv_hart_msu_vp()
 }
 
 template <typename BASE, features_e FEAT>
-iss::status riscv_hart_msu_vp<BASE, FEAT>::read(const address_type type, const access_type access, const uint32_t space,
-                                                const uint64_t addr, const unsigned length, uint8_t* const data) {
+iss::status riscv_hart_msu_vp<BASE, FEAT>::read(const addr_t& addr_, const unsigned length, uint8_t* const data) {
+    auto& addr = addr_.val;
+    auto& space = addr_.space;
+    auto& access = addr_.access;
+    auto& type = addr_.type;
 #ifndef NDEBUG
     if(access && iss::access_type::DEBUG) {
         ILOG(isslogger, logging::TRACEALL, fmt::format("debug read of {} bytes @addr 0x{:x}", length, addr));
@@ -266,7 +267,7 @@ iss::status riscv_hart_msu_vp<BASE, FEAT>::read(const address_type type, const a
                     this->fault_data = addr;
                     return iss::Err;
                 }
-                auto res = this->memory.rd_mem(access, space, addr, length, data);
+                auto res = this->memory.rd_mem({address_type::VIRTUAL, addr_.access, addr_.space, addr_.val}, length, data);
                 if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
                     this->reg.trap_state = (1UL << 31) | (traits<BASE>::RV_CAUSE_LOAD_ACCESS << 16);
                     this->fault_data = addr;
@@ -325,8 +326,11 @@ iss::status riscv_hart_msu_vp<BASE, FEAT>::read(const address_type type, const a
 }
 
 template <typename BASE, features_e FEAT>
-iss::status riscv_hart_msu_vp<BASE, FEAT>::write(const address_type type, const access_type access, const uint32_t space,
-                                                 const uint64_t addr, const unsigned length, const uint8_t* const data) {
+iss::status riscv_hart_msu_vp<BASE, FEAT>::write(const addr_t& addr_, const unsigned length, const uint8_t* const data) {
+    auto& addr = addr_.val;
+    auto& space = addr_.space;
+    auto& access = addr_.access;
+    auto& type = addr_.type;
 #ifndef NDEBUG
     const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
     switch(length) {
@@ -367,7 +371,7 @@ iss::status riscv_hart_msu_vp<BASE, FEAT>::write(const address_type type, const
                     this->fault_data = addr;
                     return iss::Err;
                 }
-                auto res = this->memory.wr_mem(access, space, addr, length, data);
+                auto res = this->memory.wr_mem({address_type::VIRTUAL, addr_.access, addr_.space, addr_.val}, length, data);
                 if(unlikely(res != iss::Ok && !is_debug(access))) {
                     this->reg.trap_state = (1UL << 31) | (traits<BASE>::RV_CAUSE_STORE_ACCESS << 16);
                     this->fault_data = addr;
@@ -587,9 +591,9 @@ uint64_t riscv_hart_msu_vp<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr
                 // Check for semihosting call
                 std::array<uint8_t, 8> data;
                 // check for SLLI_X0_X0_0X1F and SRAI_X0_X0_0X07
-                this->memory.rd_mem(iss::access_type::DEBUG_READ, traits<BASE>::IMEM, addr - 4, 4, data.data());
+                this->memory.rd_mem({address_type::VIRTUAL, access_type::DEBUG_READ, traits<BASE>::IMEM, addr - 4}, 4, data.data());
                 addr += 8;
-                this->memory.rd_mem(iss::access_type::DEBUG_READ, traits<BASE>::IMEM, addr - 4, 4, data.data() + 4);
+                this->memory.rd_mem({address_type::VIRTUAL, access_type::DEBUG_READ, traits<BASE>::IMEM, addr - 4}, 4, data.data() + 4);
 
                 const std::array<uint8_t, 8> ref_data = {0x13, 0x10, 0xf0, 0x01, 0x13, 0x50, 0x70, 0x40};
                 if(data == ref_data) {
@@ -663,7 +667,8 @@ uint64_t riscv_hart_msu_vp<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr
     if(trap_id != 0) {
         if((xtvec & 0x3UL) == 3UL) {
             reg_t data;
-            auto ret = read(address_type::LOGICAL, access_type::READ, 0, this->csr[mtvt], sizeof(reg_t), reinterpret_cast<uint8_t*>(&data));
+            auto ret = read({address_type::VIRTUAL, access_type::READ, traits<BASE>::MEM, this->csr[mtvt]}, sizeof(reg_t),
+                            reinterpret_cast<uint8_t*>(&data));
             if(ret == iss::Err)
                 return this->reg.PC;
             this->reg.NEXT_PC = data;
diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h
index 182ca4b..939d26b 100644
--- a/src/iss/arch/riscv_hart_mu_p.h
+++ b/src/iss/arch/riscv_hart_mu_p.h
@@ -132,10 +132,8 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_mu_p : pu
 
     void reset(uint64_t address) override;
 
-    iss::status read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length,
-                     uint8_t* const data);
-    iss::status write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length,
-                      const uint8_t* const data);
+    iss::status read(const addr_t& addr, const unsigned length, uint8_t* const data);
+    iss::status write(const addr_t& addr, const unsigned length, const uint8_t* const data);
 
     uint64_t enter_trap(uint64_t flags) override { return riscv_hart_mu_p::enter_trap(flags, this->fault_data, this->fault_data); }
     uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
@@ -205,8 +203,11 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
 }
 
 template <typename BASE, features_e FEAT>
-iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr,
-                                              const unsigned length, uint8_t* const data) {
+iss::status riscv_hart_mu_p<BASE, FEAT>::read(const addr_t& addr_, const unsigned length, uint8_t* const data) {
+    auto& addr = addr_.val;
+    auto& space = addr_.space;
+    auto& access = addr_.access;
+    auto& type = addr_.type;
 #ifndef NDEBUG
     if(access && iss::access_type::DEBUG) {
         ILOG(isslogger, logging::TRACEALL, fmt::format("debug read of {} bytes @addr 0x{:x}", length, addr));
@@ -233,7 +234,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
                     this->fault_data = addr;
                     return iss::Err;
                 }
-                auto res = this->memory.rd_mem(access, space, addr, length, data);
+                auto res = this->memory.rd_mem({address_type::PHYSICAL, addr_.access, addr_.space, addr_.val}, length, data);
                 if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
                     this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_LOAD_ACCESS << 16;
                     this->fault_data = addr;
@@ -289,8 +290,11 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
 }
 
 template <typename BASE, features_e FEAT>
-iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr,
-                                               const unsigned length, const uint8_t* const data) {
+iss::status riscv_hart_mu_p<BASE, FEAT>::write(const addr_t& addr_, const unsigned length, const uint8_t* const data) {
+    auto& addr = addr_.val;
+    auto& space = addr_.space;
+    auto& access = addr_.access;
+    auto& type = addr_.type;
 #ifndef NDEBUG
     const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
     switch(length) {
@@ -331,7 +335,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
                     this->fault_data = addr;
                     return iss::Err;
                 }
-                auto res = this->memory.wr_mem(access, space, addr, length, data);
+                auto res = this->memory.wr_mem({address_type::PHYSICAL, addr_.access, addr_.space, addr_.val}, length, data);
                 if(unlikely(res != iss::Ok && !is_debug(access))) {
                     this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_STORE_ACCESS << 16;
                     this->fault_data = addr;
@@ -478,9 +482,11 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
                 // Check for semihosting call
                 std::array<uint8_t, 8> data;
                 // check for SLLI_X0_X0_0X1F and SRAI_X0_X0_0X07
-                this->memory.rd_mem(iss::access_type::DEBUG_READ, traits<BASE>::IMEM, addr - 4, 4, data.data());
+                this->memory.rd_mem({iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, traits<BASE>::IMEM, addr - 4}, 4,
+                                    data.data());
                 addr += 8;
-                this->memory.rd_mem(iss::access_type::DEBUG_READ, traits<BASE>::IMEM, addr - 4, 4, data.data() + 4);
+                this->memory.rd_mem({iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, traits<BASE>::IMEM, addr - 4}, 4,
+                                    data.data() + 4);
 
                 const std::array<uint8_t, 8> ref_data = {0x13, 0x10, 0xf0, 0x01, 0x13, 0x50, 0x70, 0x40};
                 if(data == ref_data) {
@@ -544,7 +550,8 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
     if(trap_id != 0) {
         if((xtvec & 0x3UL) == 3UL) {
             reg_t data;
-            auto ret = read(address_type::LOGICAL, access_type::READ, 0, this->csr[mtvt], sizeof(reg_t), reinterpret_cast<uint8_t*>(&data));
+            auto ret = read({address_type::PHYSICAL, access_type::READ, traits<BASE>::MEM, this->csr[mtvt]}, sizeof(reg_t),
+                            reinterpret_cast<uint8_t*>(&data));
             if(ret == iss::Err)
                 return this->reg.PC;
             this->reg.NEXT_PC = data;
diff --git a/src/iss/debugger/riscv_target_adapter.h b/src/iss/debugger/riscv_target_adapter.h
index 5b8e166..be2b75b 100644
--- a/src/iss/debugger/riscv_target_adapter.h
+++ b/src/iss/debugger/riscv_target_adapter.h
@@ -267,13 +267,13 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::write_single_registe
 }
 
 template <typename ARCH> status riscv_target_adapter<ARCH>::read_mem(uint64_t addr, std::vector<uint8_t>& data) {
-    auto a = map_addr({iss::access_type::DEBUG_READ, iss::address_type::VIRTUAL, 0, addr});
+    auto a = map_addr({iss::address_type::VIRTUAL, iss::access_type::DEBUG_READ, 0, addr});
     auto f = [&]() -> status { return core->read(a, data.size(), data.data()); };
     return srv->execute_syncronized(f);
 }
 
 template <typename ARCH> status riscv_target_adapter<ARCH>::write_mem(uint64_t addr, const std::vector<uint8_t>& data) {
-    auto a = map_addr({iss::access_type::DEBUG_WRITE, iss::address_type::VIRTUAL, 0, addr});
+    auto a = map_addr({iss::address_type::VIRTUAL, iss::access_type::DEBUG_WRITE, 0, addr});
     auto f = [&]() -> status { return core->write(a, data.size(), data.data()); };
     return srv->execute_syncronized(f);
 }
@@ -322,8 +322,8 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(break_type
         return Err;
     case SW_EXEC:
     case HW_EXEC: {
-        auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
-        auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
+        auto saddr = map_addr({iss::address_type::PHYSICAL, iss::access_type::FETCH, 0, addr});
+        auto eaddr = map_addr({iss::address_type::PHYSICAL, iss::access_type::FETCH, 0, addr + length});
         target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
         CPPLOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex << saddr.val
                       << std::dec;
@@ -339,7 +339,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(break_t
         return Err;
     case SW_EXEC:
     case HW_EXEC: {
-        auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
+        auto saddr = map_addr({iss::address_type::PHYSICAL, iss::access_type::FETCH, 0, addr});
         unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
         if(handle) {
             CPPLOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val << std::dec;
diff --git a/src/iss/mem/memory_if.h b/src/iss/mem/memory_if.h
index e459a87..48cfea2 100644
--- a/src/iss/mem/memory_if.h
+++ b/src/iss/mem/memory_if.h
@@ -46,8 +46,8 @@
 namespace iss {
 namespace mem {
 
-using rd_mem_func_sig = iss::status(iss::access_type, uint32_t space, uint64_t addr, unsigned length, uint8_t* data);
-using wr_mem_func_sig = iss::status(iss::access_type, uint32_t space, uint64_t addr, unsigned length, uint8_t const* data);
+using rd_mem_func_sig = iss::status(const addr_t& addr, unsigned length, uint8_t* data);
+using wr_mem_func_sig = iss::status(const addr_t& addr, unsigned length, uint8_t const* data);
 
 struct memory_if {
     util::delegate<rd_mem_func_sig> rd_mem;
diff --git a/src/iss/mem/memory_with_htif.h b/src/iss/mem/memory_with_htif.h
index d005b1b..b0e9c2a 100644
--- a/src/iss/mem/memory_with_htif.h
+++ b/src/iss/mem/memory_with_htif.h
@@ -46,14 +46,14 @@
 
 namespace iss {
 namespace mem {
-template <typename PLAT> struct memory_with_htif : public memory_elem {
-    using this_class = memory_with_htif<PLAT>;
+template <typename PLAT> struct neumann_memory_with_htif : public memory_elem {
+    using this_class = neumann_memory_with_htif<PLAT>;
     using reg_t = typename PLAT::reg_t;
 
-    memory_with_htif(arch::priv_if<reg_t> hart_if)
+    neumann_memory_with_htif(arch::priv_if<reg_t> hart_if)
     : hart_if(hart_if) {}
 
-    ~memory_with_htif() = default;
+    ~neumann_memory_with_htif() = default;
 
     memory_if get_mem_if() override {
         return memory_if{.rd_mem{util::delegate<rd_mem_func_sig>::from<this_class, &this_class::read_mem>(this)},
@@ -65,18 +65,17 @@ template <typename PLAT> struct memory_with_htif : public memory_elem {
     }
 
 private:
-    iss::status read_mem(iss::access_type access, uint32_t space, uint64_t addr, unsigned length, uint8_t* data) {
-        // for(auto offs = 0U; offs < length; ++offs) {
-        //     *(data + offs) = mem[(addr + offs) % mem.size()];
-        // }
-        mem_type& mem = memories[space];
-        if(mem.is_allocated(addr)) {
-            const auto& p = mem(addr / mem.page_size);
-            auto offs = addr & mem.page_addr_mask;
+    iss::status read_mem(const iss::addr_t& addr, unsigned length, uint8_t* data) {
+        assert((addr.type == iss::address_type::PHYSICAL || is_debug(addr.access)) &&
+               "Only physical addresses are expected in memory_with_htif");
+        mem_type& mem = addr.space == iss::arch::traits<PLAT>::IMEM ? memories[iss::arch::traits<PLAT>::MEM] : memories[addr.space];
+        if(mem.is_allocated(addr.val)) {
+            const auto& p = mem(addr.val / mem.page_size);
+            auto offs = addr.val & mem.page_addr_mask;
             if((offs + length) > mem.page_size) {
                 auto first_part = mem.page_size - offs;
                 std::copy(p.data() + offs, p.data() + offs + first_part, data);
-                const auto& p2 = mem((addr / mem.page_size) + 1);
+                const auto& p2 = mem((addr.val / mem.page_size) + 1);
                 std::copy(p2.data(), p2.data() + length - first_part, data + first_part);
             } else {
                 std::copy(p.data() + offs, p.data() + offs + length, data);
@@ -89,21 +88,21 @@ template <typename PLAT> struct memory_with_htif : public memory_elem {
         return iss::Ok;
     }
 
-    iss::status write_mem(iss::access_type access, uint32_t space, uint64_t addr, unsigned length, uint8_t const* data) {
-        mem_type& mem = memories[space];
-        auto& p = mem(addr / mem.page_size);
-        auto offs = addr & mem.page_addr_mask;
+    iss::status write_mem(const iss::addr_t& addr, unsigned length, uint8_t const* data) {
+        assert((addr.type == iss::address_type::PHYSICAL || is_debug(addr.access)) &&
+               "Only physical addresses are expected in memory_with_htif");
+        mem_type& mem = addr.space == iss::arch::traits<PLAT>::IMEM ? memories[iss::arch::traits<PLAT>::MEM] : memories[addr.space];
+        auto& p = mem(addr.val / mem.page_size);
+        auto offs = addr.val & mem.page_addr_mask;
         if((offs + length) > mem.page_size) {
             auto first_part = mem.page_size - offs;
             std::copy(data, data + first_part, p.data() + offs);
-            auto& p2 = mem((addr / mem.page_size) + 1);
+            auto& p2 = mem((addr.val / mem.page_size) + 1);
             std::copy(data + first_part, data + length, p2.data());
         } else {
             std::copy(data, data + length, p.data() + offs);
         }
-        // this->tohost handling in case of riscv-test
-        // according to https://github.com/riscv-software-src/riscv-isa-sim/issues/364#issuecomment-607657754:
-        if(access && iss::access_type::FUNC && addr == hart_if.tohost) {
+        if(addr.val == hart_if.tohost) {
             return hart_if.exec_htif(data, length);
         }
         return iss::Ok;
@@ -114,7 +113,8 @@ template <typename PLAT> struct memory_with_htif : public memory_elem {
     // have the largest possible size. Memory footprint should still be small as it
     // a sparse array
     using mem_type = util::sparse_array<uint8_t, arch::traits<PLAT>::max_mem_size>;
-    std::array<mem_type, arch::traits<PLAT>::mem_sizes.size()> memories{};
+    // We need one fewer memory as the IMEM maps to MEM in von Neumann architecture
+    std::array<mem_type, arch::traits<PLAT>::mem_sizes.size() - 1> memories{};
     arch::priv_if<reg_t> hart_if;
 };
 } // namespace mem
diff --git a/src/iss/mem/mmu.h b/src/iss/mem/mmu.h
index 9889814..7232cbd 100644
--- a/src/iss/mem/mmu.h
+++ b/src/iss/mem/mmu.h
@@ -104,35 +104,45 @@ template <typename PLAT> struct mmu : public memory_elem {
         return priv;
     }
 
-    bool needs_translation(iss::access_type type, uint32_t space) {
-        return likely(space == arch::traits<PLAT>::MEM) && (effective_priv(type) == arch::PRIV_U || effective_priv(type) == arch::PRIV_S) &&
-               vm_setting.levels;
+    bool needs_translation(const addr_t& addr) {
+        return likely(addr.space == arch::traits<PLAT>::MEM) &&
+               (effective_priv(addr.access) == arch::PRIV_U || effective_priv(addr.access) == arch::PRIV_S) && vm_setting.levels;
     }
 
-    iss::status read_mem(iss::access_type access, uint32_t space, uint64_t addr, unsigned length, uint8_t* data) {
-        if(unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK) &&
-                    needs_translation(access, space))) { // we may cross a page boundary
-            auto split_addr = (addr + length) & ~PGMASK;
-            auto len1 = split_addr - addr;
-            auto res = down_stream_mem.rd_mem(access, space, virt2phys(access, addr), len1, data);
+    iss::status read_mem(const addr_t& addr, unsigned length, uint8_t* data) {
+        assert((addr.type == iss::address_type::VIRTUAL || is_debug(addr.access)) && "Only virtual addresses are expected in mmu");
+        if(unlikely((addr.val & ~PGMASK) != ((addr.val + length - 1) & ~PGMASK) &&
+                    needs_translation(addr))) { // we may cross a page boundary
+            auto split_addr = (addr.val + length) & ~PGMASK;
+            auto len1 = split_addr - addr.val;
+            auto res = down_stream_mem.rd_mem({iss::address_type::PHYSICAL, addr.access, addr.space, virt2phys(addr.access, addr.val)},
+                                              len1, data);
             if(res == iss::Ok)
-                res = down_stream_mem.rd_mem(access, space, virt2phys(access, split_addr), length - len1, data + len1);
+                res = down_stream_mem.rd_mem({iss::address_type::PHYSICAL, addr.access, addr.space, virt2phys(addr.access, addr.val)},
+                                             length - len1, data + len1);
             return res;
         }
-        return down_stream_mem.rd_mem(access, space, needs_translation(access, space) ? virt2phys(access, addr) : addr, length, data);
+        return down_stream_mem.rd_mem(
+            {iss::address_type::PHYSICAL, addr.access, addr.space, needs_translation(addr) ? virt2phys(addr.access, addr.val) : addr.val},
+            length, data);
     }
 
-    iss::status write_mem(iss::access_type access, uint32_t space, uint64_t addr, unsigned length, uint8_t const* data) {
-        if(unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK) &&
-                    needs_translation(access, space))) { // we may cross a page boundary
-            auto split_addr = (addr + length) & ~PGMASK;
-            auto len1 = split_addr - addr;
-            auto res = down_stream_mem.wr_mem(access, space, virt2phys(access, addr), len1, data);
+    iss::status write_mem(const addr_t& addr, unsigned length, uint8_t const* data) {
+        assert((addr.type == iss::address_type::VIRTUAL || is_debug(addr.access)) && "Only virtual addresses are expected in mmu");
+        if(unlikely((addr.val & ~PGMASK) != ((addr.val + length - 1) & ~PGMASK) &&
+                    needs_translation(addr))) { // we may cross a page boundary
+            auto split_addr = (addr.val + length) & ~PGMASK;
+            auto len1 = split_addr - addr.val;
+            auto res = down_stream_mem.wr_mem({iss::address_type::PHYSICAL, addr.access, addr.space, virt2phys(addr.access, addr.val)},
+                                              len1, data);
             if(res == iss::Ok)
-                res = down_stream_mem.wr_mem(access, space, virt2phys(access, split_addr), length - len1, data + len1);
+                res = down_stream_mem.wr_mem({iss::address_type::PHYSICAL, addr.access, addr.space, virt2phys(addr.access, split_addr)},
+                                             length - len1, data + len1);
             return res;
         }
-        return down_stream_mem.wr_mem(access, space, needs_translation(access, space) ? virt2phys(access, addr) : addr, length, data);
+        return down_stream_mem.wr_mem(
+            {iss::address_type::PHYSICAL, addr.access, addr.space, needs_translation(addr) ? virt2phys(addr.access, addr.val) : addr.val},
+            length, data);
     }
 
     iss::status read_plain(unsigned addr, reg_t& val) {
@@ -241,8 +251,9 @@ template <typename PLAT> uint64_t mmu<PLAT>::virt2phys(iss::access_type access,
         for(int i = vm_setting.levels - 1; i >= 0; i--) {
             const int ptshift = i * vm_setting.idxbits;
             const reg_t idx = (addr >> (PGSHIFT + ptshift)) & ((1 << vm_setting.idxbits) - 1);
-            const iss::status res = down_stream_mem.rd_mem(iss::access_type::READ, arch::traits<PLAT>::MEM, base + idx * vm_setting.ptesize,
-                                                           vm_setting.ptesize, (uint8_t*)&pte);
+            const iss::status res = down_stream_mem.rd_mem(
+                {iss::address_type::PHYSICAL, iss::access_type::READ, arch::traits<PLAT>::MEM, base + idx * vm_setting.ptesize},
+                vm_setting.ptesize, (uint8_t*)&pte);
             if(res != iss::status::Ok) {
                 CPPLOG(DEBUG) << "Access fault when trying to read next pte";
                 switch(type) {
diff --git a/src/iss/mem/pmp.h b/src/iss/mem/pmp.h
index 2946666..bc3a17c 100644
--- a/src/iss/mem/pmp.h
+++ b/src/iss/mem/pmp.h
@@ -116,26 +116,28 @@ template <typename PLAT> struct pmp : public memory_elem {
     void set_next(memory_if mem) override { down_stream_mem = mem; }
 
 private:
-    iss::status read_mem(iss::access_type access, uint32_t space, uint64_t addr, unsigned length, uint8_t* data) {
-        if(likely(space == arch::traits<PLAT>::MEM) && !pmp_check(access, addr, length) && !is_debug(access)) {
+    iss::status read_mem(const addr_t& addr, unsigned length, uint8_t* data) {
+        assert((addr.type == iss::address_type::PHYSICAL || is_debug(addr.access)) && "Only physical addresses are expected in pmp");
+        if(likely(addr.space == arch::traits<PLAT>::MEM) && !pmp_check(addr.access, addr.val, length) && !is_debug(addr.access)) {
             hart_if.fault_data = addr;
-            if(is_debug(access))
-                throw trap_access(0, addr);
-            hart_if.reg.trap_state = (1UL << 31) | ((access == access_type::FETCH ? 1 : 5) << 16); // issue trap 1
+            if(is_debug(addr.access))
+                throw trap_access(0, addr.val);
+            hart_if.reg.trap_state = (1UL << 31) | ((addr.access == access_type::FETCH ? 1 : 5) << 16); // issue trap 1
             return iss::Err;
         }
-        return down_stream_mem.rd_mem(access, space, addr, length, data);
+        return down_stream_mem.rd_mem(addr, length, data);
     }
 
-    iss::status write_mem(iss::access_type access, uint32_t space, uint64_t addr, unsigned length, uint8_t const* data) {
-        if(likely(space == arch::traits<PLAT>::MEM) && !pmp_check(access, addr, length) && !is_debug(access)) {
+    iss::status write_mem(const addr_t& addr, unsigned length, uint8_t const* data) {
+        assert((addr.type == iss::address_type::PHYSICAL || is_debug(addr.access)) && "Only physical addresses are expected in pmp");
+        if(likely(addr.space == arch::traits<PLAT>::MEM) && !pmp_check(addr.access, addr.val, length) && !is_debug(addr.access)) {
             hart_if.fault_data = addr;
-            if(is_debug(access))
-                throw trap_access(0, addr);
+            if(is_debug(addr.access))
+                throw trap_access(0, addr.val);
             hart_if.reg.trap_state = (1UL << 31) | (7 << 16); // issue trap 1
             return iss::Err;
         }
-        return down_stream_mem.wr_mem(access, space, addr, length, data);
+        return down_stream_mem.wr_mem(addr, length, data);
     }
 
     iss::status read_plain(unsigned addr, reg_t& val) {
diff --git a/src/iss/semihosting/semihosting.cpp b/src/iss/semihosting/semihosting.cpp
index 21fe0c4..0e4d63b 100644
--- a/src/iss/semihosting/semihosting.cpp
+++ b/src/iss/semihosting/semihosting.cpp
@@ -44,7 +44,7 @@ const char* SYS_OPEN_MODES_STRS[] = {"r", "rb", "r+", "r+b", "w", "wb", "w+", "w
 
 template <typename T> T sh_read_field(iss::arch_if* arch_if_ptr, T addr, int len = 4) {
     uint8_t bytes[4];
-    auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, addr, 4, &bytes[0]);
+    auto res = arch_if_ptr->read({iss::address_type::LOGICAL, iss::access_type::DEBUG_READ, 0, addr}, 4, &bytes[0]);
     // auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, *parameter, 1, &character);
 
     if(res != iss::Ok) {
@@ -199,7 +199,7 @@ template <typename T> void semihosting_callback<T>::operator()(iss::arch_if* arc
         }
         buffer.resize(num_read);
         for(int i = 0; i < num_read; i++) {
-            auto res = arch_if_ptr->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, addr + i, 1, &buffer[i]);
+            auto res = arch_if_ptr->write({iss::address_type::LOGICAL, iss::access_type::DEBUG_READ, 0, addr + i}, 1, &buffer[i]);
             if(res != iss::Ok)
                 return;
         }
@@ -277,7 +277,7 @@ template <typename T> void semihosting_callback<T>::operator()(iss::arch_if* arc
 
         for(int i = 0; i < buffer_len; i++) {
             uint8_t character = filename[i];
-            auto res = arch_if_ptr->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, (*parameter) + i, 1, &character);
+            auto res = arch_if_ptr->write({iss::address_type::LOGICAL, iss::access_type::DEBUG_READ, 0, (*parameter) + i}, 1, &character);
             if(res != iss::Ok)
                 return;
         }
@@ -295,7 +295,7 @@ template <typename T> void semihosting_callback<T>::operator()(iss::arch_if* arc
     }
     case semihosting_syscalls::SYS_WRITEC: {
         uint8_t character;
-        auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, *parameter, 1, &character);
+        auto res = arch_if_ptr->read({iss::address_type::LOGICAL, iss::access_type::DEBUG_READ, 0, *parameter}, 1, &character);
         if(res != iss::Ok)
             return;
         putchar(character);
@@ -304,7 +304,7 @@ template <typename T> void semihosting_callback<T>::operator()(iss::arch_if* arc
     case semihosting_syscalls::SYS_WRITE0: {
         uint8_t character;
         while(1) {
-            auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, *parameter, 1, &character);
+            auto res = arch_if_ptr->read({iss::address_type::LOGICAL, iss::access_type::DEBUG_READ, 0, *parameter}, 1, &character);
             if(res != iss::Ok)
                 return;
             if(character == 0)
diff --git a/src/main.cpp b/src/main.cpp
index b55de4e..1e03885 100644
--- a/src/main.cpp
+++ b/src/main.cpp
@@ -279,8 +279,8 @@ int main(int argc, char* argv[]) {
             }
             LOGGER(DEFAULT)::set_reporting_level(logging::ERR);
             for(auto addr = start_addr; addr < end_addr; addr += data.size()) {
-                vm->get_arch()->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0 /*MEM*/, addr, data.size(),
-                                     data.data()); // FIXME: get space from iss::arch::traits<ARCH>::mem_type_e::MEM
+                vm->get_arch()->read({iss::address_type::LOGICAL, iss::access_type::DEBUG_READ, 0 /*iss::arch::traits<ARCH>::MEM*/, addr},
+                                     data.size(), data.data());
 
                 // TODO : obey Target endianess
                 uint32_t to_print = (data[3] << 24) + (data[2] << 16) + (data[1] << 8) + data[0];
diff --git a/src/vm/vector_functions.h b/src/vm/vector_functions.h
index de8c78f..83b1552 100644
--- a/src/vm/vector_functions.h
+++ b/src/vm/vector_functions.h
@@ -74,14 +74,14 @@ constexpr size_t map_index_size[9] = {std::numeric_limits<size_t>::max(),
 
 inline bool softvec_read(void* core, uint64_t addr, uint64_t length, uint8_t* data) {
     // Read length bytes from addr into *data
-    iss::status status = static_cast<iss::arch_if*>(core)->read(iss::address_type::PHYSICAL, iss::access_type::READ,
-                                                                0 /*traits<ARCH>::MEM*/, addr, length, data);
+    iss::status status = static_cast<iss::arch_if*>(core)->read(
+        {iss::address_type::LOGICAL, iss::access_type::READ, 0 /*traits<ARCH>::MEM*/, addr}, length, data);
     return status == iss::Ok;
 }
 inline bool softvec_write(void* core, uint64_t addr, uint64_t length, uint8_t* data) {
     // Write length bytes from addr into *data
-    iss::status status = static_cast<iss::arch_if*>(core)->write(iss::address_type::PHYSICAL, iss::access_type::READ,
-                                                                 0 /*traits<ARCH>::MEM*/, addr, length, data);
+    iss::status status = static_cast<iss::arch_if*>(core)->write(
+        {iss::address_type::LOGICAL, iss::access_type::WRITE, 0 /*traits<ARCH>::MEM*/, addr}, length, data);
     return status == iss::Ok;
 }
 template <size_t VLEN>

From 527098d52c6cc569528c4fcf1b24b253c694a11e Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Sat, 22 Nov 2025 16:43:53 +0100
Subject: [PATCH 31/77] updates templates and regenerates cores llvm vms are
 not regenerated

---
 gen_input/templates/CORENAME.h.gtl          |   2 +-
 gen_input/templates/asmjit/CORENAME.cpp.gtl |   3 +-
 gen_input/templates/interp/CORENAME.cpp.gtl |   2 +-
 gen_input/templates/llvm/CORENAME.cpp.gtl   |   6 +-
 src/iss/arch/riscv_hart_m_p.h               | 128 +++++++++---------
 src/iss/arch/riscv_hart_msu_vp.h            | 138 ++++++++++----------
 src/iss/arch/riscv_hart_mu_p.h              | 137 ++++++++++---------
 src/iss/arch/rv32gc.h                       |   2 +-
 src/iss/arch/rv32gcv.h                      |   2 +-
 src/iss/arch/rv32i.h                        |   2 +-
 src/iss/arch/rv32imac.h                     |   2 +-
 src/iss/arch/rv64gc.h                       |   2 +-
 src/iss/arch/rv64gcv.h                      |   2 +-
 src/iss/arch/rv64i.h                        |   2 +-
 src/iss/arch/tgc5c.h                        |   2 +-
 src/vm/asmjit/vm_rv32gc.cpp                 |   3 +-
 src/vm/asmjit/vm_rv32gcv.cpp                |   3 +-
 src/vm/asmjit/vm_rv32i.cpp                  |   3 +-
 src/vm/asmjit/vm_rv32imac.cpp               |   3 +-
 src/vm/asmjit/vm_rv64gc.cpp                 |   3 +-
 src/vm/asmjit/vm_rv64gcv.cpp                |   3 +-
 src/vm/asmjit/vm_rv64i.cpp                  |   3 +-
 src/vm/asmjit/vm_tgc5c.cpp                  |   3 +-
 src/vm/interp/vm_rv32gc.cpp                 |   2 +-
 src/vm/interp/vm_rv32gcv.cpp                |   2 +-
 src/vm/interp/vm_rv32i.cpp                  |   2 +-
 src/vm/interp/vm_rv32imac.cpp               |   2 +-
 src/vm/interp/vm_rv64gc.cpp                 |   2 +-
 src/vm/interp/vm_rv64gcv.cpp                |   2 +-
 src/vm/interp/vm_rv64i.cpp                  |   2 +-
 src/vm/interp/vm_tgc5c.cpp                  |   2 +-
 31 files changed, 225 insertions(+), 247 deletions(-)

diff --git a/gen_input/templates/CORENAME.h.gtl b/gen_input/templates/CORENAME.h.gtl
index 53f5d41..d59ebc6 100644
--- a/gen_input/templates/CORENAME.h.gtl
+++ b/gen_input/templates/CORENAME.h.gtl
@@ -209,7 +209,7 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
 
     enum sreg_flag_e { FLAGS };
 
-    enum mem_type_e { ${spaces.collect{it.name}.join(', ')}, IMEM = MEM };
+    enum mem_type_e { ${spaces.collect{it.name}.join(', ')}, IMEM = std::numeric_limits<decltype(phys_addr_t::space)>::max()};
     
     static constexpr std::array<const uint64_t, ${spaces.size()}> mem_sizes{{
         ${spaces.collect{overflowsafeSize(it.value)}.join(',\n        ')}
diff --git a/gen_input/templates/asmjit/CORENAME.cpp.gtl b/gen_input/templates/asmjit/CORENAME.cpp.gtl
index 25af08d..76b4845 100644
--- a/gen_input/templates/asmjit/CORENAME.cpp.gtl
+++ b/gen_input/templates/asmjit/CORENAME.cpp.gtl
@@ -365,9 +365,8 @@ template <typename ARCH>
 continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, jit_holder& jh) {
     enum {TRAP_ID=1<<16};
     code_word_t instr = 0;
-    phys_addr_t paddr(pc);
     auto *const data = (uint8_t *)&instr;
-    auto res = this->core.read(paddr, 4, data);
+    auto res = this->core.read({address_type::LOGICAL, access_type::DEBUG_READ, arch::traits<ARCH>::IMEM, pc.val}, 4, data);
     if (res != iss::Ok)
         return ILLEGAL_FETCH;
     if (instr == 0x0000006f || (instr&0xffff)==0xa001)
diff --git a/gen_input/templates/interp/CORENAME.cpp.gtl b/gen_input/templates/interp/CORENAME.cpp.gtl
index 879141c..ed8c026 100644
--- a/gen_input/templates/interp/CORENAME.cpp.gtl
+++ b/gen_input/templates/interp/CORENAME.cpp.gtl
@@ -295,7 +295,7 @@ private:
     decoder instr_decoder;
 
     iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
-        if (this->core.read(iss::address_type::PHYSICAL, pc.access, pc.space, pc.val, 4, data) != iss::Ok)
+        if (this->core.read({iss::address_type::LOGICAL, pc.access, arch::traits<ARCH>::IMEM, pc.val}, 4, data) != iss::Ok)
                     return iss::Err;
         return iss::Ok;
     }
diff --git a/gen_input/templates/llvm/CORENAME.cpp.gtl b/gen_input/templates/llvm/CORENAME.cpp.gtl
index 3b63455..36d5bb9 100644
--- a/gen_input/templates/llvm/CORENAME.cpp.gtl
+++ b/gen_input/templates/llvm/CORENAME.cpp.gtl
@@ -271,11 +271,9 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, BasicBlock *this_block)
     // we fetch at max 4 byte, alignment is 2
     enum {TRAP_ID=1<<16};
     code_word_t instr = 0;
-    // const typename traits::addr_t upper_bits = ~traits::PGMASK;
-    phys_addr_t paddr(pc);
     auto *const data = (uint8_t *)&instr;
-    auto res = this->core.read(paddr, 4, data);
-    if (res != iss::Ok) 
+    auto res = this->core.read({address_type::LOGICAL, access_type::DEBUG_READ, arch::traits<ARCH>::IMEM, pc.val}, 4, data);
+    if (res != iss::Ok)
         return std::make_tuple(ILLEGAL_FETCH, nullptr);
     if (instr == 0x0000006f || (instr&0xffff)==0xa001){
         this->builder.CreateBr(this->leave_blk);
diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h
index 2c09e7b..af58e29 100644
--- a/src/iss/arch/riscv_hart_m_p.h
+++ b/src/iss/arch/riscv_hart_m_p.h
@@ -133,7 +133,7 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_m_p : pub
     iss::status read_ip(unsigned addr, reg_t& val);
 
     void check_interrupt();
-    mem::memory_with_htif<BASE> default_mem;
+    mem::neumann_memory_with_htif<BASE> default_mem;
 };
 
 template <typename BASE, features_e FEAT>
@@ -173,35 +173,6 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const addr_t& a, const unsigned len
 #endif
     try {
         switch(space) {
-        case traits<BASE>::MEM: {
-            auto alignment = is_fetch(access) ? (this->has_compressed() ? 2 : 4) : std::min<unsigned>(length, sizeof(reg_t));
-            if(unlikely(is_fetch(access) && (addr & (alignment - 1)))) {
-                this->fault_data = addr;
-                if(is_debug(access))
-                    throw trap_access(0, addr);
-                this->reg.trap_state = (1UL << 31); // issue trap 0
-                return iss::Err;
-            }
-            try {
-                if(!is_debug(access) && (addr & (alignment - 1))) {
-                    this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_MISALIGNED_LOAD << 16;
-                    this->fault_data = addr;
-                    return iss::Err;
-                }
-                auto res = this->memory.rd_mem({address_type::PHYSICAL, a.access, a.space, a.val}, length, data);
-                if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
-                    this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_LOAD_ACCESS << 16;
-                    this->fault_data = addr;
-                }
-                return res;
-            } catch(trap_access& ta) {
-                if((access & access_type::DEBUG) == 0) {
-                    this->reg.trap_state = (1UL << 31) | ta.id;
-                    this->fault_data = ta.addr;
-                }
-                return iss::Err;
-            }
-        } break;
         case traits<BASE>::CSR: {
             if(length != sizeof(reg_t))
                 return iss::Err;
@@ -230,8 +201,35 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const addr_t& a, const unsigned len
             } else
                 memset(data, 0, length);
         } break;
-        default:
-            return iss::Err; // assert("Not supported");
+        default: {
+            auto alignment = is_fetch(access) ? (this->has_compressed() ? 2 : 4) : std::min<unsigned>(length, sizeof(reg_t));
+            if(unlikely(is_fetch(access) && (addr & (alignment - 1)))) {
+                this->fault_data = addr;
+                if(is_debug(access))
+                    throw trap_access(0, addr);
+                this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_MISALIGNED_FETCH << 16;
+                return iss::Err;
+            }
+            try {
+                if(!is_debug(access) && (addr & (alignment - 1))) {
+                    this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_MISALIGNED_LOAD << 16;
+                    this->fault_data = addr;
+                    return iss::Err;
+                }
+                auto res = this->memory.rd_mem({address_type::PHYSICAL, a.access, a.space, a.val}, length, data);
+                if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
+                    this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_LOAD_ACCESS << 16;
+                    this->fault_data = addr;
+                }
+                return res;
+            } catch(trap_access& ta) {
+                if((access & access_type::DEBUG) == 0) {
+                    this->reg.trap_state = (1UL << 31) | ta.id;
+                    this->fault_data = ta.addr;
+                }
+                return iss::Err;
+            }
+        } break;
         }
         return iss::Ok;
     } catch(trap_access& ta) {
@@ -244,11 +242,11 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const addr_t& a, const unsigned len
 }
 
 template <typename BASE, features_e FEAT>
-iss::status riscv_hart_m_p<BASE, FEAT>::write(const addr_t& addr_, const unsigned length, const uint8_t* const data) {
-    auto& addr = addr_.val;
-    auto& space = addr_.space;
-    auto& access = addr_.access;
-    auto& type = addr_.type;
+iss::status riscv_hart_m_p<BASE, FEAT>::write(const addr_t& a, const unsigned length, const uint8_t* const data) {
+    auto& addr = a.val;
+    auto& space = a.space;
+    auto& access = a.access;
+    auto& type = a.type;
 #ifndef NDEBUG
     const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
     switch(length) {
@@ -274,33 +272,6 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const addr_t& addr_, const unsigne
 #endif
     try {
         switch(space) {
-        case traits<BASE>::MEM: {
-            if(unlikely(is_fetch(access) && (addr & 0x1) == 1)) {
-                this->fault_data = addr;
-                if(access && iss::access_type::DEBUG)
-                    throw trap_access(0, addr);
-                this->reg.trap_state = (1UL << 31); // issue trap 0
-                return iss::Err;
-            }
-            try {
-                auto alignment = std::min<unsigned>(length, sizeof(reg_t));
-                if(length > 1 && (addr & (alignment - 1)) && !is_debug(access)) {
-                    this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_MISALIGNED_STORE << 16;
-                    this->fault_data = addr;
-                    return iss::Err;
-                }
-                auto res = this->memory.wr_mem({address_type::PHYSICAL, addr_.access, addr_.space, addr_.val}, length, data);
-                if(unlikely(res != iss::Ok && !is_debug(access))) {
-                    this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_STORE_ACCESS << 16;
-                    this->fault_data = addr;
-                }
-                return res;
-            } catch(trap_access& ta) {
-                this->reg.trap_state = (1UL << 31) | ta.id;
-                this->fault_data = ta.addr;
-                return iss::Err;
-            }
-        } break;
         case traits<BASE>::CSR: {
             if(length != sizeof(reg_t))
                 return iss::Err;
@@ -324,8 +295,33 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const addr_t& addr_, const unsigne
         case traits<BASE>::RES: {
             atomic_reservation[addr] = data[0];
         } break;
-        default:
-            return iss::Err;
+        default: {
+            if(unlikely(is_fetch(access) && (addr & 0x1) == 1)) {
+                this->fault_data = addr;
+                if(access && access_type::DEBUG)
+                    throw trap_access(0, addr);
+                this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_MISALIGNED_FETCH << 16;
+                return iss::Err;
+            }
+            try {
+                auto alignment = std::min<unsigned>(length, sizeof(reg_t));
+                if(length > 1 && (addr & (alignment - 1)) && !is_debug(access)) {
+                    this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_MISALIGNED_STORE << 16;
+                    this->fault_data = addr;
+                    return iss::Err;
+                }
+                auto res = this->memory.wr_mem({address_type::PHYSICAL, a.access, a.space, a.val}, length, data);
+                if(unlikely(res != iss::Ok && !is_debug(access))) {
+                    this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_STORE_ACCESS << 16;
+                    this->fault_data = addr;
+                }
+                return res;
+            } catch(trap_access& ta) {
+                this->reg.trap_state = (1UL << 31) | ta.id;
+                this->fault_data = ta.addr;
+                return iss::Err;
+            }
+        } break;
         }
         return iss::Ok;
     } catch(trap_access& ta) {
diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h
index 5371c91..f5cdab2 100644
--- a/src/iss/arch/riscv_hart_msu_vp.h
+++ b/src/iss/arch/riscv_hart_msu_vp.h
@@ -168,7 +168,7 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_msu_vp :
 
     void check_interrupt();
     mem::mmu<BASE> mmu;
-    mem::memory_with_htif<BASE> default_mem;
+    mem::neumann_memory_with_htif<BASE> default_mem;
 };
 
 template <typename BASE, features_e FEAT>
@@ -236,11 +236,11 @@ riscv_hart_msu_vp<BASE, FEAT>::riscv_hart_msu_vp()
 }
 
 template <typename BASE, features_e FEAT>
-iss::status riscv_hart_msu_vp<BASE, FEAT>::read(const addr_t& addr_, const unsigned length, uint8_t* const data) {
-    auto& addr = addr_.val;
-    auto& space = addr_.space;
-    auto& access = addr_.access;
-    auto& type = addr_.type;
+iss::status riscv_hart_msu_vp<BASE, FEAT>::read(const addr_t& a, const unsigned length, uint8_t* const data) {
+    auto& addr = a.val;
+    auto& space = a.space;
+    auto& access = a.access;
+    auto& type = a.type;
 #ifndef NDEBUG
     if(access && iss::access_type::DEBUG) {
         ILOG(isslogger, logging::TRACEALL, fmt::format("debug read of {} bytes @addr 0x{:x}", length, addr));
@@ -252,35 +252,6 @@ iss::status riscv_hart_msu_vp<BASE, FEAT>::read(const addr_t& addr_, const unsig
 #endif
     try {
         switch(space) {
-        case traits<BASE>::MEM: {
-            auto alignment = is_fetch(access) ? (this->has_compressed() ? 2 : 4) : std::min<unsigned>(length, sizeof(reg_t));
-            if(unlikely(is_fetch(access) && (addr & (alignment - 1)))) {
-                this->fault_data = addr;
-                if(is_debug(access))
-                    throw trap_access(0, addr);
-                this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_MISALIGNED_FETCH << 16;
-                return iss::Err;
-            }
-            try {
-                if(!is_debug(access) && (addr & (alignment - 1))) {
-                    this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_MISALIGNED_LOAD << 16;
-                    this->fault_data = addr;
-                    return iss::Err;
-                }
-                auto res = this->memory.rd_mem({address_type::VIRTUAL, addr_.access, addr_.space, addr_.val}, length, data);
-                if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
-                    this->reg.trap_state = (1UL << 31) | (traits<BASE>::RV_CAUSE_LOAD_ACCESS << 16);
-                    this->fault_data = addr;
-                }
-                return res;
-            } catch(trap_access& ta) {
-                if((access & access_type::DEBUG) == 0) {
-                    this->reg.trap_state = (1UL << 31) | ta.id;
-                    this->fault_data = ta.addr;
-                }
-                return iss::Err;
-            }
-        } break;
         case traits<BASE>::CSR: {
             if(length != sizeof(reg_t))
                 return iss::Err;
@@ -312,8 +283,35 @@ iss::status riscv_hart_msu_vp<BASE, FEAT>::read(const addr_t& addr_, const unsig
             } else
                 memset(data, 0, length);
         } break;
-        default:
-            return iss::Err; // assert("Not supported");
+        default: {
+            auto alignment = is_fetch(access) ? (this->has_compressed() ? 2 : 4) : std::min<unsigned>(length, sizeof(reg_t));
+            if(unlikely(is_fetch(access) && (addr & (alignment - 1)))) {
+                this->fault_data = addr;
+                if(is_debug(access))
+                    throw trap_access(0, addr);
+                this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_MISALIGNED_FETCH << 16;
+                return iss::Err;
+            }
+            try {
+                if(!is_debug(access) && (addr & (alignment - 1))) {
+                    this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_MISALIGNED_LOAD << 16;
+                    this->fault_data = addr;
+                    return iss::Err;
+                }
+                auto res = this->memory.rd_mem({address_type::VIRTUAL, a.access, a.space, a.val}, length, data);
+                if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
+                    this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_LOAD_ACCESS << 16;
+                    this->fault_data = addr;
+                }
+                return res;
+            } catch(trap_access& ta) {
+                if((access & access_type::DEBUG) == 0) {
+                    this->reg.trap_state = (1UL << 31) | ta.id;
+                    this->fault_data = ta.addr;
+                }
+                return iss::Err;
+            }
+        } break;
         }
         return iss::Ok;
     } catch(trap_access& ta) {
@@ -326,11 +324,11 @@ iss::status riscv_hart_msu_vp<BASE, FEAT>::read(const addr_t& addr_, const unsig
 }
 
 template <typename BASE, features_e FEAT>
-iss::status riscv_hart_msu_vp<BASE, FEAT>::write(const addr_t& addr_, const unsigned length, const uint8_t* const data) {
-    auto& addr = addr_.val;
-    auto& space = addr_.space;
-    auto& access = addr_.access;
-    auto& type = addr_.type;
+iss::status riscv_hart_msu_vp<BASE, FEAT>::write(const addr_t& a, const unsigned length, const uint8_t* const data) {
+    auto& addr = a.val;
+    auto& space = a.space;
+    auto& access = a.access;
+    auto& type = a.type;
 #ifndef NDEBUG
     const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
     switch(length) {
@@ -356,33 +354,6 @@ iss::status riscv_hart_msu_vp<BASE, FEAT>::write(const addr_t& addr_, const unsi
 #endif
     try {
         switch(space) {
-        case traits<BASE>::MEM: {
-            if(unlikely(is_fetch(access) && (addr & 0x1) == 1)) {
-                this->fault_data = addr;
-                if(access && iss::access_type::DEBUG)
-                    throw trap_access(0, addr);
-                this->reg.trap_state = (1UL << 31); // issue trap 0
-                return iss::Err;
-            }
-            try {
-                auto alignment = std::min<unsigned>(length, sizeof(reg_t));
-                if(length > 1 && (addr & (alignment - 1)) && !is_debug(access)) {
-                    this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_MISALIGNED_STORE << 16;
-                    this->fault_data = addr;
-                    return iss::Err;
-                }
-                auto res = this->memory.wr_mem({address_type::VIRTUAL, addr_.access, addr_.space, addr_.val}, length, data);
-                if(unlikely(res != iss::Ok && !is_debug(access))) {
-                    this->reg.trap_state = (1UL << 31) | (traits<BASE>::RV_CAUSE_STORE_ACCESS << 16);
-                    this->fault_data = addr;
-                }
-                return res;
-            } catch(trap_access& ta) {
-                this->reg.trap_state = (1UL << 31) | ta.id;
-                this->fault_data = ta.addr;
-                return iss::Err;
-            }
-        } break;
         case traits<BASE>::CSR: {
             if(length != sizeof(reg_t))
                 return iss::Err;
@@ -417,8 +388,33 @@ iss::status riscv_hart_msu_vp<BASE, FEAT>::write(const addr_t& addr_, const unsi
         case traits<BASE>::RES: {
             atomic_reservation[addr] = data[0];
         } break;
-        default:
-            return iss::Err;
+        default: {
+            if(unlikely(is_fetch(access) && (addr & 0x1) == 1)) {
+                this->fault_data = addr;
+                if(access && iss::access_type::DEBUG)
+                    throw trap_access(0, addr);
+                this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_MISALIGNED_FETCH << 16;
+                return iss::Err;
+            }
+            try {
+                auto alignment = std::min<unsigned>(length, sizeof(reg_t));
+                if(length > 1 && (addr & (alignment - 1)) && !is_debug(access)) {
+                    this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_MISALIGNED_STORE << 16;
+                    this->fault_data = addr;
+                    return iss::Err;
+                }
+                auto res = this->memory.wr_mem({address_type::VIRTUAL, a.access, a.space, a.val}, length, data);
+                if(unlikely(res != iss::Ok && !is_debug(access))) {
+                    this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_STORE_ACCESS << 16;
+                    this->fault_data = addr;
+                }
+                return res;
+            } catch(trap_access& ta) {
+                this->reg.trap_state = (1UL << 31) | ta.id;
+                this->fault_data = ta.addr;
+                return iss::Err;
+            }
+        } break;
         }
         return iss::Ok;
     } catch(trap_access& ta) {
diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h
index 939d26b..a48753e 100644
--- a/src/iss/arch/riscv_hart_mu_p.h
+++ b/src/iss/arch/riscv_hart_mu_p.h
@@ -157,7 +157,7 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_mu_p : pu
     iss::status read_ip(unsigned addr, reg_t& val);
 
     void check_interrupt();
-    mem::memory_with_htif<BASE> default_mem;
+    mem::neumann_memory_with_htif<BASE> default_mem;
 };
 
 template <typename BASE, features_e FEAT>
@@ -203,11 +203,12 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
 }
 
 template <typename BASE, features_e FEAT>
-iss::status riscv_hart_mu_p<BASE, FEAT>::read(const addr_t& addr_, const unsigned length, uint8_t* const data) {
-    auto& addr = addr_.val;
-    auto& space = addr_.space;
-    auto& access = addr_.access;
-    auto& type = addr_.type;
+iss::status riscv_hart_mu_p<BASE, FEAT>::read(const addr_t& a, const unsigned length, uint8_t* const data) {
+    auto& addr = a.val;
+    auto& space = a.space;
+    auto& access = a.access;
+    auto& type = a.type;
+
 #ifndef NDEBUG
     if(access && iss::access_type::DEBUG) {
         ILOG(isslogger, logging::TRACEALL, fmt::format("debug read of {} bytes @addr 0x{:x}", length, addr));
@@ -219,35 +220,6 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const addr_t& addr_, const unsigne
 #endif
     try {
         switch(space) {
-        case traits<BASE>::MEM: {
-            auto alignment = is_fetch(access) ? (this->has_compressed() ? 2 : 4) : std::min<unsigned>(length, sizeof(reg_t));
-            if(unlikely(is_fetch(access) && (addr & (alignment - 1)))) {
-                this->fault_data = addr;
-                if(is_debug(access))
-                    throw trap_access(0, addr);
-                this->reg.trap_state = (1UL << 31); // issue trap 0
-                return iss::Err;
-            }
-            try {
-                if(!is_debug(access) && (addr & (alignment - 1))) {
-                    this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_MISALIGNED_LOAD << 16;
-                    this->fault_data = addr;
-                    return iss::Err;
-                }
-                auto res = this->memory.rd_mem({address_type::PHYSICAL, addr_.access, addr_.space, addr_.val}, length, data);
-                if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
-                    this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_LOAD_ACCESS << 16;
-                    this->fault_data = addr;
-                }
-                return res;
-            } catch(trap_access& ta) {
-                if((access & access_type::DEBUG) == 0) {
-                    this->reg.trap_state = (1UL << 31) | ta.id;
-                    this->fault_data = ta.addr;
-                }
-                return iss::Err;
-            }
-        } break;
         case traits<BASE>::CSR: {
             if(length != sizeof(reg_t))
                 return iss::Err;
@@ -276,8 +248,35 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const addr_t& addr_, const unsigne
             } else
                 memset(data, 0, length);
         } break;
-        default:
-            return iss::Err; // assert("Not supported");
+        default: {
+            auto alignment = is_fetch(access) ? (this->has_compressed() ? 2 : 4) : std::min<unsigned>(length, sizeof(reg_t));
+            if(unlikely(is_fetch(access) && (addr & (alignment - 1)))) {
+                this->fault_data = addr;
+                if(is_debug(access))
+                    throw trap_access(0, addr);
+                this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_MISALIGNED_FETCH << 16;
+                return iss::Err;
+            }
+            try {
+                if(!is_debug(access) && (addr & (alignment - 1))) {
+                    this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_MISALIGNED_LOAD << 16;
+                    this->fault_data = addr;
+                    return iss::Err;
+                }
+                auto res = this->memory.rd_mem({address_type::PHYSICAL, a.access, a.space, a.val}, length, data);
+                if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
+                    this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_LOAD_ACCESS << 16;
+                    this->fault_data = addr;
+                }
+                return res;
+            } catch(trap_access& ta) {
+                if((access & access_type::DEBUG) == 0) {
+                    this->reg.trap_state = (1UL << 31) | ta.id;
+                    this->fault_data = ta.addr;
+                }
+                return iss::Err;
+            }
+        } break;
         }
         return iss::Ok;
     } catch(trap_access& ta) {
@@ -290,11 +289,11 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const addr_t& addr_, const unsigne
 }
 
 template <typename BASE, features_e FEAT>
-iss::status riscv_hart_mu_p<BASE, FEAT>::write(const addr_t& addr_, const unsigned length, const uint8_t* const data) {
-    auto& addr = addr_.val;
-    auto& space = addr_.space;
-    auto& access = addr_.access;
-    auto& type = addr_.type;
+iss::status riscv_hart_mu_p<BASE, FEAT>::write(const addr_t& a, const unsigned length, const uint8_t* const data) {
+    auto& addr = a.val;
+    auto& space = a.space;
+    auto& access = a.access;
+    auto& type = a.type;
 #ifndef NDEBUG
     const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
     switch(length) {
@@ -320,12 +319,35 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const addr_t& addr_, const unsign
 #endif
     try {
         switch(space) {
-        case traits<BASE>::MEM: {
+        case traits<BASE>::CSR: {
+            if(length != sizeof(reg_t))
+                return iss::Err;
+            auto res = this->write_csr(addr, *reinterpret_cast<const reg_t*>(data));
+            if(res != iss::Ok && !is_debug(access))
+                this->reg.trap_state = (1U << 31) | traits<BASE>::RV_CAUSE_ILLEGAL_INSTRUCTION << 16;
+            return res;
+        } break;
+        case traits<BASE>::FENCE: {
+            switch(addr) {
+            case traits<BASE>::fence:
+            case traits<BASE>::fencei:
+                break;
+            case traits<BASE>::fencevma: {
+                this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_ILLEGAL_INSTRUCTION << 16;
+            }
+            default:
+                return iss::Ok;
+            }
+        }
+        case traits<BASE>::RES: {
+            atomic_reservation[addr] = data[0];
+        } break;
+        default: {
             if(unlikely(is_fetch(access) && (addr & 0x1) == 1)) {
                 this->fault_data = addr;
                 if(access && iss::access_type::DEBUG)
                     throw trap_access(0, addr);
-                this->reg.trap_state = (1UL << 31); // issue trap 0
+                this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_MISALIGNED_FETCH << 16;
                 return iss::Err;
             }
             try {
@@ -335,7 +357,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const addr_t& addr_, const unsign
                     this->fault_data = addr;
                     return iss::Err;
                 }
-                auto res = this->memory.wr_mem({address_type::PHYSICAL, addr_.access, addr_.space, addr_.val}, length, data);
+                auto res = this->memory.wr_mem({address_type::PHYSICAL, a.access, a.space, a.val}, length, data);
                 if(unlikely(res != iss::Ok && !is_debug(access))) {
                     this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_STORE_ACCESS << 16;
                     this->fault_data = addr;
@@ -347,31 +369,6 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const addr_t& addr_, const unsign
                 return iss::Err;
             }
         } break;
-        case traits<BASE>::CSR: {
-            if(length != sizeof(reg_t))
-                return iss::Err;
-            auto res = this->write_csr(addr, *reinterpret_cast<const reg_t*>(data));
-            if(res != iss::Ok && !is_debug(access))
-                this->reg.trap_state = (1U << 31) | traits<BASE>::RV_CAUSE_ILLEGAL_INSTRUCTION << 16;
-            return res;
-        } break;
-        case traits<BASE>::FENCE: {
-            switch(addr) {
-            case traits<BASE>::fence:
-            case traits<BASE>::fencei:
-                break;
-            case traits<BASE>::fencevma: {
-                this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_ILLEGAL_INSTRUCTION << 16;
-            }
-            default:
-                return iss::Ok;
-            }
-        }
-        case traits<BASE>::RES: {
-            atomic_reservation[addr] = data[0];
-        } break;
-        default:
-            return iss::Err;
         }
         return iss::Ok;
     } catch(trap_access& ta) {
diff --git a/src/iss/arch/rv32gc.h b/src/iss/arch/rv32gc.h
index f105c10..4f54b68 100644
--- a/src/iss/arch/rv32gc.h
+++ b/src/iss/arch/rv32gc.h
@@ -477,7 +477,7 @@ template <> struct traits<rv32gc> {
 
     enum sreg_flag_e { FLAGS };
 
-    enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = MEM };
+    enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = std::numeric_limits<decltype(phys_addr_t::space)>::max()};
     
     static constexpr std::array<const uint64_t, 4> mem_sizes{{
         4294967296,
diff --git a/src/iss/arch/rv32gcv.h b/src/iss/arch/rv32gcv.h
index dca317e..2680cba 100644
--- a/src/iss/arch/rv32gcv.h
+++ b/src/iss/arch/rv32gcv.h
@@ -591,7 +591,7 @@ template <> struct traits<rv32gcv> {
 
     enum sreg_flag_e { FLAGS };
 
-    enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = MEM };
+    enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = std::numeric_limits<decltype(phys_addr_t::space)>::max()};
     
     static constexpr std::array<const uint64_t, 4> mem_sizes{{
         4294967296,
diff --git a/src/iss/arch/rv32i.h b/src/iss/arch/rv32i.h
index 0d074be..1a81b3f 100644
--- a/src/iss/arch/rv32i.h
+++ b/src/iss/arch/rv32i.h
@@ -378,7 +378,7 @@ template <> struct traits<rv32i> {
 
     enum sreg_flag_e { FLAGS };
 
-    enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = MEM };
+    enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = std::numeric_limits<decltype(phys_addr_t::space)>::max()};
     
     static constexpr std::array<const uint64_t, 4> mem_sizes{{
         4294967296,
diff --git a/src/iss/arch/rv32imac.h b/src/iss/arch/rv32imac.h
index 71825c4..ba90c01 100644
--- a/src/iss/arch/rv32imac.h
+++ b/src/iss/arch/rv32imac.h
@@ -378,7 +378,7 @@ template <> struct traits<rv32imac> {
 
     enum sreg_flag_e { FLAGS };
 
-    enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = MEM };
+    enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = std::numeric_limits<decltype(phys_addr_t::space)>::max()};
     
     static constexpr std::array<const uint64_t, 4> mem_sizes{{
         4294967296,
diff --git a/src/iss/arch/rv64gc.h b/src/iss/arch/rv64gc.h
index 7081f29..f78ae2e 100644
--- a/src/iss/arch/rv64gc.h
+++ b/src/iss/arch/rv64gc.h
@@ -477,7 +477,7 @@ template <> struct traits<rv64gc> {
 
     enum sreg_flag_e { FLAGS };
 
-    enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = MEM };
+    enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = std::numeric_limits<decltype(phys_addr_t::space)>::max()};
     
     static constexpr std::array<const uint64_t, 4> mem_sizes{{
         std::numeric_limits<uint64_t>::max(),
diff --git a/src/iss/arch/rv64gcv.h b/src/iss/arch/rv64gcv.h
index 5a70c40..7ffc113 100644
--- a/src/iss/arch/rv64gcv.h
+++ b/src/iss/arch/rv64gcv.h
@@ -591,7 +591,7 @@ template <> struct traits<rv64gcv> {
 
     enum sreg_flag_e { FLAGS };
 
-    enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = MEM };
+    enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = std::numeric_limits<decltype(phys_addr_t::space)>::max()};
     
     static constexpr std::array<const uint64_t, 4> mem_sizes{{
         std::numeric_limits<uint64_t>::max(),
diff --git a/src/iss/arch/rv64i.h b/src/iss/arch/rv64i.h
index a5d1afd..76df877 100644
--- a/src/iss/arch/rv64i.h
+++ b/src/iss/arch/rv64i.h
@@ -378,7 +378,7 @@ template <> struct traits<rv64i> {
 
     enum sreg_flag_e { FLAGS };
 
-    enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = MEM };
+    enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = std::numeric_limits<decltype(phys_addr_t::space)>::max()};
     
     static constexpr std::array<const uint64_t, 4> mem_sizes{{
         std::numeric_limits<uint64_t>::max(),
diff --git a/src/iss/arch/tgc5c.h b/src/iss/arch/tgc5c.h
index f96f115..a07cc99 100644
--- a/src/iss/arch/tgc5c.h
+++ b/src/iss/arch/tgc5c.h
@@ -378,7 +378,7 @@ template <> struct traits<tgc5c> {
 
     enum sreg_flag_e { FLAGS };
 
-    enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = MEM };
+    enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = std::numeric_limits<decltype(phys_addr_t::space)>::max()};
     
     static constexpr std::array<const uint64_t, 4> mem_sizes{{
         4294967296,
diff --git a/src/vm/asmjit/vm_rv32gc.cpp b/src/vm/asmjit/vm_rv32gc.cpp
index 07f2bdf..fd3c84f 100644
--- a/src/vm/asmjit/vm_rv32gc.cpp
+++ b/src/vm/asmjit/vm_rv32gc.cpp
@@ -9986,9 +9986,8 @@ template <typename ARCH>
 continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, jit_holder& jh) {
     enum {TRAP_ID=1<<16};
     code_word_t instr = 0;
-    phys_addr_t paddr(pc);
     auto *const data = (uint8_t *)&instr;
-    auto res = this->core.read(paddr, 4, data);
+    auto res = this->core.read({address_type::LOGICAL, access_type::DEBUG_READ, arch::traits<ARCH>::IMEM, pc.val}, 4, data);
     if (res != iss::Ok)
         return ILLEGAL_FETCH;
     if (instr == 0x0000006f || (instr&0xffff)==0xa001)
diff --git a/src/vm/asmjit/vm_rv32gcv.cpp b/src/vm/asmjit/vm_rv32gcv.cpp
index 61499b2..92023c1 100644
--- a/src/vm/asmjit/vm_rv32gcv.cpp
+++ b/src/vm/asmjit/vm_rv32gcv.cpp
@@ -85393,9 +85393,8 @@ template <typename ARCH>
 continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, jit_holder& jh) {
     enum {TRAP_ID=1<<16};
     code_word_t instr = 0;
-    phys_addr_t paddr(pc);
     auto *const data = (uint8_t *)&instr;
-    auto res = this->core.read(paddr, 4, data);
+    auto res = this->core.read({address_type::LOGICAL, access_type::DEBUG_READ, arch::traits<ARCH>::IMEM, pc.val}, 4, data);
     if (res != iss::Ok)
         return ILLEGAL_FETCH;
     if (instr == 0x0000006f || (instr&0xffff)==0xa001)
diff --git a/src/vm/asmjit/vm_rv32i.cpp b/src/vm/asmjit/vm_rv32i.cpp
index 8841d85..3788601 100644
--- a/src/vm/asmjit/vm_rv32i.cpp
+++ b/src/vm/asmjit/vm_rv32i.cpp
@@ -2829,9 +2829,8 @@ template <typename ARCH>
 continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, jit_holder& jh) {
     enum {TRAP_ID=1<<16};
     code_word_t instr = 0;
-    phys_addr_t paddr(pc);
     auto *const data = (uint8_t *)&instr;
-    auto res = this->core.read(paddr, 4, data);
+    auto res = this->core.read({address_type::LOGICAL, access_type::DEBUG_READ, arch::traits<ARCH>::IMEM, pc.val}, 4, data);
     if (res != iss::Ok)
         return ILLEGAL_FETCH;
     if (instr == 0x0000006f || (instr&0xffff)==0xa001)
diff --git a/src/vm/asmjit/vm_rv32imac.cpp b/src/vm/asmjit/vm_rv32imac.cpp
index ef5fd9e..11de413 100644
--- a/src/vm/asmjit/vm_rv32imac.cpp
+++ b/src/vm/asmjit/vm_rv32imac.cpp
@@ -5429,9 +5429,8 @@ template <typename ARCH>
 continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, jit_holder& jh) {
     enum {TRAP_ID=1<<16};
     code_word_t instr = 0;
-    phys_addr_t paddr(pc);
     auto *const data = (uint8_t *)&instr;
-    auto res = this->core.read(paddr, 4, data);
+    auto res = this->core.read({address_type::LOGICAL, access_type::DEBUG_READ, arch::traits<ARCH>::IMEM, pc.val}, 4, data);
     if (res != iss::Ok)
         return ILLEGAL_FETCH;
     if (instr == 0x0000006f || (instr&0xffff)==0xa001)
diff --git a/src/vm/asmjit/vm_rv64gc.cpp b/src/vm/asmjit/vm_rv64gc.cpp
index 153be17..7e74b61 100644
--- a/src/vm/asmjit/vm_rv64gc.cpp
+++ b/src/vm/asmjit/vm_rv64gc.cpp
@@ -12567,9 +12567,8 @@ template <typename ARCH>
 continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, jit_holder& jh) {
     enum {TRAP_ID=1<<16};
     code_word_t instr = 0;
-    phys_addr_t paddr(pc);
     auto *const data = (uint8_t *)&instr;
-    auto res = this->core.read(paddr, 4, data);
+    auto res = this->core.read({address_type::LOGICAL, access_type::DEBUG_READ, arch::traits<ARCH>::IMEM, pc.val}, 4, data);
     if (res != iss::Ok)
         return ILLEGAL_FETCH;
     if (instr == 0x0000006f || (instr&0xffff)==0xa001)
diff --git a/src/vm/asmjit/vm_rv64gcv.cpp b/src/vm/asmjit/vm_rv64gcv.cpp
index 912d3a2..1e7e94c 100644
--- a/src/vm/asmjit/vm_rv64gcv.cpp
+++ b/src/vm/asmjit/vm_rv64gcv.cpp
@@ -87974,9 +87974,8 @@ template <typename ARCH>
 continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, jit_holder& jh) {
     enum {TRAP_ID=1<<16};
     code_word_t instr = 0;
-    phys_addr_t paddr(pc);
     auto *const data = (uint8_t *)&instr;
-    auto res = this->core.read(paddr, 4, data);
+    auto res = this->core.read({address_type::LOGICAL, access_type::DEBUG_READ, arch::traits<ARCH>::IMEM, pc.val}, 4, data);
     if (res != iss::Ok)
         return ILLEGAL_FETCH;
     if (instr == 0x0000006f || (instr&0xffff)==0xa001)
diff --git a/src/vm/asmjit/vm_rv64i.cpp b/src/vm/asmjit/vm_rv64i.cpp
index 523cb5e..9374dc8 100644
--- a/src/vm/asmjit/vm_rv64i.cpp
+++ b/src/vm/asmjit/vm_rv64i.cpp
@@ -3484,9 +3484,8 @@ template <typename ARCH>
 continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, jit_holder& jh) {
     enum {TRAP_ID=1<<16};
     code_word_t instr = 0;
-    phys_addr_t paddr(pc);
     auto *const data = (uint8_t *)&instr;
-    auto res = this->core.read(paddr, 4, data);
+    auto res = this->core.read({address_type::LOGICAL, access_type::DEBUG_READ, arch::traits<ARCH>::IMEM, pc.val}, 4, data);
     if (res != iss::Ok)
         return ILLEGAL_FETCH;
     if (instr == 0x0000006f || (instr&0xffff)==0xa001)
diff --git a/src/vm/asmjit/vm_tgc5c.cpp b/src/vm/asmjit/vm_tgc5c.cpp
index 0f0ff20..7ba7ec1 100644
--- a/src/vm/asmjit/vm_tgc5c.cpp
+++ b/src/vm/asmjit/vm_tgc5c.cpp
@@ -4723,9 +4723,8 @@ template <typename ARCH>
 continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, jit_holder& jh) {
     enum {TRAP_ID=1<<16};
     code_word_t instr = 0;
-    phys_addr_t paddr(pc);
     auto *const data = (uint8_t *)&instr;
-    auto res = this->core.read(paddr, 4, data);
+    auto res = this->core.read({address_type::LOGICAL, access_type::DEBUG_READ, arch::traits<ARCH>::IMEM, pc.val}, 4, data);
     if (res != iss::Ok)
         return ILLEGAL_FETCH;
     if (instr == 0x0000006f || (instr&0xffff)==0xa001)
diff --git a/src/vm/interp/vm_rv32gc.cpp b/src/vm/interp/vm_rv32gc.cpp
index f03c301..5b405e8 100644
--- a/src/vm/interp/vm_rv32gc.cpp
+++ b/src/vm/interp/vm_rv32gc.cpp
@@ -359,7 +359,7 @@ template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
     decoder instr_decoder;
 
     iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
-        if (this->core.read(iss::address_type::PHYSICAL, pc.access, pc.space, pc.val, 4, data) != iss::Ok)
+        if (this->core.read({iss::address_type::LOGICAL, pc.access, arch::traits<ARCH>::IMEM, pc.val}, 4, data) != iss::Ok)
                     return iss::Err;
         return iss::Ok;
     }
diff --git a/src/vm/interp/vm_rv32gcv.cpp b/src/vm/interp/vm_rv32gcv.cpp
index 95c7ebf..c5e6994 100644
--- a/src/vm/interp/vm_rv32gcv.cpp
+++ b/src/vm/interp/vm_rv32gcv.cpp
@@ -1330,7 +1330,7 @@ template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
     decoder instr_decoder;
 
     iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
-        if (this->core.read(iss::address_type::PHYSICAL, pc.access, pc.space, pc.val, 4, data) != iss::Ok)
+        if (this->core.read({iss::address_type::LOGICAL, pc.access, arch::traits<ARCH>::IMEM, pc.val}, 4, data) != iss::Ok)
                     return iss::Err;
         return iss::Ok;
     }
diff --git a/src/vm/interp/vm_rv32i.cpp b/src/vm/interp/vm_rv32i.cpp
index cde4275..7447095 100644
--- a/src/vm/interp/vm_rv32i.cpp
+++ b/src/vm/interp/vm_rv32i.cpp
@@ -215,7 +215,7 @@ template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
     decoder instr_decoder;
 
     iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
-        if (this->core.read(iss::address_type::PHYSICAL, pc.access, pc.space, pc.val, 4, data) != iss::Ok)
+        if (this->core.read({iss::address_type::LOGICAL, pc.access, arch::traits<ARCH>::IMEM, pc.val}, 4, data) != iss::Ok)
                     return iss::Err;
         return iss::Ok;
     }
diff --git a/src/vm/interp/vm_rv32imac.cpp b/src/vm/interp/vm_rv32imac.cpp
index 1a09e34..ca29721 100644
--- a/src/vm/interp/vm_rv32imac.cpp
+++ b/src/vm/interp/vm_rv32imac.cpp
@@ -264,7 +264,7 @@ template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
     decoder instr_decoder;
 
     iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
-        if (this->core.read(iss::address_type::PHYSICAL, pc.access, pc.space, pc.val, 4, data) != iss::Ok)
+        if (this->core.read({iss::address_type::LOGICAL, pc.access, arch::traits<ARCH>::IMEM, pc.val}, 4, data) != iss::Ok)
                     return iss::Err;
         return iss::Ok;
     }
diff --git a/src/vm/interp/vm_rv64gc.cpp b/src/vm/interp/vm_rv64gc.cpp
index 641d3d0..ced250c 100644
--- a/src/vm/interp/vm_rv64gc.cpp
+++ b/src/vm/interp/vm_rv64gc.cpp
@@ -399,7 +399,7 @@ template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
     decoder instr_decoder;
 
     iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
-        if (this->core.read(iss::address_type::PHYSICAL, pc.access, pc.space, pc.val, 4, data) != iss::Ok)
+        if (this->core.read({iss::address_type::LOGICAL, pc.access, arch::traits<ARCH>::IMEM, pc.val}, 4, data) != iss::Ok)
                     return iss::Err;
         return iss::Ok;
     }
diff --git a/src/vm/interp/vm_rv64gcv.cpp b/src/vm/interp/vm_rv64gcv.cpp
index a930efe..efc747a 100644
--- a/src/vm/interp/vm_rv64gcv.cpp
+++ b/src/vm/interp/vm_rv64gcv.cpp
@@ -1370,7 +1370,7 @@ template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
     decoder instr_decoder;
 
     iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
-        if (this->core.read(iss::address_type::PHYSICAL, pc.access, pc.space, pc.val, 4, data) != iss::Ok)
+        if (this->core.read({iss::address_type::LOGICAL, pc.access, arch::traits<ARCH>::IMEM, pc.val}, 4, data) != iss::Ok)
                     return iss::Err;
         return iss::Ok;
     }
diff --git a/src/vm/interp/vm_rv64i.cpp b/src/vm/interp/vm_rv64i.cpp
index 828fdef..9ca2dc6 100644
--- a/src/vm/interp/vm_rv64i.cpp
+++ b/src/vm/interp/vm_rv64i.cpp
@@ -227,7 +227,7 @@ template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
     decoder instr_decoder;
 
     iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
-        if (this->core.read(iss::address_type::PHYSICAL, pc.access, pc.space, pc.val, 4, data) != iss::Ok)
+        if (this->core.read({iss::address_type::LOGICAL, pc.access, arch::traits<ARCH>::IMEM, pc.val}, 4, data) != iss::Ok)
                     return iss::Err;
         return iss::Ok;
     }
diff --git a/src/vm/interp/vm_tgc5c.cpp b/src/vm/interp/vm_tgc5c.cpp
index ea25afd..5bc85f8 100644
--- a/src/vm/interp/vm_tgc5c.cpp
+++ b/src/vm/interp/vm_tgc5c.cpp
@@ -253,7 +253,7 @@ template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
     decoder instr_decoder;
 
     iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
-        if (this->core.read(iss::address_type::PHYSICAL, pc.access, pc.space, pc.val, 4, data) != iss::Ok)
+        if (this->core.read({iss::address_type::LOGICAL, pc.access, arch::traits<ARCH>::IMEM, pc.val}, 4, data) != iss::Ok)
                     return iss::Err;
         return iss::Ok;
     }

From 18d477fa5c6bf1c6fdc52112a962b82067efe043 Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Sat, 22 Nov 2025 16:53:27 +0100
Subject: [PATCH 32/77] adapts core2sc_adapter to use addr_t

---
 src/sysc/core2sc_adapter.h | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/sysc/core2sc_adapter.h b/src/sysc/core2sc_adapter.h
index 71b17eb..c295042 100644
--- a/src/sysc/core2sc_adapter.h
+++ b/src/sysc/core2sc_adapter.h
@@ -147,18 +147,18 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
                                    .wr_mem{util::delegate<iss::mem::wr_mem_func_sig>::from<this_class, &this_class::write_mem>(this)}};
     }
 
-    iss::status read_mem(iss::access_type access, uint32_t space, uint64_t addr, unsigned length, uint8_t* data) {
-        if(access && iss::access_type::DEBUG)
-            return owner->read_mem_dbg(addr, length, data) ? iss::Ok : iss::Err;
+    iss::status read_mem(const iss::addr_t& addr, unsigned length, uint8_t* data) {
+        if(iss::is_debug(addr.access))
+            return owner->read_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
         else {
-            return owner->read_mem(addr, length, data, is_fetch(access)) ? iss::Ok : iss::Err;
+            return owner->read_mem(addr.val, length, data, is_fetch(addr.access)) ? iss::Ok : iss::Err;
         }
     }
 
-    iss::status write_mem(iss::access_type access, uint32_t space, uint64_t addr, unsigned length, uint8_t const* data) {
-        if(access && iss::access_type::DEBUG)
-            return owner->write_mem_dbg(addr, length, data) ? iss::Ok : iss::Err;
-        if(addr == this->tohost) {
+    iss::status write_mem(const iss::addr_t& addr_, unsigned length, uint8_t const* data) {
+        if(iss::is_debug(addr.access))
+            return owner->write_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
+        if(addr.val == this->tohost) {
             reg_t cur_data = *reinterpret_cast<const reg_t*>(data);
             // Extract Device (bits 63:56)
             uint8_t device = sizeof(reg_t) == 4 ? 0 : (cur_data >> 56) & 0xFF;
@@ -201,7 +201,7 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
             this->interrupt_sim = payload_addr;
             return iss::Ok;
         }
-        auto res = owner->write_mem(addr, length, data) ? iss::Ok : iss::Err;
+        auto res = owner->write_mem(addr.val, length, data) ? iss::Ok : iss::Err;
         return res;
     }
 

From 0585ee655eb0b0aa600b3a0f0cdf272731b536a6 Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Sat, 22 Nov 2025 16:59:25 +0100
Subject: [PATCH 33/77] corrects typo that inhibits building

---
 src/sysc/core2sc_adapter.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/sysc/core2sc_adapter.h b/src/sysc/core2sc_adapter.h
index c295042..0f2c7dc 100644
--- a/src/sysc/core2sc_adapter.h
+++ b/src/sysc/core2sc_adapter.h
@@ -155,7 +155,7 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
         }
     }
 
-    iss::status write_mem(const iss::addr_t& addr_, unsigned length, uint8_t const* data) {
+    iss::status write_mem(const iss::addr_t& addr, unsigned length, uint8_t const* data) {
         if(iss::is_debug(addr.access))
             return owner->write_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
         if(addr.val == this->tohost) {

From 19f3737bd0db02721ca2616580d19a193910a8a4 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Mon, 24 Nov 2025 08:40:22 +0100
Subject: [PATCH 34/77] fixes zlib version conflict when using LLVM

---
 conanfile.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/conanfile.py b/conanfile.py
index 76ba146..cb2240e 100644
--- a/conanfile.py
+++ b/conanfile.py
@@ -43,7 +43,7 @@ def requirements(self):
         self.requires("lz4/1.9.3")
         self.requires("yaml-cpp/0.7.0")
         self.requires("jsoncpp/1.9.5")
-        self.requires("zlib/1.2.12")
+        self.requires("zlib/1.3.1")
         self.requires("asmjit/cci.20240531")
         if "WITH_LLVM" in os.environ:
             self.requires("llvm-core/19.1.7")

From 462d4eff5ce74f4427edca16a213f020e14521f5 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Mon, 24 Nov 2025 08:44:00 +0100
Subject: [PATCH 35/77] updates ci-compile.yml to include LLVM backend

---
 .github/workflows/ci-compile.yml | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/ci-compile.yml b/.github/workflows/ci-compile.yml
index b5971c4..eb04bc8 100644
--- a/.github/workflows/ci-compile.yml
+++ b/.github/workflows/ci-compile.yml
@@ -40,10 +40,14 @@ jobs:
           cmake --version
 
       - name: Configure
-        run: cmake --preset Debug -B build -DCMAKE_CXX_STANDARD=${{ matrix.cpp_std }}
+        run: |
+          echo "WITH_LLVM=1" >> $GITHUB_ENV
+          cmake --preset Debug -B build -DCMAKE_CXX_STANDARD=${{ matrix.cpp_std }}
 
       - name: Build
-        run: cmake --build build -j
+        run: |
+          echo "WITH_LLVM=1" >> $GITHUB_ENV
+          cmake --build build -j
 
       - name: Run smoke test
         run: ./build/riscv-sim -h

From 366f6664d9f9eb94d5a1332fd7da2431fc497ad0 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Mon, 24 Nov 2025 08:52:07 +0100
Subject: [PATCH 36/77] adds missign cmake option in ci-compile.yml

---
 .github/workflows/ci-compile.yml | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/.github/workflows/ci-compile.yml b/.github/workflows/ci-compile.yml
index eb04bc8..b56ee4a 100644
--- a/.github/workflows/ci-compile.yml
+++ b/.github/workflows/ci-compile.yml
@@ -40,14 +40,10 @@ jobs:
           cmake --version
 
       - name: Configure
-        run: |
-          echo "WITH_LLVM=1" >> $GITHUB_ENV
-          cmake --preset Debug -B build -DCMAKE_CXX_STANDARD=${{ matrix.cpp_std }}
+        run: WITH_LLVM=1 cmake --preset Debug -B build -DCMAKE_CXX_STANDARD=${{ matrix.cpp_std }} WITH_LLVM=ON
 
       - name: Build
-        run: |
-          echo "WITH_LLVM=1" >> $GITHUB_ENV
-          cmake --build build -j
+        run: WITH_LLVM=1 cmake --build build -j
 
       - name: Run smoke test
         run: ./build/riscv-sim -h

From d6cc81e065743fa85f49b8e8d9351c017c554742 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Mon, 24 Nov 2025 09:43:26 +0100
Subject: [PATCH 37/77] fixes cmake CLI syntax in ci-compile.yml

---
 .github/workflows/ci-compile.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/ci-compile.yml b/.github/workflows/ci-compile.yml
index b56ee4a..5daa727 100644
--- a/.github/workflows/ci-compile.yml
+++ b/.github/workflows/ci-compile.yml
@@ -40,7 +40,7 @@ jobs:
           cmake --version
 
       - name: Configure
-        run: WITH_LLVM=1 cmake --preset Debug -B build -DCMAKE_CXX_STANDARD=${{ matrix.cpp_std }} WITH_LLVM=ON
+        run: WITH_LLVM=1 cmake --preset Debug -B build -DCMAKE_CXX_STANDARD=${{ matrix.cpp_std }} -DWITH_LLVM=ON
 
       - name: Build
         run: WITH_LLVM=1 cmake --build build -j

From 14bf9bf09760afe883f5a722ec38793ea5dee010 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Mon, 24 Nov 2025 09:44:26 +0100
Subject: [PATCH 38/77] changes build type type to Release in ci-compile.yml

---
 .github/workflows/ci-compile.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/ci-compile.yml b/.github/workflows/ci-compile.yml
index 5daa727..b053839 100644
--- a/.github/workflows/ci-compile.yml
+++ b/.github/workflows/ci-compile.yml
@@ -40,7 +40,7 @@ jobs:
           cmake --version
 
       - name: Configure
-        run: WITH_LLVM=1 cmake --preset Debug -B build -DCMAKE_CXX_STANDARD=${{ matrix.cpp_std }} -DWITH_LLVM=ON
+        run: WITH_LLVM=1 cmake --preset Release -B build -DCMAKE_CXX_STANDARD=${{ matrix.cpp_std }} -DWITH_LLVM=ON
 
       - name: Build
         run: WITH_LLVM=1 cmake --build build -j

From d49d14f9a9bcd90117f3e766c95e0fc4193e772c Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Mon, 24 Nov 2025 11:44:32 +0100
Subject: [PATCH 39/77] updates used version of dbt-rise-core

---
 .envrc                |  2 ++
 .vscode/settings.json | 15 +++++++++++----
 CMakeLists.txt        |  2 +-
 3 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/.envrc b/.envrc
index 65d6496..6934684 100644
--- a/.envrc
+++ b/.envrc
@@ -6,6 +6,8 @@ if [ $distro == "CentOS" ]; then
     . /opt/rh/rh-python38/enable
 elif [ $distro == "Rocky" ]; then
     . /opt/rh/gcc-toolset-11/enable
+elif [ $distro == "RockyLinux" ]; then
+    . /opt/rh/gcc-toolset-14/enable
 fi
 layout python3
 [ -f .envrc.$USER ] && . .envrc.$USER
diff --git a/.vscode/settings.json b/.vscode/settings.json
index fba823b..08558c4 100644
--- a/.vscode/settings.json
+++ b/.vscode/settings.json
@@ -4,9 +4,16 @@
         "workbench.action.tasks.runTask"
     ],
     "clangd.arguments": [
-    "--pretty",
-    "--background-index",
-    "--compile-commands-dir=${workspaceFolder}/build"
+        "--pretty",
+        "--background-index",
+        "--compile-commands-dir=${workspaceFolder}/build"
     ],
-    "cmake.copyCompileCommands": "${workspaceFolder}/build/compile_commands.json"
+    "cmake.copyCompileCommands": "${workspaceFolder}/build/compile_commands.json",
+    "editor.rulers": [
+        {
+            "column": 140,
+            "comment": "clang-format"
+        }
+    ],
+    "editor.formatOnSave": true
 }
\ No newline at end of file
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 0d242f7..8c674d5 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -20,7 +20,7 @@ if(NOT TARGET dbt-rise-core)
         dbt_rise_core_git
         GIT_REPOSITORY "https://github.com/Minres/DBT-RISE-Core.git"
         #GIT_TAG         "origin/develop"
-        GIT_TAG 874d3241
+        GIT_TAG cc0de2d
         GIT_SHALLOW OFF
         UPDATE_DISCONNECTED NOT ${UPDATE_EXTERNAL_PROJECT} # When enabled, this option causes the update step to be skipped.
     )

From a1bb6eca4fcd1f27c840e9436ab65d127575c6cf Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Wed, 26 Nov 2025 12:54:43 +0100
Subject: [PATCH 40/77] remoces tcc leftovers, disables asmjit by default to
 decrease build time

---
 CMakeLists.txt    | 16 ----------------
 CMakePresets.json |  4 ++--
 2 files changed, 2 insertions(+), 18 deletions(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 8c674d5..2cabe65 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -76,12 +76,6 @@ if(TARGET yaml-cpp::yaml-cpp)
     )
 endif()
 
-if(WITH_TCC)
-    list(APPEND LIB_SOURCES
-        src/vm/tcc/vm_tgc5c.cpp
-    )
-endif()
-
 if(WITH_LLVM)
     list(APPEND LIB_SOURCES
         src/vm/llvm/vm_tgc5c.cpp
@@ -127,11 +121,6 @@ if(IS_DIRECTORY "${PROJECT_SOURCE_DIR}/../dbt-rise-custom")
         list(APPEND LIB_SOURCES ${LLVM_GEN_SOURCES})
     endif()
 
-    if(WITH_TCC)
-        FILE(GLOB TCC_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/../dbt-rise-custom/src/vm/tcc/vm_*.cpp)
-        list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
-    endif()
-
     if(WITH_ASMJIT)
         FILE(GLOB TCC_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/../dbt-rise-custom/src/vm/asmjit/vm_*.cpp)
         list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
@@ -238,11 +227,6 @@ if(BUILD_TESTING)
     add_test(NAME riscv-sim-interp
         COMMAND riscv-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend interp)
 
-    if(WITH_TCC)
-        add_test(NAME riscv-sim-tcc
-            COMMAND riscv-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend tcc)
-    endif()
-
     if(WITH_LLVM)
         add_test(NAME riscv-sim-llvm
             COMMAND riscv-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend llvm)
diff --git a/CMakePresets.json b/CMakePresets.json
index 412e6ec..038bf0a 100644
--- a/CMakePresets.json
+++ b/CMakePresets.json
@@ -22,7 +22,7 @@
                 "CMAKE_PROJECT_TOP_LEVEL_INCLUDES": "contrib/cmake/conan_provider.cmake",
                 "CONAN_HOST_PROFILE": "auto-cmake",
                 "CONAN_BUILD_PROFILE": "conan_host_profile",
-                "WITH_TCC": "OFF"
+                "WITH_ASMJIT": "OFF"
             }
         },
         {
@@ -50,4 +50,4 @@
             }
         }
     ]
-}
+}
\ No newline at end of file

From 855d24dfe4d2e976ffd5f2baaff3e519fa5cef36 Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Wed, 26 Nov 2025 14:14:10 +0100
Subject: [PATCH 41/77] most minor change

---
 src/iss/arch/riscv_hart_m_p.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h
index af58e29..bea226b 100644
--- a/src/iss/arch/riscv_hart_m_p.h
+++ b/src/iss/arch/riscv_hart_m_p.h
@@ -163,7 +163,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const addr_t& a, const unsigned len
     auto& type = a.type;
 
 #ifndef NDEBUG
-    if(access && iss::access_type::DEBUG) {
+    if(is_debug(access)) {
         ILOG(isslogger, logging::TRACEALL, fmt::format("debug read of {} bytes @addr 0x{:x}", length, addr));
     } else if(is_fetch(access)) {
         ILOG(isslogger, logging::TRACEALL, fmt::format("fetch of {} bytes @addr 0x{:x}", length, addr));
@@ -248,7 +248,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const addr_t& a, const unsigned le
     auto& access = a.access;
     auto& type = a.type;
 #ifndef NDEBUG
-    const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
+    const char* prefix = (is_debug(access)) ? "debug " : "";
     switch(length) {
     case 8:
         ILOG(isslogger, logging::TRACEALL,

From 17d799d10d1bca5b0b226584168949ea27285337 Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Wed, 26 Nov 2025 14:14:52 +0100
Subject: [PATCH 42/77] corrects memory_with_htif turns out IMEM is a label
 with no corresponding memory declaration

---
 src/iss/mem/memory_with_htif.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/iss/mem/memory_with_htif.h b/src/iss/mem/memory_with_htif.h
index b0e9c2a..663180b 100644
--- a/src/iss/mem/memory_with_htif.h
+++ b/src/iss/mem/memory_with_htif.h
@@ -113,8 +113,7 @@ template <typename PLAT> struct neumann_memory_with_htif : public memory_elem {
     // have the largest possible size. Memory footprint should still be small as it
     // a sparse array
     using mem_type = util::sparse_array<uint8_t, arch::traits<PLAT>::max_mem_size>;
-    // We need one fewer memory as the IMEM maps to MEM in von Neumann architecture
-    std::array<mem_type, arch::traits<PLAT>::mem_sizes.size() - 1> memories{};
+    std::array<mem_type, arch::traits<PLAT>::mem_sizes.size()> memories{};
     arch::priv_if<reg_t> hart_if;
 };
 } // namespace mem

From fff0a7570563624218a02ba6cfa747b538d68219 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Thu, 27 Nov 2025 17:43:48 +0100
Subject: [PATCH 43/77] unifies singe- and multi-threaded core_complex

---
 CMakeLists.txt               |   3 +-
 src/main.cpp                 |   2 -
 src/sysc/core_complex.cpp    |  87 +++---
 src/sysc/core_complex.h      |  82 +++++-
 src/sysc/core_complex_mt.cpp | 522 -----------------------------------
 src/sysc/core_complex_mt.h   | 227 ---------------
 src/sysc/register_cores.cpp  |   8 +-
 7 files changed, 119 insertions(+), 812 deletions(-)
 delete mode 100644 src/sysc/core_complex_mt.cpp
 delete mode 100644 src/sysc/core_complex_mt.h

diff --git a/CMakeLists.txt b/CMakeLists.txt
index a29b664..02ab07d 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -120,7 +120,7 @@ if(IS_DIRECTORY "${PROJECT_SOURCE_DIR}/../dbt-rise-custom")
         list(APPEND LIB_DEFINES CORE_${CORE})
     endforeach()
 
-    message(STATUS "Core defines are ${LIB_DEFINES}")
+    #message(STATUS "Core defines are ${LIB_DEFINES}")
 
     if(WITH_LLVM)
         FILE(GLOB LLVM_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/../dbt-rise-custom/src/vm/llvm/vm_*.cpp)
@@ -261,7 +261,6 @@ if(TARGET scc-sysc)
     project(dbt-rise-riscv_sc VERSION 1.0.0)
     set(LIB_SOURCES
         src/sysc/core_complex.cpp
-        src/sysc/core_complex_mt.cpp
         src/sysc/register_cores.cpp
         src/sysc/register_rv32gcv.cpp
         src/sysc/register_rv64gcv.cpp
diff --git a/src/main.cpp b/src/main.cpp
index 1e03885..2f042ed 100644
--- a/src/main.cpp
+++ b/src/main.cpp
@@ -210,8 +210,6 @@ int main(int argc, char* argv[]) {
         }
         if(clim.count("disass")) {
             vm->setDisassEnabled(true);
-            LOGGER(disass)::set_reporting_level(logging::DEBUG);
-            auto lvl = LOGGER(disass)::get_reporting_level();
             LOGGER(disass)::print_time() = false;
             auto file_name = clim["disass"].as<std::string>();
             if(file_name.length() > 0) {
diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index 64182bc..6e3b5e3 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -39,6 +39,7 @@
 #include <iss/iss.h>
 #include <iss/vm_types.h>
 #include "iss_factory.h"
+#include "tlm/scc/quantum_keeper.h"
 #include <memory>
 #include <sstream>
 #include <tlm/scc/tlm_signal_gp.h>
@@ -84,9 +85,9 @@ iss::debugger::encoder_decoder encdec;
 std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
 } // namespace
 
-template <unsigned int BUSWIDTH>
-int core_complex<BUSWIDTH>::cmd_sysc(int argc, char* argv[], debugger::out_func of, debugger::data_func df,
-                                     debugger::target_adapter_if* tgt_adapter) {
+template <unsigned int BUSWIDTH, typename QK>
+int core_complex<BUSWIDTH, QK>::cmd_sysc(int argc, char* argv[], debugger::out_func of, debugger::data_func df,
+                                         debugger::target_adapter_if* tgt_adapter) {
     if(argc > 1) {
         if(strcasecmp(argv[1], "print_time") == 0) {
             std::string t = sc_time_stamp().to_string();
@@ -115,17 +116,15 @@ int core_complex<BUSWIDTH>::cmd_sysc(int argc, char* argv[], debugger::out_func
     return Err;
 }
 
-template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::reset(uint64_t addr) { vm->reset(addr); }
-template <unsigned int BUSWIDTH> inline void core_complex<BUSWIDTH>::start(bool dump) {
-    vm->start(std::numeric_limits<uint64_t>::max(), dump);
-}
-template <unsigned int BUSWIDTH> inline std::pair<uint64_t, bool> core_complex<BUSWIDTH>::load_file(std::string const& name) {
+template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::reset(uint64_t addr) { vm->reset(addr); }
+template <unsigned int BUSWIDTH, typename QK>
+inline std::pair<uint64_t, bool> core_complex<BUSWIDTH, QK>::load_file(std::string const& name) {
     iss::arch_if* cc = vm->get_arch();
     return cc->load_file(name);
 };
 
-template <unsigned int BUSWIDTH>
-void core_complex<BUSWIDTH>::create_cpu(std::string const& type, std::string const& backend, unsigned gdb_port, uint32_t hart_id) {
+template <unsigned int BUSWIDTH, typename QK>
+void core_complex<BUSWIDTH, QK>::create_cpu(std::string const& type, std::string const& backend, unsigned gdb_port, uint32_t hart_id) {
     auto& f = sysc::iss_factory::instance();
     if(type.size() == 0 || type == "?") {
         std::unordered_map<std::string, std::vector<std::string>> core_by_backend;
@@ -176,8 +175,8 @@ void core_complex<BUSWIDTH>::create_cpu(std::string const& type, std::string con
 }
 
 #ifndef CWR_SYSTEMC
-template <unsigned int BUSWIDTH>
-core_complex<BUSWIDTH>::core_complex(sc_module_name const& name)
+template <unsigned int BUSWIDTH, typename QK>
+core_complex<BUSWIDTH, QK>::core_complex(sc_module_name const& name)
 : sc_module(name)
 , fetch_lut(tlm_dmi_ext())
 , read_lut(tlm_dmi_ext())
@@ -186,7 +185,7 @@ core_complex<BUSWIDTH>::core_complex(sc_module_name const& name)
 }
 #endif
 
-template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::init() {
+template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::init() {
     ibus.register_invalidate_direct_mem_ptr([this](uint64_t start, uint64_t end) -> void {
         auto lut_entry = fetch_lut.getEntry(start);
         if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
@@ -204,7 +203,7 @@ template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::init() {
         }
     });
 
-    SC_HAS_PROCESS(core_complex<BUSWIDTH>); // NOLINT
+    SC_HAS_PROCESS(this_class); // NOLINT
     SC_THREAD(run);
     SC_METHOD(rst_cb);
     sensitive << rst_i;
@@ -250,7 +249,7 @@ template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::init() {
 #endif
 }
 
-template <unsigned int BUSWIDTH> core_complex<BUSWIDTH>::~core_complex() {
+template <unsigned int BUSWIDTH, typename QK> core_complex<BUSWIDTH, QK>::~core_complex() {
     for(auto* p : plugin_list)
         delete p;
     if(post_run_stats.get_value()) {
@@ -261,9 +260,9 @@ template <unsigned int BUSWIDTH> core_complex<BUSWIDTH>::~core_complex() {
     }
 }
 
-template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::trace(sc_trace_file* trf) const {}
+template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::trace(sc_trace_file* trf) const {}
 
-template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::before_end_of_elaboration() {
+template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::before_end_of_elaboration() {
     auto& type = GET_PROP_VALUE(core_type);
     SCCDEBUG(SCMOD) << "instantiating core " << type << " with " << GET_PROP_VALUE(backend) << " backend";
     // cpu = scc::make_unique<core_wrapper>(this);
@@ -314,7 +313,7 @@ template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::before_end_of_elab
     }
 }
 
-template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::start_of_simulation() {
+template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::start_of_simulation() {
     // quantum_keeper.reset();
     if(GET_PROP_VALUE(elf_file).size() > 0) {
         auto file_names = util::split(GET_PROP_VALUE(elf_file), ',');
@@ -340,7 +339,7 @@ template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::start_of_simulatio
     }
 }
 
-template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::disass_output(uint64_t pc, std::string const& instr_str) {
+template <unsigned int BUSWIDTH, typename QK> bool core_complex<BUSWIDTH, QK>::disass_output(uint64_t pc, std::string const& instr_str) {
     if(trc.m_db == nullptr)
         return false;
     if(trc.tr_handle.is_active())
@@ -350,11 +349,11 @@ template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::disass_output(uint
     trc.tr_handle.record_attribute("INSTR", instr_str);
     trc.tr_handle.record_attribute("MODE", lvl[core->get_mode()]);
     trc.tr_handle.record_attribute("MSTATUS", core->get_state());
-    trc.tr_handle.record_attribute("LTIME_START", quantum_keeper.get_current_time().value() / 1000);
+    trc.tr_handle.record_attribute("LTIME_START", quantum_keeper.get_local_absolute_time().value() / 1000);
     return true;
 }
 
-template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::forward() {
+template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::forward() {
 #ifndef CWR_SYSTEMC
     set_clock_period(clk_i.read());
 #else
@@ -363,25 +362,25 @@ template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::forward() {
 #endif
 }
 
-template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::set_clock_period(sc_core::sc_time period) {
+template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::set_clock_period(sc_core::sc_time period) {
     curr_clk = period;
     if(period == SC_ZERO_TIME)
         core->set_interrupt_execution(true);
 }
 
-template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::rst_cb() {
+template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::rst_cb() {
     if(rst_i.read())
         core->set_interrupt_execution(true);
 }
 
 #ifndef USE_TLM_SIGNAL
-template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::sw_irq_cb() { core->local_irq(3, sw_irq_i.read()); }
+template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::sw_irq_cb() { core->local_irq(3, sw_irq_i.read()); }
 
-template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::timer_irq_cb() { core->local_irq(7, timer_irq_i.read()); }
+template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::timer_irq_cb() { core->local_irq(7, timer_irq_i.read()); }
 
-template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::ext_irq_cb() { core->local_irq(11, ext_irq_i.read()); }
+template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::ext_irq_cb() { core->local_irq(11, ext_irq_i.read()); }
 
-template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::local_irq_cb() {
+template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::local_irq_cb() {
     for(auto i = 0U; i < local_irq_i.size(); ++i) {
         if(local_irq_i[i].event()) {
             core->local_irq(16 + i, local_irq_i[i].read());
@@ -390,7 +389,7 @@ template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::local_irq_cb() {
 }
 #endif
 
-template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::run() {
+template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::run() {
     wait(SC_ZERO_TIME); // separate from elaboration phase
     do {
         wait(SC_ZERO_TIME);
@@ -403,12 +402,13 @@ template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::run() {
         }
         quantum_keeper.reset();
         core->set_interrupt_execution(false);
-        start(dump_ir);
+        run_iss();
     } while(!core->get_interrupt_execution());
     sc_stop();
 }
 
-template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) {
+template <unsigned int BUSWIDTH, typename QK>
+bool core_complex<BUSWIDTH, QK>::read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) {
     auto& dmi_lut = is_fetch ? fetch_lut : read_lut;
     auto lut_entry = dmi_lut.getEntry(addr);
     if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && (addr + length) <= (lut_entry.get_end_address() + 1)) {
@@ -435,15 +435,8 @@ template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::read_mem(uint64_t
         gp.set_data_length(length);
         gp.set_streaming_width(length);
         sc_time delay = quantum_keeper.get_local_time();
-        if(trc.m_db != nullptr && trc.tr_handle.is_valid()) {
-            if(is_fetch && trc.tr_handle.is_active()) {
-                trc.tr_handle.end_transaction();
-            }
-            auto preExt = new tlm::scc::scv::tlm_recording_extension(trc.tr_handle, this);
-            gp.set_extension(preExt);
-        }
         auto pre_delay = delay;
-        sckt->b_transport(gp, delay);
+        exec_b_transport(gp, delay, is_fetch);
         if(pre_delay > delay) {
             quantum_keeper.reset();
         } else {
@@ -464,7 +457,7 @@ template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::read_mem(uint64_t
             gp.set_command(tlm::TLM_READ_COMMAND);
             gp.set_address(addr);
             tlm_dmi_ext dmi_data;
-            if(sckt->get_direct_mem_ptr(gp, dmi_data)) {
+            if(exec_get_direct_mem_ptr(gp, dmi_data)) {
                 if(dmi_data.is_read_allowed() && (addr + length - 1) <= dmi_data.get_end_address())
                     dmi_lut.addEntry(dmi_data, dmi_data.get_start_address(), dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
             }
@@ -473,7 +466,8 @@ template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::read_mem(uint64_t
     }
 }
 
-template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::write_mem(uint64_t addr, unsigned length, const uint8_t* const data) {
+template <unsigned int BUSWIDTH, typename QK>
+bool core_complex<BUSWIDTH, QK>::write_mem(uint64_t addr, unsigned length, const uint8_t* const data) {
     auto lut_entry = write_lut.getEntry(addr);
     if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && (addr + length) <= (lut_entry.get_end_address() + 1)) {
         auto offset = addr - lut_entry.get_start_address();
@@ -502,7 +496,7 @@ template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::write_mem(uint64_t
             gp.set_extension(preExt);
         }
         auto pre_delay = delay;
-        dbus->b_transport(gp, delay);
+        exec_b_transport(gp, delay);
         if(pre_delay > delay)
             quantum_keeper.reset();
         else
@@ -518,7 +512,7 @@ template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::write_mem(uint64_t
             gp.set_command(tlm::TLM_READ_COMMAND);
             gp.set_address(addr);
             tlm_dmi_ext dmi_data;
-            if(dbus->get_direct_mem_ptr(gp, dmi_data)) {
+            if(exec_get_direct_mem_ptr(gp, dmi_data)) {
                 if(dmi_data.is_write_allowed() && (addr + length - 1) <= dmi_data.get_end_address())
                     write_lut.addEntry(dmi_data, dmi_data.get_start_address(),
                                        dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
@@ -528,7 +522,8 @@ template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::write_mem(uint64_t
     }
 }
 
-template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) {
+template <unsigned int BUSWIDTH, typename QK>
+bool core_complex<BUSWIDTH, QK>::read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) {
     tlm::tlm_generic_payload gp;
     gp.set_command(tlm::TLM_READ_COMMAND);
     gp.set_address(addr);
@@ -538,7 +533,8 @@ template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::read_mem_dbg(uint6
     return dbus->transport_dbg(gp) == length;
 }
 
-template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) {
+template <unsigned int BUSWIDTH, typename QK>
+bool core_complex<BUSWIDTH, QK>::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) {
     write_buf.resize(length);
     std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
     tlm::tlm_generic_payload gp;
@@ -553,6 +549,9 @@ template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::write_mem_dbg(uint
 template class core_complex<scc::LT>;
 template class core_complex<32>;
 template class core_complex<64>;
+template class core_complex<scc::LT, tlm::scc::quantumkeeper_mt>;
+template class core_complex<32, tlm::scc::quantumkeeper_mt>;
+template class core_complex<64, tlm::scc::quantumkeeper_mt>;
 
 } // namespace riscv
 } /* namespace sysc */
diff --git a/src/sysc/core_complex.h b/src/sysc/core_complex.h
index 0643f09..819754c 100644
--- a/src/sysc/core_complex.h
+++ b/src/sysc/core_complex.h
@@ -42,7 +42,9 @@
 #include <scc/tick2time.h>
 #include <scc/traceable.h>
 #include <scc/utilities.h>
+#include <sysc/kernel/sc_time.h>
 #include <tlm/scc/initiator_mixin.h>
+#include <tlm/scc/quantum_keeper.h>
 #include <tlm/scc/scv/tlm_rec_initiator_socket.h>
 #ifdef CWR_SYSTEMC
 #include <scmlinc/scml_property.h>
@@ -80,8 +82,11 @@ using irq_signal_t = tlm::scc::tlm_signal_bool_opt_in;
 using irq_signal_t = sc_core::sc_in<bool>;
 #endif
 
-template <unsigned int BUSWIDTH = scc::LT> class core_complex : public sc_core::sc_module, public scc::traceable, public core_complex_if {
+template <unsigned int BUSWIDTH = scc::LT, typename QK = tlm::scc::quantumkeeper>
+class core_complex : public sc_core::sc_module, public scc::traceable, public core_complex_if {
 public:
+    using this_class = core_complex<BUSWIDTH, QK>;
+
     tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<BUSWIDTH>> ibus{"ibus"};
 
     tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<BUSWIDTH>> dbus{"dbus"};
@@ -180,11 +185,12 @@ template <unsigned int BUSWIDTH = scc::LT> class core_complex : public sc_core::
 
     void sync(uint64_t cycle) override {
         auto core_inc = curr_clk * (cycle - last_sync_cycle);
-        quantum_keeper.inc(core_inc);
-        if(quantum_keeper.need_sync()) {
-            wait(quantum_keeper.get_local_time());
-            quantum_keeper.reset();
-        }
+        quantum_keeper.check_and_sync(core_inc);
+        // quantum_keeper.inc(core_inc);
+        // if(quantum_keeper.need_sync()) {
+        //     wait(quantum_keeper.get_local_time());
+        //     quantum_keeper.reset();
+        // }
         last_sync_cycle = cycle;
     }
 
@@ -206,14 +212,11 @@ template <unsigned int BUSWIDTH = scc::LT> class core_complex : public sc_core::
 
     void reset(uint64_t addr);
 
-    inline void start(bool dump = false);
-
     inline std::pair<uint64_t, bool> load_file(std::string const& name);
 
 protected:
     void create_cpu(std::string const& type, std::string const& backend, unsigned gdb_port, uint32_t hart_id);
     int cmd_sysc(int argc, char* argv[], iss::debugger::out_func, iss::debugger::data_func, iss::debugger::target_adapter_if*);
-
     void before_end_of_elaboration() override;
     void start_of_simulation() override;
     void forward();
@@ -225,16 +228,73 @@ template <unsigned int BUSWIDTH = scc::LT> class core_complex : public sc_core::
     void ext_irq_cb();
     void local_irq_cb();
 #endif
+    ///////////////////////////////////////////////////////////////////////////////
+    // multi-threaded function implementations
+    ///////////////////////////////////////////////////////////////////////////////
+    template <typename U = QK>
+    typename std::enable_if<std::is_same<U, tlm::scc::quantumkeeper_mt>::value>::type
+    exec_b_transport(tlm::tlm_generic_payload& gp, sc_core::sc_time& delay, bool is_fetch = false) {
+        quantum_keeper.execute_on_sysc([this, &gp, &delay, is_fetch]() {
+            if(trc.m_db != nullptr && trc.tr_handle.is_valid()) {
+                if(is_fetch && trc.tr_handle.is_active()) {
+                    trc.tr_handle.end_transaction();
+                }
+                auto preExt = new tlm::scc::scv::tlm_recording_extension(trc.tr_handle, this);
+                gp.set_extension(preExt);
+            }
+            dbus->b_transport(gp, delay);
+        });
+    }
+    template <typename U = QK>
+    typename std::enable_if<std::is_same<U, tlm::scc::quantumkeeper>::value, bool>::type
+    exec_get_direct_mem_ptr(tlm::tlm_generic_payload& gp, tlm::tlm_dmi& dmi_data) {
+        return dbus->get_direct_mem_ptr(gp, dmi_data);
+    }
+    template <typename U = QK> typename std::enable_if<std::is_same<U, tlm::scc::quantumkeeper_mt>::value>::type run_iss() {
+        core->setup_mt();
+        quantum_keeper.check_and_sync(sc_core::SC_ZERO_TIME);
+        quantum_keeper.run_thread([this]() {
+            vm->start(std::numeric_limits<uint64_t>::max(), dump_ir);
+            return quantum_keeper.get_local_absolute_time();
+        });
+    }
+    ///////////////////////////////////////////////////////////////////////////////
+    // single-threaded function implementations
+    ///////////////////////////////////////////////////////////////////////////////
+    template <typename U = QK>
+    typename std::enable_if<std::is_same<U, tlm::scc::quantumkeeper>::value>::type
+    exec_b_transport(tlm::tlm_generic_payload& gp, sc_core::sc_time& delay, bool is_fetch = false) {
+        if(trc.m_db != nullptr && trc.tr_handle.is_valid()) {
+            if(is_fetch && trc.tr_handle.is_active()) {
+                trc.tr_handle.end_transaction();
+            }
+            auto preExt = new tlm::scc::scv::tlm_recording_extension(trc.tr_handle, this);
+            gp.set_extension(preExt);
+        }
+        dbus->b_transport(gp, delay);
+    }
+    template <typename U = QK>
+    typename std::enable_if<std::is_same<U, tlm::scc::quantumkeeper_mt>::value, bool>::type
+    exec_get_direct_mem_ptr(tlm::tlm_generic_payload& gp, tlm::tlm_dmi& dmi_data) {
+        auto result = false;
+        quantum_keeper.execute_on_sysc([this, &gp, &dmi_data, &result]() { result = dbus->get_direct_mem_ptr(gp, dmi_data); });
+        return result;
+    }
+    template <typename U = QK> typename std::enable_if<std::is_same<U, tlm::scc::quantumkeeper>::value>::type run_iss() {
+        vm->start(std::numeric_limits<uint64_t>::max(), dump_ir);
+    }
+    ///////////////////////////////////////////////////////////////////////////////
+    //
+    ///////////////////////////////////////////////////////////////////////////////
     uint64_t last_sync_cycle = 0;
     util::range_lut<tlm_dmi_ext> fetch_lut, read_lut, write_lut;
-    tlm_utils::tlm_quantumkeeper quantum_keeper;
+    QK quantum_keeper;
     std::vector<uint8_t> write_buf;
     sc_core::sc_signal<sc_core::sc_time> curr_clk;
     uint64_t ibus_inc{0}, dbus_inc{0};
     std::unique_ptr<sc2core_if> core;
     std::unique_ptr<iss::vm_if> vm;
     iss::debugger::target_adapter_if* tgt_adapter{nullptr};
-
     struct {
         //! transaction recording database
         SCVNS scv_tr_db* m_db{nullptr};
diff --git a/src/sysc/core_complex_mt.cpp b/src/sysc/core_complex_mt.cpp
deleted file mode 100644
index 2f743eb..0000000
--- a/src/sysc/core_complex_mt.cpp
+++ /dev/null
@@ -1,522 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-
-// clang-format off
-#include "core_complex_mt.h"
-#include <future>
-#include <iss/debugger/gdb_session.h>
-#include <iss/debugger/encoderdecoder.h>
-#include <iss/debugger/server.h>
-#include <iss/debugger/target_adapter_if.h>
-#include <iss/iss.h>
-#include <iss/vm_types.h>
-#include "iss_factory.h"
-#include <memory>
-#include <sstream>
-#include <sysc/kernel/sc_time.h>
-#include <tlm/scc/tlm_signal_gp.h>
-#include <tlm_core/tlm_2/tlm_generic_payload/tlm_gp.h>
-#ifndef WIN32
-#include <iss/plugin/loader.h>
-#endif
-#include <scc/report.h>
-#include <util/ities.h>
-#include <array>
-#include <iss/plugin/cycle_estimate.h>
-#include <iss/plugin/instruction_count.h>
-#include <util/ities.h>
-// clang-format on
-
-#ifdef HAS_SCV
-#include <scv.h>
-#else
-#include <scv-tr.h>
-using namespace scv_tr;
-#endif
-
-#define GET_PROP_VALUE(P) P.get_value()
-
-#ifdef _MSC_VER
-// not #if defined(_WIN32) || defined(_WIN64) because we have strncasecmp in mingw
-#define strncasecmp _strnicmp
-#define strcasecmp _stricmp
-#endif
-
-namespace sysc {
-namespace riscv {
-using namespace std;
-using namespace iss;
-using namespace logging;
-using namespace sc_core;
-
-namespace {
-iss::debugger::encoder_decoder encdec;
-std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
-} // namespace
-
-template <unsigned int BUSWIDTH>
-int core_complex_mt<BUSWIDTH>::cmd_sysc(int argc, char* argv[], debugger::out_func of, debugger::data_func df,
-                                        debugger::target_adapter_if* tgt_adapter) {
-    if(argc > 1) {
-        if(strcasecmp(argv[1], "print_time") == 0) {
-            std::string t = sc_time_stamp().to_string();
-            of(t.c_str());
-            std::array<char, 64> buf;
-            encdec.enc_string(t.c_str(), buf.data(), 63);
-            df(buf.data());
-            return Ok;
-        } else if(strcasecmp(argv[1], "break") == 0) {
-            sc_time t;
-            if(argc == 4) {
-                t = scc::parse_from_string(argv[2], argv[3]);
-            } else if(argc == 3) {
-                t = scc::parse_from_string(argv[2]);
-            } else
-                return Err;
-            // no check needed as it is only called if debug server is active
-            tgt_adapter->add_break_condition([t]() -> unsigned {
-                SCCTRACE() << "Checking condition at " << sc_time_stamp();
-                return sc_time_stamp() >= t ? std::numeric_limits<unsigned>::max() : 0;
-            });
-            return Ok;
-        }
-        return Err;
-    }
-    return Err;
-}
-
-template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::reset(uint64_t addr) { vm->reset(addr); }
-
-template <unsigned int BUSWIDTH> inline std::pair<uint64_t, bool> core_complex_mt<BUSWIDTH>::load_file(std::string const& name) {
-    iss::arch_if* cc = vm->get_arch();
-    return cc->load_file(name);
-};
-
-template <unsigned int BUSWIDTH>
-void core_complex_mt<BUSWIDTH>::create_cpu(std::string const& type, std::string const& backend, unsigned gdb_port, uint32_t hart_id) {
-    auto& f = sysc::iss_factory::instance();
-    if(type.size() == 0 || type == "?") {
-        std::unordered_map<std::string, std::vector<std::string>> core_by_backend;
-        for(auto& e : f.get_names()) {
-            auto p = e.find(':');
-            assert(p != std::string::npos);
-            core_by_backend[e.substr(p + 1)].push_back(e.substr(0, p));
-        }
-        std::ostringstream os;
-        os << "Available implementations\n";
-        os << "=========================\n";
-        for(auto& e : core_by_backend) {
-            std::sort(std::begin(e.second), std::end(e.second));
-            if(os.str().size())
-                os << "\n";
-            os << "  backend " << e.first << ":\n  - " << util::join(e.second, "\n  - ");
-        }
-        SCCINFO(SCMOD) << "\n" << os.str();
-        sc_core::sc_stop();
-    } else if(type.find(':') == std::string::npos) {
-        std::tie(core, vm) = f.create(type + ":" + backend, gdb_port, this);
-    } else {
-        auto base_isa = type.substr(0, 5);
-        if(base_isa == "tgc5d" || base_isa == "tgc5e") {
-            std::tie(core, vm) = f.create(type + "_clic_pmp:" + backend, gdb_port, this);
-        } else {
-            std::tie(core, vm) = f.create(type + ":" + backend, gdb_port, this);
-        }
-    }
-    if(!core) {
-        if(type != "?")
-            SCCFATAL() << "Could not create cpu for isa " << type << " and backend " << backend;
-    } else if(!vm) {
-        if(type != "?")
-            SCCFATAL() << "Could not create vm for isa " << type << " and backend " << backend;
-    } else {
-        core->set_hartid(hart_id);
-        auto* srv = debugger::server<debugger::gdb_session>::get();
-        if(srv)
-            tgt_adapter = srv->get_target(0); // FIXME: add core_id
-        if(tgt_adapter)
-            tgt_adapter->add_custom_command({"sysc",
-                                             [this](int argc, char* argv[], debugger::out_func of, debugger::data_func df) -> int {
-                                                 return cmd_sysc(argc, argv, of, df, tgt_adapter);
-                                             },
-                                             "SystemC sub-commands: break <time>, print_time"});
-    }
-}
-
-template <unsigned int BUSWIDTH>
-core_complex_mt<BUSWIDTH>::core_complex_mt(sc_module_name const& name)
-: sc_module(name)
-, fetch_lut(tlm_dmi_ext())
-, read_lut(tlm_dmi_ext())
-, write_lut(tlm_dmi_ext()) {
-    init();
-}
-
-template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::init() {
-    ibus.register_invalidate_direct_mem_ptr([this](uint64_t start, uint64_t end) -> void {
-        auto lut_entry = fetch_lut.getEntry(start);
-        if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
-            fetch_lut.removeEntry(lut_entry);
-        }
-    });
-    dbus.register_invalidate_direct_mem_ptr([this](uint64_t start, uint64_t end) -> void {
-        auto lut_entry = read_lut.getEntry(start);
-        if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
-            read_lut.removeEntry(lut_entry);
-        }
-        lut_entry = write_lut.getEntry(start);
-        if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
-            write_lut.removeEntry(lut_entry);
-        }
-    });
-
-    SC_HAS_PROCESS(core_complex_mt<BUSWIDTH>); // NOLINT
-    SC_THREAD(run);
-    SC_METHOD(rst_cb);
-    sensitive << rst_i;
-#ifdef USE_TLM_SIGNAL
-    sw_irq_i.register_nb_transport([this](tlm::scc::tlm_signal_gp<bool>& gp, tlm::tlm_phase& p, sc_core::sc_time& t) {
-        cpu->local_irq(3, gp.get_value());
-        return tlm::TLM_COMPLETED;
-    });
-    timer_irq_i.register_nb_transport([this](tlm::scc::tlm_signal_gp<bool>& gp, tlm::tlm_phase& p, sc_core::sc_time& t) {
-        cpu->local_irq(7, gp.get_value());
-        return tlm::TLM_COMPLETED;
-    });
-    ext_irq_i.register_nb_transport([this](tlm::scc::tlm_signal_gp<bool>& gp, tlm::tlm_phase& p, sc_core::sc_time& t) {
-        cpu->local_irq(11, gp.get_value());
-        return tlm::TLM_COMPLETED;
-    });
-    for(auto i = 0U; i < local_irq_i.size(); ++i)
-        local_irq_i[i].register_nb_transport([this, i](tlm::scc::tlm_signal_gp<bool>& gp, tlm::tlm_phase& p, sc_core::sc_time& t) {
-            cpu->local_irq(16 + i, gp.get_value());
-            return tlm::TLM_COMPLETED;
-        });
-#else
-    SC_METHOD(sw_irq_cb);
-    sensitive << sw_irq_i;
-    SC_METHOD(timer_irq_cb);
-    sensitive << timer_irq_i;
-    SC_METHOD(ext_irq_cb);
-    sensitive << ext_irq_i;
-    SC_METHOD(local_irq_cb);
-    for(auto pin : local_irq_i)
-        sensitive << pin;
-#endif
-    trc.m_db = scv_tr_db::get_default_db();
-
-    SC_METHOD(forward);
-    sensitive << clk_i;
-    SC_THREAD(core_task_handler);
-}
-
-template <unsigned int BUSWIDTH> core_complex_mt<BUSWIDTH>::~core_complex_mt() {
-    for(auto* p : plugin_list)
-        delete p;
-}
-
-template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::trace(sc_trace_file* trf) const {}
-
-template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::before_end_of_elaboration() {
-    auto& type = GET_PROP_VALUE(core_type);
-    SCCDEBUG(SCMOD) << "instantiating core " << type << " with " << GET_PROP_VALUE(backend) << " backend";
-    // cpu = scc::make_unique<core_wrapper>(this);
-    create_cpu(type, GET_PROP_VALUE(backend), GET_PROP_VALUE(gdb_server_port), GET_PROP_VALUE(mhartid));
-    if(type == "?")
-        return;
-    if(!local_irq_num.is_default_value()) {
-        core->set_irq_count(16 + local_irq_num);
-    }
-    sc_assert(vm);
-    auto disass = GET_PROP_VALUE(enable_disass);
-    if(disass && trc.m_db)
-        SCCINFO(SCMOD) << "Disasssembly will only be in transaction trace database!";
-    vm->setDisassEnabled(disass || trc.m_db != nullptr);
-    if(GET_PROP_VALUE(plugins).length()) {
-        auto p = util::split(GET_PROP_VALUE(plugins), ';');
-        for(std::string const& opt_val : p) {
-            std::string plugin_name = opt_val;
-            std::string filename{"cycles.txt"};
-            std::size_t found = opt_val.find('=');
-            if(found != std::string::npos) {
-                plugin_name = opt_val.substr(0, found);
-                filename = opt_val.substr(found + 1, opt_val.size());
-            }
-            if(plugin_name == "ic") {
-                auto* plugin = new iss::plugin::instruction_count(filename);
-                vm->register_plugin(*plugin);
-                plugin_list.push_back(plugin);
-            } else if(plugin_name == "ce") {
-                auto* plugin = new iss::plugin::cycle_estimate(filename);
-                vm->register_plugin(*plugin);
-                plugin_list.push_back(plugin);
-            } else {
-#ifndef WIN32
-                std::array<char const*, 1> a{{filename.c_str()}};
-                iss::plugin::loader l(plugin_name, {{"initPlugin"}});
-                auto* plugin = l.call_function<iss::vm_plugin*>("initPlugin", a.size(), a.data());
-                if(plugin) {
-                    vm->register_plugin(*plugin);
-                    plugin_list.push_back(plugin);
-                } else
-#endif
-                    SCCERR(SCMOD) << "Unknown plugin '" << plugin_name << "' or plugin not found";
-            }
-        }
-    }
-}
-
-template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::start_of_simulation() {
-    // quantum_keeper.reset();
-    if(GET_PROP_VALUE(elf_file).size() > 0) {
-        auto file_names = util::split(GET_PROP_VALUE(elf_file), ',');
-        for(auto& s : file_names) {
-            std::pair<uint64_t, bool> load_result = load_file(s);
-            if(!std::get<1>(load_result)) {
-                SCCWARN(SCMOD) << "Could not load FW file " << s;
-            } else {
-                if(reset_address.is_default_value())
-                    reset_address.set_value(load_result.first);
-            }
-        }
-    }
-    if(trc.m_db != nullptr && trc.stream_handle == nullptr) {
-        string basename(this->name());
-        trc.stream_handle = new scv_tr_stream((basename + ".instr").c_str(), "TRANSACTOR", trc.m_db);
-        trc.instr_tr_handle = new scv_tr_generator<>("execute", *trc.stream_handle);
-    }
-}
-
-template <unsigned int BUSWIDTH> bool core_complex_mt<BUSWIDTH>::disass_output(uint64_t pc, std::string const& instr_str) {
-    if(trc.m_db == nullptr)
-        return false;
-    if(trc.tr_handle.is_active())
-        trc.tr_handle.end_transaction();
-    trc.tr_handle = trc.instr_tr_handle->begin_transaction();
-    trc.tr_handle.record_attribute("PC", pc);
-    trc.tr_handle.record_attribute("INSTR", instr_str);
-    trc.tr_handle.record_attribute("MODE", lvl[core->get_mode()]);
-    trc.tr_handle.record_attribute("MSTATUS", core->get_state());
-    trc.tr_handle.record_attribute("LTIME_START", quantum_keeper.get_local_absolute_time().value() / 1000);
-    return true;
-}
-
-template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::core_task_handler() {
-    std::packaged_task<bool()> task;
-    wait(SC_ZERO_TIME);
-    while(true) {
-        wait(core_tasks.data_event());
-        while(core_tasks.try_get(task))
-            task();
-    }
-}
-
-template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::forward() { set_clock_period(clk_i.read()); }
-
-template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::set_clock_period(sc_core::sc_time period) {
-    curr_clk = period;
-    if(period == SC_ZERO_TIME)
-        core->set_interrupt_execution(true);
-}
-
-template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::rst_cb() {
-    if(rst_i.read())
-        core->set_interrupt_execution(true);
-}
-
-#ifndef USE_TLM_SIGNAL
-template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::sw_irq_cb() { core->local_irq(3, sw_irq_i.read()); }
-
-template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::timer_irq_cb() { core->local_irq(7, timer_irq_i.read()); }
-
-template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::ext_irq_cb() { core->local_irq(11, ext_irq_i.read()); }
-
-template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::local_irq_cb() {
-    for(auto i = 0U; i < local_irq_i.size(); ++i) {
-        if(local_irq_i[i].event()) {
-            core->local_irq(16 + i, local_irq_i[i].read());
-        }
-    }
-}
-#endif
-
-template <unsigned int BUSWIDTH> void core_complex_mt<BUSWIDTH>::run() {
-    wait(SC_ZERO_TIME); // separate from elaboration phase
-    do {
-        wait(SC_ZERO_TIME);
-        if(rst_i.read()) {
-            reset(GET_PROP_VALUE(reset_address));
-            wait(rst_i.negedge_event());
-        }
-        while(curr_clk.read() == SC_ZERO_TIME) {
-            wait(curr_clk.value_changed_event());
-        }
-        quantum_keeper.reset();
-        core->set_interrupt_execution(false);
-        core->setup_mt();
-        core_executor.start([this]() {
-            vm->start(std::numeric_limits<uint64_t>::max(), dump_ir);
-            return sc_core::SC_ZERO_TIME; // TODO: need to return real time
-        });
-        wait(core_executor.thread_finish_event());
-    } while(!core->get_interrupt_execution());
-    sc_stop();
-}
-
-template <unsigned int BUSWIDTH>
-bool core_complex_mt<BUSWIDTH>::read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) {
-    auto& dmi_lut = is_fetch ? fetch_lut : read_lut;
-    auto lut_entry = dmi_lut.getEntry(addr);
-    if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && (addr + length) <= (lut_entry.get_end_address() + 1)) {
-        auto offset = addr - lut_entry.get_start_address();
-        std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data);
-        if(is_fetch)
-            ibus_inc += lut_entry.get_read_latency() / curr_clk;
-        else
-            dbus_inc += lut_entry.get_read_latency() / curr_clk;
-        return true;
-    } else {
-        auto& sckt = is_fetch ? ibus : dbus;
-        tlm::tlm_generic_payload gp;
-        gp.set_command(tlm::TLM_READ_COMMAND);
-        gp.set_address(addr);
-        gp.set_data_ptr(data);
-        gp.set_data_length(length);
-        gp.set_streaming_width(length);
-        sc_time delay = quantum_keeper.get_local_time();
-        auto pre_delay = delay;
-        exec_b_transport(gp, delay, is_fetch);
-        if(pre_delay > delay) {
-            quantum_keeper.reset();
-        } else {
-            auto incr = (delay - pre_delay) / curr_clk;
-            if(is_fetch)
-                ibus_inc += incr;
-            else
-                dbus_inc += incr;
-        }
-        SCCTRACE(this->name()) << "[local time: " << delay << "]: finish read_mem(0x" << std::hex << addr << ") : 0x"
-                               << (length == 4   ? *(uint32_t*)data
-                                   : length == 2 ? *(uint16_t*)data
-                                                 : (unsigned)*data);
-        if(gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
-            return false;
-        }
-        if(gp.is_dmi_allowed() && !GET_PROP_VALUE(disable_dmi)) {
-            gp.set_command(tlm::TLM_READ_COMMAND);
-            gp.set_address(addr);
-            tlm_dmi_ext dmi_data;
-            if(exec_get_direct_mem_ptr(gp, dmi_data)) {
-                if(dmi_data.is_read_allowed() && (addr + length - 1) <= dmi_data.get_end_address())
-                    dmi_lut.addEntry(dmi_data, dmi_data.get_start_address(), dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
-            }
-        }
-        return true;
-    }
-}
-
-template <unsigned int BUSWIDTH> bool core_complex_mt<BUSWIDTH>::write_mem(uint64_t addr, unsigned length, const uint8_t* const data) {
-    auto lut_entry = write_lut.getEntry(addr);
-    if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && (addr + length) <= (lut_entry.get_end_address() + 1)) {
-        auto offset = addr - lut_entry.get_start_address();
-        std::copy(data, data + length, lut_entry.get_dmi_ptr() + offset);
-        dbus_inc += lut_entry.get_write_latency() / curr_clk;
-        return true;
-    } else {
-        write_buf.resize(length);
-        std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
-        tlm::tlm_generic_payload gp;
-        gp.set_command(tlm::TLM_WRITE_COMMAND);
-        gp.set_address(addr);
-        gp.set_data_ptr(write_buf.data());
-        gp.set_data_length(length);
-        gp.set_streaming_width(length);
-        sc_time delay = quantum_keeper.get_local_time();
-        if(trc.m_db != nullptr && trc.tr_handle.is_valid()) {
-            auto preExt = new tlm::scc::scv::tlm_recording_extension(trc.tr_handle, this);
-            gp.set_extension(preExt);
-        }
-        auto pre_delay = delay;
-        exec_b_transport(gp, delay);
-        if(pre_delay > delay)
-            quantum_keeper.reset();
-        else
-            dbus_inc += (delay - quantum_keeper.get_local_time()) / curr_clk;
-        SCCTRACE() << "[local time: " << delay << "]: finish write_mem(0x" << std::hex << addr << ") : 0x"
-                   << (length == 4   ? *(uint32_t*)data
-                       : length == 2 ? *(uint16_t*)data
-                                     : (unsigned)*data);
-        if(gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
-            return false;
-        }
-        if(gp.is_dmi_allowed() && !GET_PROP_VALUE(disable_dmi)) {
-            gp.set_command(tlm::TLM_READ_COMMAND);
-            gp.set_address(addr);
-            tlm_dmi_ext dmi_data;
-            if(exec_get_direct_mem_ptr(gp, dmi_data)) {
-                if(dmi_data.is_write_allowed() && (addr + length - 1) <= dmi_data.get_end_address())
-                    write_lut.addEntry(dmi_data, dmi_data.get_start_address(),
-                                       dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
-            }
-        }
-        return true;
-    }
-}
-
-template <unsigned int BUSWIDTH> bool core_complex_mt<BUSWIDTH>::read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) {
-    tlm::tlm_generic_payload gp;
-    gp.set_command(tlm::TLM_READ_COMMAND);
-    gp.set_address(addr);
-    gp.set_data_ptr(data);
-    gp.set_data_length(length);
-    gp.set_streaming_width(length);
-    return dbus->transport_dbg(gp) == length;
-}
-
-template <unsigned int BUSWIDTH> bool core_complex_mt<BUSWIDTH>::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) {
-    write_buf.resize(length);
-    std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
-    tlm::tlm_generic_payload gp;
-    gp.set_command(tlm::TLM_WRITE_COMMAND);
-    gp.set_address(addr);
-    gp.set_data_ptr(write_buf.data());
-    gp.set_data_length(length);
-    gp.set_streaming_width(length);
-    return dbus->transport_dbg(gp) == length;
-}
-
-template class core_complex_mt<scc::LT>;
-template class core_complex_mt<32>;
-template class core_complex_mt<64>;
-
-} // namespace riscv
-} /* namespace sysc */
diff --git a/src/sysc/core_complex_mt.h b/src/sysc/core_complex_mt.h
deleted file mode 100644
index 8726588..0000000
--- a/src/sysc/core_complex_mt.h
+++ /dev/null
@@ -1,227 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017-2021 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-
-#ifndef _SYSC_CORE_COMPLEX__MT_H_
-#define _SYSC_CORE_COMPLEX__MT_H_
-
-#include "core_complex_if.h"
-#include "sc2core_if.h"
-#include <cci_configuration>
-#include <future>
-#include <iss/debugger/target_adapter_if.h>
-#include <iss/debugger_if.h>
-#include <iss/vm_if.h>
-#include <scc/signal_opt_ports.h>
-#include <scc/tick2time.h>
-#include <scc/traceable.h>
-#include <scc/utilities.h>
-#include <tlm/scc/initiator_mixin.h>
-#include <tlm/scc/quantum_keeper.h>
-#include <tlm/scc/scv/tlm_rec_initiator_socket.h>
-#include <tlm_core/tlm_2/tlm_2_interfaces/tlm_dmi.h>
-#ifndef SC_SIGNAL_IF
-#include <tlm/scc/signal_target_mixin.h>
-#define USE_TLM_SIGNAL
-#endif
-#include <memory>
-#include <scc/async_queue.h>
-#include <scc/async_thread.h>
-#include <tlm>
-#include <tlm_utils/tlm_quantumkeeper.h>
-#include <util/range_lut.h>
-
-namespace iss {
-class vm_plugin;
-}
-namespace sysc {
-
-class tlm_dmi_ext : public tlm::tlm_dmi {
-public:
-    bool operator==(const tlm_dmi_ext& o) const {
-        return this->get_granted_access() == o.get_granted_access() && this->get_start_address() == o.get_start_address() &&
-               this->get_end_address() == o.get_end_address();
-    }
-
-    bool operator!=(const tlm_dmi_ext& o) const { return !operator==(o); }
-};
-
-namespace riscv {
-#ifdef USE_TLM_SIGNAL
-using irq_signal_t = tlm::scc::tlm_signal_bool_opt_in;
-#else
-using irq_signal_t = sc_core::sc_in<bool>;
-#endif
-
-template <unsigned int BUSWIDTH = scc::LT>
-class core_complex_mt : public sc_core::sc_module, public scc::traceable, public core_complex_if {
-public:
-    tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<BUSWIDTH>> ibus{"ibus"};
-
-    tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<BUSWIDTH>> dbus{"dbus"};
-
-    sc_core::sc_in<bool> rst_i{"rst_i"};
-
-    irq_signal_t ext_irq_i{"ext_irq_i"};
-
-    irq_signal_t timer_irq_i{"timer_irq_i"};
-
-    irq_signal_t sw_irq_i{"sw_irq_i"};
-
-    sc_core::sc_vector<irq_signal_t> local_irq_i{"local_irq_i", 16};
-
-    sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
-
-    cci::cci_param<std::string> elf_file{"elf_file", ""};
-
-    cci::cci_param<bool> enable_disass{"enable_disass", false};
-
-    cci::cci_param<bool> disable_dmi{"disable_dmi", false};
-
-    cci::cci_param<uint64_t> reset_address{"reset_address", 0ULL};
-
-    cci::cci_param<std::string> core_type{"core_type", "rv32imac_m"};
-
-    cci::cci_param<std::string> backend{"backend", "interp"};
-
-    cci::cci_param<unsigned short> gdb_server_port{"gdb_server_port", 0};
-
-    cci::cci_param<bool> dump_ir{"dump_ir", false};
-
-    cci::cci_param<uint32_t> mhartid{"mhartid", 0};
-
-    cci::cci_param<uint32_t> local_irq_num{"local_irq_num", 0};
-
-    cci::cci_param<std::string> plugins{"plugins", ""};
-
-    core_complex_mt(sc_core::sc_module_name const& name);
-
-    ~core_complex_mt();
-
-    unsigned get_last_bus_cycles() override {
-        auto mem_incr = std::max(ibus_inc, dbus_inc);
-        ibus_inc = dbus_inc = 0;
-        return mem_incr > 1 ? mem_incr : 1;
-    }
-
-    void sync(uint64_t cycle) override {
-        auto core_inc = curr_clk * (cycle - last_sync_cycle);
-        quantum_keeper.check_and_sync(core_inc);
-        last_sync_cycle = cycle;
-    }
-
-    bool read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) override;
-
-    bool write_mem(uint64_t addr, unsigned length, const uint8_t* const data) override;
-
-    bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) override;
-
-    bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) override;
-
-    void trace(sc_core::sc_trace_file* trf) const override;
-
-    bool disass_output(uint64_t pc, std::string const& instr) override;
-
-    void set_clock_period(sc_core::sc_time period);
-
-    char const* hier_name() override { return name(); }
-
-    void reset(uint64_t addr);
-
-    inline std::pair<uint64_t, bool> load_file(std::string const& name);
-
-protected:
-    void create_cpu(std::string const& type, std::string const& backend, unsigned gdb_port, uint32_t hart_id);
-    int cmd_sysc(int argc, char* argv[], iss::debugger::out_func, iss::debugger::data_func, iss::debugger::target_adapter_if*);
-    void before_end_of_elaboration() override;
-    void start_of_simulation() override;
-    void core_task_handler();
-    void forward();
-    void run();
-    void rst_cb();
-#ifndef USE_TLM_SIGNAL
-    void sw_irq_cb();
-    void timer_irq_cb();
-    void ext_irq_cb();
-    void local_irq_cb();
-#endif
-    void exec_b_transport(tlm::tlm_generic_payload& gp, sc_core::sc_time& delay, bool is_fetch = false) {
-        std::packaged_task<bool()> t([this, &gp, &delay, is_fetch]() {
-            if(trc.m_db != nullptr && trc.tr_handle.is_valid()) {
-                if(is_fetch && trc.tr_handle.is_active()) {
-                    trc.tr_handle.end_transaction();
-                }
-                auto preExt = new tlm::scc::scv::tlm_recording_extension(trc.tr_handle, this);
-                gp.set_extension(preExt);
-            }
-            dbus->b_transport(gp, delay);
-            return true;
-        });
-        std::future<bool> fu = t.get_future();
-        core_tasks.emplace(std::move(t));
-        fu.get();
-    }
-    bool exec_get_direct_mem_ptr(tlm::tlm_generic_payload& gp, tlm::tlm_dmi& dmi_data) {
-        std::packaged_task<bool()> t([this, &gp, &dmi_data]() { return dbus->get_direct_mem_ptr(gp, dmi_data); });
-        std::future<bool> fu = t.get_future();
-        core_tasks.emplace(std::move(t));
-        return fu.get();
-    }
-    uint64_t last_sync_cycle = 0;
-    util::range_lut<tlm_dmi_ext> fetch_lut, read_lut, write_lut;
-    tlm::scc::quantumkeeper_mt quantum_keeper;
-    std::vector<uint8_t> write_buf;
-    sc_core::sc_signal<sc_core::sc_time> curr_clk;
-    uint64_t ibus_inc{0}, dbus_inc{0};
-    std::unique_ptr<sc2core_if> core;
-    std::unique_ptr<iss::vm_if> vm;
-    iss::debugger::target_adapter_if* tgt_adapter{nullptr};
-    scc::async_queue<std::packaged_task<bool()>> core_tasks;
-    scc::async_thread core_executor;
-    struct {
-        //! transaction recording database
-        SCVNS scv_tr_db* m_db{nullptr};
-        //! blocking transaction recording stream handle
-        SCVNS scv_tr_stream* stream_handle{nullptr};
-        //! transaction generator handle for blocking transactions
-        SCVNS scv_tr_generator<SCVNS _scv_tr_generator_default_data, SCVNS _scv_tr_generator_default_data>* instr_tr_handle{nullptr};
-        SCVNS scv_tr_handle tr_handle;
-    } trc;
-    std::unique_ptr<scc::tick2time> t2t;
-
-private:
-    void init();
-    std::vector<iss::vm_plugin*> plugin_list;
-};
-} // namespace riscv
-} /* namespace sysc */
-
-#endif /* _SYSC_CORE_COMPLEX__MT_H_ */
diff --git a/src/sysc/register_cores.cpp b/src/sysc/register_cores.cpp
index eac7154..6e02119 100644
--- a/src/sysc/register_cores.cpp
+++ b/src/sysc/register_cores.cpp
@@ -124,15 +124,15 @@ volatile std::array<bool, 14> riscv_init = {
 namespace llvm {
 using namespace sysc;
 volatile std::array<bool, 4> riscv_init = {
-    iss_factory::instance().register_creator("rv32imc_m:llvm",
+    iss_factory::instance().register_creator("rv32imac_m:llvm",
                                              [](unsigned gdb_port, sysc::riscv::core_complex_if* cc) -> iss_factory::base_t {
                                                  auto* cpu = new core2sc_adapter<arch::riscv_hart_m_p<arch::rv32imc>>(cc);
-                                                 return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast<arch::rv32imc*>(cpu), gdb_port)}};
+                                                 return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast<arch::rv32imac*>(cpu), gdb_port)}};
                                              }),
-    iss_factory::instance().register_creator("rv32imc_mu:llvm",
+    iss_factory::instance().register_creator("rv32imac_mu:llvm",
                                              [](unsigned gdb_port, sysc::riscv::core_complex_if* cc) -> iss_factory::base_t {
                                                  auto* cpu = new core2sc_adapter<arch::riscv_hart_mu_p<arch::rv32imc>>(cc);
-                                                 return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast<arch::rv32imc*>(cpu), gdb_port)}};
+                                                 return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast<arch::rv32imac*>(cpu), gdb_port)}};
                                              }),
     iss_factory::instance().register_creator("tgc5c_m:llvm",
                                              [](unsigned gdb_port, sysc::riscv::core_complex_if* cc) -> iss_factory::base_t {

From dab4c69f59e0f33b979ac43b40a29d6ec5c67d68 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Fri, 28 Nov 2025 08:38:53 +0100
Subject: [PATCH 44/77] refactors instrcution tracing/disass to be mt save

---
 src/sysc/core2sc_adapter.h |  20 +++++--
 src/sysc/core_complex.cpp  |  32 ++--------
 src/sysc/core_complex.h    |  31 +++-------
 src/sysc/core_complex_if.h |   2 +-
 src/sysc/instr_recorder.h  | 116 +++++++++++++++++++++++++++++++++++++
 src/sysc/sc2core_if.h      |   1 +
 6 files changed, 146 insertions(+), 56 deletions(-)
 create mode 100644 src/sysc/instr_recorder.h

diff --git a/src/sysc/core2sc_adapter.h b/src/sysc/core2sc_adapter.h
index 4364cf8..3e80e26 100644
--- a/src/sysc/core2sc_adapter.h
+++ b/src/sysc/core2sc_adapter.h
@@ -75,9 +75,11 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
         this->register_csr_rd = util::delegate<void(unsigned, rd_csr_f)>::from<this_class, &this_class::_register_csr_rd>(this);
         this->register_csr_wr = util::delegate<void(unsigned, wr_csr_f)>::from<this_class, &this_class::_register_csr_wr>(this);
 
+        disass_delegate.log = util::delegate<util::LoggerDelegate::delegate_fn>(*this, &core2sc_adapter::disass);
+        disass_delegate.level = logging::log_level::INFO;
+        this->disasslogger.set_logger(disass_delegate);
         log_delegate.log = util::delegate<util::LoggerDelegate::delegate_fn>(*this, &core2sc_adapter::log);
         log_delegate.level = static_cast<logging::log_level>(scc::get_logging_level());
-        this->disasslogger.set_logger(log_delegate);
         this->isslogger.set_logger(log_delegate);
     }
 
@@ -95,6 +97,10 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
 
     virtual ~core2sc_adapter() {}
 
+    void enable_disass(bool enable) override {
+        this->disasslogger.set_log_level(enable ? logging::log_level::DEBUG : logging::log_level::INFO);
+    }
+
     void register_unknown_instr_handler(util::delegate<iss::arch_if::unknown_instr_cb_t> handler) override {
         PLAT::unknown_instr_cb = handler;
     };
@@ -150,11 +156,14 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
         }
     }
 
+    void disass(logging::log_level lvl, std::string const& msg_type, std::string const& msg, unsigned line, char const* file) {
+        ::scc ::ScLogger<::sc_core ::SC_INFO>(file, line, sc_core ::SC_HIGH).type(owner->hier_name()).get()
+            << "[" << msg_type << "] " << msg;
+    }
+
     void disass_output(uint64_t pc, std::string const& instr) {
-        static constexpr std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
-        if(!owner->disass_output(pc, instr)) {
-            PLAT::disass_output(pc, instr);
-        }
+        owner->disass_output(pc, instr);
+        PLAT::disass_output(pc, instr);
     };
 
     iss::mem::memory_if get_mem_if() {
@@ -335,6 +344,7 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
 
     sysc::riscv::core_complex_if* const owner{nullptr};
     util::LoggerDelegate log_delegate;
+    util::LoggerDelegate disass_delegate;
     sc_core::sc_event wfi_evt;
     unsigned to_host_wr_cnt = 0;
     bool first{true};
diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index 6e3b5e3..cf87058 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -236,7 +236,6 @@ template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::i
     for(auto pin : local_irq_i)
         sensitive << pin;
 #endif
-    trc.m_db = scv_tr_db::get_default_db();
 
     SC_METHOD(forward);
 #ifndef CWR_SYSTEMC
@@ -275,10 +274,11 @@ template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::b
     }
 #endif
     sc_assert(vm);
+    auto instr_trace = GET_PROP_VALUE(enable_instr_trace) ? trc.init(this->name()) : false;
     auto disass = GET_PROP_VALUE(enable_disass);
-    if(disass && trc.m_db)
-        SCCINFO(SCMOD) << "Disasssembly will only be in transaction trace database!";
-    vm->setDisassEnabled(disass || trc.m_db != nullptr);
+    if(disass)
+        core->enable_disass(true);
+    vm->setDisassEnabled(disass || instr_trace);
     if(GET_PROP_VALUE(plugins).length()) {
         auto p = util::split(GET_PROP_VALUE(plugins), ';');
         for(std::string const& opt_val : p) {
@@ -314,7 +314,6 @@ template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::b
 }
 
 template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::start_of_simulation() {
-    // quantum_keeper.reset();
     if(GET_PROP_VALUE(elf_file).size() > 0) {
         auto file_names = util::split(GET_PROP_VALUE(elf_file), ',');
         for(auto& s : file_names) {
@@ -332,25 +331,10 @@ template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::s
             }
         }
     }
-    if(trc.m_db != nullptr && trc.stream_handle == nullptr) {
-        string basename(this->name());
-        trc.stream_handle = new scv_tr_stream((basename + ".instr").c_str(), "TRANSACTOR", trc.m_db);
-        trc.instr_tr_handle = new scv_tr_generator<>("execute", *trc.stream_handle);
-    }
 }
 
-template <unsigned int BUSWIDTH, typename QK> bool core_complex<BUSWIDTH, QK>::disass_output(uint64_t pc, std::string const& instr_str) {
-    if(trc.m_db == nullptr)
-        return false;
-    if(trc.tr_handle.is_active())
-        trc.tr_handle.end_transaction();
-    trc.tr_handle = trc.instr_tr_handle->begin_transaction();
-    trc.tr_handle.record_attribute("PC", pc);
-    trc.tr_handle.record_attribute("INSTR", instr_str);
-    trc.tr_handle.record_attribute("MODE", lvl[core->get_mode()]);
-    trc.tr_handle.record_attribute("MSTATUS", core->get_state());
-    trc.tr_handle.record_attribute("LTIME_START", quantum_keeper.get_local_absolute_time().value() / 1000);
-    return true;
+template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::disass_output(uint64_t pc, std::string const& instr_str) {
+    trc.disass_output(pc, instr_str, lvl[core->get_mode()], core->get_state());
 }
 
 template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::forward() {
@@ -491,10 +475,6 @@ bool core_complex<BUSWIDTH, QK>::write_mem(uint64_t addr, unsigned length, const
         gp.set_data_length(length);
         gp.set_streaming_width(length);
         sc_time delay = quantum_keeper.get_local_time();
-        if(trc.m_db != nullptr && trc.tr_handle.is_valid()) {
-            auto preExt = new tlm::scc::scv::tlm_recording_extension(trc.tr_handle, this);
-            gp.set_extension(preExt);
-        }
         auto pre_delay = delay;
         exec_b_transport(gp, delay);
         if(pre_delay > delay)
diff --git a/src/sysc/core_complex.h b/src/sysc/core_complex.h
index 819754c..2e11900 100644
--- a/src/sysc/core_complex.h
+++ b/src/sysc/core_complex.h
@@ -34,6 +34,7 @@
 #define _SYSC_CORE_COMPLEX_H_
 
 #include "core_complex_if.h"
+#include "instr_recorder.h"
 #include "sc2core_if.h"
 #include <iss/debugger/target_adapter_if.h>
 #include <iss/debugger_if.h>
@@ -108,6 +109,8 @@ class core_complex : public sc_core::sc_module, public scc::traceable, public co
 
     cci::cci_param<bool> enable_disass{"enable_disass", false};
 
+    cci::cci_param<bool> enable_instr_trace{"enable_instr_trace", true};
+
     cci::cci_param<bool> disable_dmi{"disable_dmi", false};
 
     cci::cci_param<uint64_t> reset_address{"reset_address", 0ULL};
@@ -204,7 +207,7 @@ class core_complex : public sc_core::sc_module, public scc::traceable, public co
 
     void trace(sc_core::sc_trace_file* trf) const override;
 
-    bool disass_output(uint64_t pc, std::string const& instr) override;
+    void disass_output(uint64_t pc, std::string const& instr) override;
 
     void set_clock_period(sc_core::sc_time period);
 
@@ -235,13 +238,7 @@ class core_complex : public sc_core::sc_module, public scc::traceable, public co
     typename std::enable_if<std::is_same<U, tlm::scc::quantumkeeper_mt>::value>::type
     exec_b_transport(tlm::tlm_generic_payload& gp, sc_core::sc_time& delay, bool is_fetch = false) {
         quantum_keeper.execute_on_sysc([this, &gp, &delay, is_fetch]() {
-            if(trc.m_db != nullptr && trc.tr_handle.is_valid()) {
-                if(is_fetch && trc.tr_handle.is_active()) {
-                    trc.tr_handle.end_transaction();
-                }
-                auto preExt = new tlm::scc::scv::tlm_recording_extension(trc.tr_handle, this);
-                gp.set_extension(preExt);
-            }
+            gp.set_extension(trc.get_recording_extension(is_fetch));
             dbus->b_transport(gp, delay);
         });
     }
@@ -264,13 +261,7 @@ class core_complex : public sc_core::sc_module, public scc::traceable, public co
     template <typename U = QK>
     typename std::enable_if<std::is_same<U, tlm::scc::quantumkeeper>::value>::type
     exec_b_transport(tlm::tlm_generic_payload& gp, sc_core::sc_time& delay, bool is_fetch = false) {
-        if(trc.m_db != nullptr && trc.tr_handle.is_valid()) {
-            if(is_fetch && trc.tr_handle.is_active()) {
-                trc.tr_handle.end_transaction();
-            }
-            auto preExt = new tlm::scc::scv::tlm_recording_extension(trc.tr_handle, this);
-            gp.set_extension(preExt);
-        }
+        gp.set_extension(trc.get_recording_extension(is_fetch));
         dbus->b_transport(gp, delay);
     }
     template <typename U = QK>
@@ -295,15 +286,7 @@ class core_complex : public sc_core::sc_module, public scc::traceable, public co
     std::unique_ptr<sc2core_if> core;
     std::unique_ptr<iss::vm_if> vm;
     iss::debugger::target_adapter_if* tgt_adapter{nullptr};
-    struct {
-        //! transaction recording database
-        SCVNS scv_tr_db* m_db{nullptr};
-        //! blocking transaction recording stream handle
-        SCVNS scv_tr_stream* stream_handle{nullptr};
-        //! transaction generator handle for blocking transactions
-        SCVNS scv_tr_generator<SCVNS _scv_tr_generator_default_data, SCVNS _scv_tr_generator_default_data>* instr_tr_handle{nullptr};
-        SCVNS scv_tr_handle tr_handle;
-    } trc;
+    instr_recorder<QK> trc{quantum_keeper};
     std::unique_ptr<scc::tick2time> t2t;
 
 private:
diff --git a/src/sysc/core_complex_if.h b/src/sysc/core_complex_if.h
index 36b2fa9..d0a0286 100644
--- a/src/sysc/core_complex_if.h
+++ b/src/sysc/core_complex_if.h
@@ -49,7 +49,7 @@ struct core_complex_if {
 
     virtual bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) = 0;
 
-    virtual bool disass_output(uint64_t pc, std::string const& instr) = 0;
+    virtual void disass_output(uint64_t pc, std::string const& instr) = 0;
 
     virtual unsigned get_last_bus_cycles() = 0;
 
diff --git a/src/sysc/instr_recorder.h b/src/sysc/instr_recorder.h
new file mode 100644
index 0000000..af63326
--- /dev/null
+++ b/src/sysc/instr_recorder.h
@@ -0,0 +1,116 @@
+#pragma once
+
+#include "scv-tr/scv_tr.h"
+#include <rigtorp/SPSCQueue.h>
+#include <tlm/scc/quantum_keeper.h>
+#include <tlm/scc/scv/tlm_recording_extension.h>
+#ifdef HAS_SCV
+#include <scv.h>
+#else
+#include <scv-tr.h>
+#ifndef SCVNS
+#define SCVNS ::scv_tr::
+#endif
+#endif
+
+namespace sysc {
+namespace riscv {
+
+struct instr_recorder_b {
+    bool init(std::string const& basename) {
+        if(m_db != nullptr) {
+            stream_handle = new SCVNS scv_tr_stream((basename + ".instr").c_str(), "TRANSACTOR", m_db);
+            instr_tr_handle = new SCVNS scv_tr_generator<>("execute", *stream_handle);
+            return true;
+        }
+        return false;
+    }
+    instr_recorder_b(SCVNS scv_tr_db* m_db = SCVNS scv_tr_db::get_default_db())
+    : m_db(m_db) {}
+    void record_instr(uint64_t pc, std::string const& instr_str, char mode, uint64_t status, sc_core::sc_time ltime) {
+        if(stream_handle == nullptr)
+            return;
+        if(tr_handle.is_active())
+            tr_handle.end_transaction();
+        tr_handle = instr_tr_handle->begin_transaction();
+        tr_handle.record_attribute("PC", pc);
+        tr_handle.record_attribute("INSTR", instr_str);
+        tr_handle.record_attribute("MODE", mode);
+        tr_handle.record_attribute("MSTATUS", status);
+        tr_handle.record_attribute("LTIME_START", ltime / 1_ns);
+    }
+
+    tlm::scc::scv::tlm_recording_extension* get_recording_extension(bool finish_instr) {
+        if(m_db != nullptr && tr_handle.is_valid()) {
+            if(finish_instr && tr_handle.is_active())
+                tr_handle.end_transaction();
+            return new tlm::scc::scv::tlm_recording_extension(tr_handle, this);
+        }
+        return nullptr;
+    }
+
+protected:
+    //! transaction recording database
+    SCVNS scv_tr_db* m_db{nullptr};
+    //! blocking transaction recording stream handle
+    SCVNS scv_tr_stream* stream_handle{nullptr};
+    //! transaction generator handle for blocking transactions
+    SCVNS scv_tr_generator<SCVNS _scv_tr_generator_default_data, SCVNS _scv_tr_generator_default_data>* instr_tr_handle{nullptr};
+    SCVNS scv_tr_handle tr_handle;
+};
+
+template <typename QK> struct instr_recorder : instr_recorder_b {};
+
+template <> struct instr_recorder<tlm::scc::quantumkeeper> : instr_recorder_b {
+    void disass_output(uint64_t pc, std::string const& instr_str, char mode, uint64_t status) {
+        if(stream_handle == nullptr)
+            return;
+        record_instr(pc, instr_str, mode, status, quantum_keeper.get_local_absolute_time());
+    }
+    instr_recorder(tlm::scc::quantumkeeper& quantum_keeper)
+    : quantum_keeper(quantum_keeper) {}
+
+protected:
+    tlm::scc::quantumkeeper& quantum_keeper;
+};
+
+template <> struct instr_recorder<tlm::scc::quantumkeeper_mt> : instr_recorder_b {
+    void disass_output(uint64_t pc, std::string const& instr_str, char mode, uint64_t status) {
+        if(stream_handle == nullptr)
+            return;
+        que.push(instr_record{pc, instr_str, mode, status, quantum_keeper.get_local_absolute_time()});
+    }
+
+    void record() {
+        while(auto r = que.front()) {
+            record_instr(r->pc, r->instr_str, r->mode, r->status, r->start_time);
+            que.pop();
+        }
+    }
+
+    struct callback : sc_core::sc_stage_callback_if {
+        void stage_callback(const sc_core::sc_stage& stage) override { owner->record(); }
+        callback(instr_recorder<tlm::scc::quantumkeeper_mt>* owner)
+        : owner(owner) {}
+        instr_recorder<tlm::scc::quantumkeeper_mt>* owner;
+    } stage_cb{this};
+
+    instr_recorder(tlm::scc::quantumkeeper_mt& quantum_keeper)
+    : quantum_keeper(quantum_keeper)
+    , que(8 * 1024) {
+        sc_core::sc_register_stage_callback(stage_cb, sc_core::SC_PRE_TIMESTEP);
+    }
+
+protected:
+    struct instr_record {
+        uint64_t pc;
+        std::string const instr_str;
+        char mode;
+        uint64_t status;
+        sc_core::sc_time start_time;
+    };
+    tlm::scc::quantumkeeper_mt& quantum_keeper;
+    rigtorp::SPSCQueue<instr_record> que;
+};
+} // namespace riscv
+} // namespace sysc
\ No newline at end of file
diff --git a/src/sysc/sc2core_if.h b/src/sysc/sc2core_if.h
index 95709dc..44574ee 100644
--- a/src/sysc/sc2core_if.h
+++ b/src/sysc/sc2core_if.h
@@ -50,6 +50,7 @@ struct sc2core_if {
 
     virtual void setup_mt() = 0;
 
+    virtual void enable_disass(bool enable) = 0;
     util::delegate<void(unsigned)> set_hartid;
     util::delegate<void(unsigned)> set_irq_count;
     util::delegate<uint32_t()> get_mode;

From 39769b6d1fda6aa5fc22cb69c3e84246cb0a4443 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Sat, 29 Nov 2025 11:23:57 +0100
Subject: [PATCH 45/77] adds timed instruction recording

---
 src/sysc/instr_recorder.h | 60 +++++++++++++++++++++++----------------
 1 file changed, 35 insertions(+), 25 deletions(-)

diff --git a/src/sysc/instr_recorder.h b/src/sysc/instr_recorder.h
index af63326..57f269b 100644
--- a/src/sysc/instr_recorder.h
+++ b/src/sysc/instr_recorder.h
@@ -18,52 +18,62 @@ namespace riscv {
 
 struct instr_recorder_b {
     bool init(std::string const& basename) {
-        if(m_db != nullptr) {
-            stream_handle = new SCVNS scv_tr_stream((basename + ".instr").c_str(), "TRANSACTOR", m_db);
-            instr_tr_handle = new SCVNS scv_tr_generator<>("execute", *stream_handle);
+        if(tx_db != nullptr) {
+            stream_hnd = new SCVNS scv_tr_stream((basename + ".instr").c_str(), "TRANSACTOR", tx_db);
+            gen_hndl = new SCVNS scv_tr_generator<>("execute", *stream_hnd);
+            gen_timed_hndl = new SCVNS scv_tr_generator<>("execute(timed)", *stream_hnd);
             return true;
         }
         return false;
     }
-    instr_recorder_b(SCVNS scv_tr_db* m_db = SCVNS scv_tr_db::get_default_db())
-    : m_db(m_db) {}
+    instr_recorder_b(SCVNS scv_tr_db* tx_db = SCVNS scv_tr_db::get_default_db())
+    : tx_db(tx_db) {}
     void record_instr(uint64_t pc, std::string const& instr_str, char mode, uint64_t status, sc_core::sc_time ltime) {
-        if(stream_handle == nullptr)
-            return;
-        if(tr_handle.is_active())
-            tr_handle.end_transaction();
-        tr_handle = instr_tr_handle->begin_transaction();
-        tr_handle.record_attribute("PC", pc);
-        tr_handle.record_attribute("INSTR", instr_str);
-        tr_handle.record_attribute("MODE", mode);
-        tr_handle.record_attribute("MSTATUS", status);
-        tr_handle.record_attribute("LTIME_START", ltime / 1_ns);
+        tx_hndl = gen_hndl->begin_transaction();
+        tx_hndl.record_attribute("PC", pc);
+        tx_hndl.record_attribute("INSTR", instr_str);
+        tx_hndl.record_attribute("MODE", mode);
+        tx_hndl.record_attribute("MSTATUS", status);
+        tx_hndl.record_attribute("LTIME_START(ps)", static_cast<uint64_t>(ltime / 1_ps));
+        tx_hndl.end_transaction();
+        if(tx_timed_hndl.is_active())
+            gen_timed_hndl->end_transaction(tx_timed_hndl, ltime);
+        tx_timed_hndl = gen_timed_hndl->begin_transaction(ltime);
+        tx_timed_hndl.record_attribute("PC", pc);
+        tx_timed_hndl.record_attribute("INSTR", instr_str);
+        tx_timed_hndl.record_attribute("MODE", mode);
+        tx_timed_hndl.record_attribute("MSTATUS", status);
+        tx_timed_hndl.add_relation("PARENT/CHILD", tx_hndl);
     }
 
     tlm::scc::scv::tlm_recording_extension* get_recording_extension(bool finish_instr) {
-        if(m_db != nullptr && tr_handle.is_valid()) {
-            if(finish_instr && tr_handle.is_active())
-                tr_handle.end_transaction();
-            return new tlm::scc::scv::tlm_recording_extension(tr_handle, this);
+        if(tx_db != nullptr) {
+            if(tx_timed_hndl.is_valid()) {
+                return new tlm::scc::scv::tlm_recording_extension(tx_timed_hndl, this);
+            } else if(tx_hndl.is_valid()) {
+                return new tlm::scc::scv::tlm_recording_extension(tx_hndl, this);
+            }
         }
         return nullptr;
     }
 
 protected:
     //! transaction recording database
-    SCVNS scv_tr_db* m_db{nullptr};
+    SCVNS scv_tr_db* tx_db{nullptr};
     //! blocking transaction recording stream handle
-    SCVNS scv_tr_stream* stream_handle{nullptr};
+    SCVNS scv_tr_stream* stream_hnd{nullptr};
     //! transaction generator handle for blocking transactions
-    SCVNS scv_tr_generator<SCVNS _scv_tr_generator_default_data, SCVNS _scv_tr_generator_default_data>* instr_tr_handle{nullptr};
-    SCVNS scv_tr_handle tr_handle;
+    SCVNS scv_tr_generator<SCVNS _scv_tr_generator_default_data, SCVNS _scv_tr_generator_default_data>* gen_hndl{nullptr};
+    SCVNS scv_tr_generator<SCVNS _scv_tr_generator_default_data, SCVNS _scv_tr_generator_default_data>* gen_timed_hndl{nullptr};
+    SCVNS scv_tr_handle tx_hndl;
+    SCVNS scv_tr_handle tx_timed_hndl;
 };
 
 template <typename QK> struct instr_recorder : instr_recorder_b {};
 
 template <> struct instr_recorder<tlm::scc::quantumkeeper> : instr_recorder_b {
     void disass_output(uint64_t pc, std::string const& instr_str, char mode, uint64_t status) {
-        if(stream_handle == nullptr)
+        if(stream_hnd == nullptr)
             return;
         record_instr(pc, instr_str, mode, status, quantum_keeper.get_local_absolute_time());
     }
@@ -76,7 +86,7 @@ template <> struct instr_recorder<tlm::scc::quantumkeeper> : instr_recorder_b {
 
 template <> struct instr_recorder<tlm::scc::quantumkeeper_mt> : instr_recorder_b {
     void disass_output(uint64_t pc, std::string const& instr_str, char mode, uint64_t status) {
-        if(stream_handle == nullptr)
+        if(stream_hnd == nullptr)
             return;
         que.push(instr_record{pc, instr_str, mode, status, quantum_keeper.get_local_absolute_time()});
     }

From f22ac29eee996d1acd71e389873cd96009387a01 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Sat, 29 Nov 2025 11:24:48 +0100
Subject: [PATCH 46/77] fixes end of execution handling if cores shall be
 synced

---
 src/sysc/core_complex.cpp |  9 +++++++--
 src/sysc/core_complex.h   | 10 +++++++++-
 2 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index cf87058..14b1d6b 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -42,6 +42,7 @@
 #include "tlm/scc/quantum_keeper.h"
 #include <memory>
 #include <sstream>
+#include <sysc/kernel/sc_simcontext.h>
 #include <tlm/scc/tlm_signal_gp.h>
 #ifndef WIN32
 #include <iss/plugin/loader.h>
@@ -388,7 +389,12 @@ template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::r
         core->set_interrupt_execution(false);
         run_iss();
     } while(!core->get_interrupt_execution());
-    sc_stop();
+    if(finish_evt_inuse)
+        finish_evt.notify();
+    else {
+        if(sc_core::sc_get_simulator_status() != sc_core::SC_SIM_USER_STOP) // stop simulation
+            sc_stop();
+    }
 }
 
 template <unsigned int BUSWIDTH, typename QK>
@@ -411,7 +417,6 @@ bool core_complex<BUSWIDTH, QK>::read_mem(uint64_t addr, unsigned length, uint8_
 #endif
         return true;
     } else {
-        auto& sckt = is_fetch ? ibus : dbus;
         tlm::tlm_generic_payload gp;
         gp.set_command(tlm::TLM_READ_COMMAND);
         gp.set_address(addr);
diff --git a/src/sysc/core_complex.h b/src/sysc/core_complex.h
index 2e11900..aafa24f 100644
--- a/src/sysc/core_complex.h
+++ b/src/sysc/core_complex.h
@@ -217,6 +217,11 @@ class core_complex : public sc_core::sc_module, public scc::traceable, public co
 
     inline std::pair<uint64_t, bool> load_file(std::string const& name);
 
+    sc_core::sc_event const& get_finish_event() {
+        finish_evt_inuse = true;
+        return finish_evt;
+    }
+
 protected:
     void create_cpu(std::string const& type, std::string const& backend, unsigned gdb_port, uint32_t hart_id);
     int cmd_sysc(int argc, char* argv[], iss::debugger::out_func, iss::debugger::data_func, iss::debugger::target_adapter_if*);
@@ -261,8 +266,9 @@ class core_complex : public sc_core::sc_module, public scc::traceable, public co
     template <typename U = QK>
     typename std::enable_if<std::is_same<U, tlm::scc::quantumkeeper>::value>::type
     exec_b_transport(tlm::tlm_generic_payload& gp, sc_core::sc_time& delay, bool is_fetch = false) {
+        auto& sckt = is_fetch ? ibus : dbus;
         gp.set_extension(trc.get_recording_extension(is_fetch));
-        dbus->b_transport(gp, delay);
+        sckt->b_transport(gp, delay);
     }
     template <typename U = QK>
     typename std::enable_if<std::is_same<U, tlm::scc::quantumkeeper_mt>::value, bool>::type
@@ -288,6 +294,8 @@ class core_complex : public sc_core::sc_module, public scc::traceable, public co
     iss::debugger::target_adapter_if* tgt_adapter{nullptr};
     instr_recorder<QK> trc{quantum_keeper};
     std::unique_ptr<scc::tick2time> t2t;
+    sc_core::sc_event finish_evt{"finish_evt"};
+    bool finish_evt_inuse{false};
 
 private:
     void init();

From f6168176bdfb40826dac12f34f2b3bbe101cfb3f Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Mon, 24 Nov 2025 14:09:29 +0100
Subject: [PATCH 47/77] changes systemc interface wrt memory interaction
 functions to be inline with those used in the vm, namely handing around
 addr_t which includes  spaces

---
 src/sysc/core2sc_adapter.h | 11 ++++-----
 src/sysc/core_complex.cpp  | 46 +++++++++++++++++++-------------------
 src/sysc/core_complex.h    |  8 +++----
 src/sysc/core_complex_if.h |  9 ++++----
 4 files changed, 38 insertions(+), 36 deletions(-)

diff --git a/src/sysc/core2sc_adapter.h b/src/sysc/core2sc_adapter.h
index 3e80e26..754cc21 100644
--- a/src/sysc/core2sc_adapter.h
+++ b/src/sysc/core2sc_adapter.h
@@ -173,15 +173,15 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
 
     iss::status read_mem(const iss::addr_t& addr, unsigned length, uint8_t* data) {
         if(iss::is_debug(addr.access))
-            return owner->read_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
+            return owner->read_mem_dbg(addr, length, data) ? iss::Ok : iss::Err;
         else {
-            return owner->read_mem(addr.val, length, data, is_fetch(addr.access)) ? iss::Ok : iss::Err;
+            return owner->read_mem(addr, length, data) ? iss::Ok : iss::Err;
         }
     }
 
     iss::status write_mem(const iss::addr_t& addr, unsigned length, uint8_t const* data) {
         if(iss::is_debug(addr.access))
-            return owner->write_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
+            return owner->write_mem_dbg(addr, length, data) ? iss::Ok : iss::Err;
         if(addr.val == this->tohost) {
             reg_t cur_data = *reinterpret_cast<const reg_t*>(data);
             // Extract Device (bits 63:56)
@@ -204,7 +204,8 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
             }
             if(device == 0 && command == 0) {
                 std::array<uint64_t, 8> loaded_payload;
-                auto res = owner->read_mem(payload_addr, 8 * sizeof(uint64_t), reinterpret_cast<uint8_t*>(loaded_payload.data()), false)
+                auto res = owner->read_mem({addr.type, addr.access, addr.space, payload_addr}, 8 * sizeof(uint64_t),
+                                           reinterpret_cast<uint8_t*>(loaded_payload.data()))
                                ? iss::Ok
                                : iss::Err;
                 if(res == iss::Err) {
@@ -225,7 +226,7 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
             this->interrupt_sim = payload_addr;
             return iss::Ok;
         }
-        auto res = owner->write_mem(addr.val, length, data) ? iss::Ok : iss::Err;
+        auto res = owner->write_mem(addr, length, data) ? iss::Ok : iss::Err;
         return res;
     }
 
diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index 14b1d6b..de199b7 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -397,19 +397,19 @@ template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::r
     }
 }
 
-template <unsigned int BUSWIDTH, typename QK>
-bool core_complex<BUSWIDTH, QK>::read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) {
+template <unsigned int BUSWIDTH, typename QK> bool core_complex<BUSWIDTH, QK>::read_mem(addr_t addr, unsigned length, uint8_t* const data) {
+    bool is_fetch = addr.space == std::numeric_limits<decltype(addr.space)>::max() ? true : false;
     auto& dmi_lut = is_fetch ? fetch_lut : read_lut;
-    auto lut_entry = dmi_lut.getEntry(addr);
-    if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && (addr + length) <= (lut_entry.get_end_address() + 1)) {
-        auto offset = addr - lut_entry.get_start_address();
+    auto lut_entry = dmi_lut.getEntry(addr.val);
+    if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && (addr.val + length) <= (lut_entry.get_end_address() + 1)) {
+        auto offset = addr.val - lut_entry.get_start_address();
         std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data);
         if(is_fetch)
             ibus_inc += lut_entry.get_read_latency() / curr_clk;
         else
             dbus_inc += lut_entry.get_read_latency() / curr_clk;
 #ifndef NDEBUG
-        SCCTRACE(this->name()) << "[local time: " << quantum_keeper.get_local_time() << "]: finish dmi_read_mem(0x" << std::hex << addr
+        SCCTRACE(this->name()) << "[local time: " << quantum_keeper.get_local_time() << "]: finish dmi_read_mem(0x" << std::hex << addr.val
                                << ") : 0x"
                                << (length == 4   ? *(uint32_t*)data
                                    : length == 2 ? *(uint16_t*)data
@@ -419,7 +419,7 @@ bool core_complex<BUSWIDTH, QK>::read_mem(uint64_t addr, unsigned length, uint8_
     } else {
         tlm::tlm_generic_payload gp;
         gp.set_command(tlm::TLM_READ_COMMAND);
-        gp.set_address(addr);
+        gp.set_address(addr.val);
         gp.set_data_ptr(data);
         gp.set_data_length(length);
         gp.set_streaming_width(length);
@@ -435,7 +435,7 @@ bool core_complex<BUSWIDTH, QK>::read_mem(uint64_t addr, unsigned length, uint8_
             else
                 dbus_inc += incr;
         }
-        SCCTRACE(this->name()) << "[local time: " << delay << "]: finish read_mem(0x" << std::hex << addr << ") : 0x"
+        SCCTRACE(this->name()) << "[local time: " << delay << "]: finish read_mem(0x" << std::hex << addr.val << ") : 0x"
                                << (length == 4   ? *(uint32_t*)data
                                    : length == 2 ? *(uint16_t*)data
                                                  : (unsigned)*data);
@@ -444,10 +444,10 @@ bool core_complex<BUSWIDTH, QK>::read_mem(uint64_t addr, unsigned length, uint8_
         }
         if(gp.is_dmi_allowed() && !GET_PROP_VALUE(disable_dmi)) {
             gp.set_command(tlm::TLM_READ_COMMAND);
-            gp.set_address(addr);
+            gp.set_address(addr.val);
             tlm_dmi_ext dmi_data;
             if(exec_get_direct_mem_ptr(gp, dmi_data)) {
-                if(dmi_data.is_read_allowed() && (addr + length - 1) <= dmi_data.get_end_address())
+                if(dmi_data.is_read_allowed() && (addr.val + length - 1) <= dmi_data.get_end_address())
                     dmi_lut.addEntry(dmi_data, dmi_data.get_start_address(), dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
             }
         }
@@ -456,14 +456,14 @@ bool core_complex<BUSWIDTH, QK>::read_mem(uint64_t addr, unsigned length, uint8_
 }
 
 template <unsigned int BUSWIDTH, typename QK>
-bool core_complex<BUSWIDTH, QK>::write_mem(uint64_t addr, unsigned length, const uint8_t* const data) {
-    auto lut_entry = write_lut.getEntry(addr);
-    if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && (addr + length) <= (lut_entry.get_end_address() + 1)) {
-        auto offset = addr - lut_entry.get_start_address();
+bool core_complex<BUSWIDTH, QK>::write_mem(addr_t addr, unsigned length, const uint8_t* const data) {
+    auto lut_entry = write_lut.getEntry(addr.val);
+    if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && (addr.val + length) <= (lut_entry.get_end_address() + 1)) {
+        auto offset = addr.val - lut_entry.get_start_address();
         std::copy(data, data + length, lut_entry.get_dmi_ptr() + offset);
         dbus_inc += lut_entry.get_write_latency() / curr_clk;
 #ifndef NDEBUG
-        SCCTRACE(this->name()) << "[local time: " << quantum_keeper.get_local_time() << "]: finish dmi_write_mem(0x" << std::hex << addr
+        SCCTRACE(this->name()) << "[local time: " << quantum_keeper.get_local_time() << "]: finish dmi_write_mem(0x" << std::hex << addr.val
                                << ") : 0x"
                                << (length == 4   ? *(uint32_t*)data
                                    : length == 2 ? *(uint16_t*)data
@@ -475,7 +475,7 @@ bool core_complex<BUSWIDTH, QK>::write_mem(uint64_t addr, unsigned length, const
         std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
         tlm::tlm_generic_payload gp;
         gp.set_command(tlm::TLM_WRITE_COMMAND);
-        gp.set_address(addr);
+        gp.set_address(addr.val);
         gp.set_data_ptr(write_buf.data());
         gp.set_data_length(length);
         gp.set_streaming_width(length);
@@ -486,7 +486,7 @@ bool core_complex<BUSWIDTH, QK>::write_mem(uint64_t addr, unsigned length, const
             quantum_keeper.reset();
         else
             dbus_inc += (delay - quantum_keeper.get_local_time()) / curr_clk;
-        SCCTRACE(this->name()) << "[local time: " << delay << "]: finish write_mem(0x" << std::hex << addr << ") : 0x"
+        SCCTRACE(this->name()) << "[local time: " << delay << "]: finish write_mem(0x" << std::hex << addr.val << ") : 0x"
                                << (length == 4   ? *(uint32_t*)data
                                    : length == 2 ? *(uint16_t*)data
                                                  : (unsigned)*data);
@@ -495,10 +495,10 @@ bool core_complex<BUSWIDTH, QK>::write_mem(uint64_t addr, unsigned length, const
         }
         if(gp.is_dmi_allowed() && !GET_PROP_VALUE(disable_dmi)) {
             gp.set_command(tlm::TLM_READ_COMMAND);
-            gp.set_address(addr);
+            gp.set_address(addr.val);
             tlm_dmi_ext dmi_data;
             if(exec_get_direct_mem_ptr(gp, dmi_data)) {
-                if(dmi_data.is_write_allowed() && (addr + length - 1) <= dmi_data.get_end_address())
+                if(dmi_data.is_write_allowed() && (addr.val + length - 1) <= dmi_data.get_end_address())
                     write_lut.addEntry(dmi_data, dmi_data.get_start_address(),
                                        dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
             }
@@ -508,10 +508,10 @@ bool core_complex<BUSWIDTH, QK>::write_mem(uint64_t addr, unsigned length, const
 }
 
 template <unsigned int BUSWIDTH, typename QK>
-bool core_complex<BUSWIDTH, QK>::read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) {
+bool core_complex<BUSWIDTH, QK>::read_mem_dbg(addr_t addr, unsigned length, uint8_t* const data) {
     tlm::tlm_generic_payload gp;
     gp.set_command(tlm::TLM_READ_COMMAND);
-    gp.set_address(addr);
+    gp.set_address(addr.val);
     gp.set_data_ptr(data);
     gp.set_data_length(length);
     gp.set_streaming_width(length);
@@ -519,12 +519,12 @@ bool core_complex<BUSWIDTH, QK>::read_mem_dbg(uint64_t addr, unsigned length, ui
 }
 
 template <unsigned int BUSWIDTH, typename QK>
-bool core_complex<BUSWIDTH, QK>::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) {
+bool core_complex<BUSWIDTH, QK>::write_mem_dbg(addr_t addr, unsigned length, const uint8_t* const data) {
     write_buf.resize(length);
     std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
     tlm::tlm_generic_payload gp;
     gp.set_command(tlm::TLM_WRITE_COMMAND);
-    gp.set_address(addr);
+    gp.set_address(addr.val);
     gp.set_data_ptr(write_buf.data());
     gp.set_data_length(length);
     gp.set_streaming_width(length);
diff --git a/src/sysc/core_complex.h b/src/sysc/core_complex.h
index aafa24f..85c912e 100644
--- a/src/sysc/core_complex.h
+++ b/src/sysc/core_complex.h
@@ -197,13 +197,13 @@ class core_complex : public sc_core::sc_module, public scc::traceable, public co
         last_sync_cycle = cycle;
     }
 
-    bool read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) override;
+    bool read_mem(iss::addr_t a, unsigned length, uint8_t* const data) override;
 
-    bool write_mem(uint64_t addr, unsigned length, const uint8_t* const data) override;
+    bool write_mem(iss::addr_t a, unsigned length, const uint8_t* const data) override;
 
-    bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) override;
+    bool read_mem_dbg(iss::addr_t a, unsigned length, uint8_t* const data) override;
 
-    bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) override;
+    bool write_mem_dbg(iss::addr_t a, unsigned length, const uint8_t* const data) override;
 
     void trace(sc_core::sc_trace_file* trf) const override;
 
diff --git a/src/sysc/core_complex_if.h b/src/sysc/core_complex_if.h
index d0a0286..6657c3e 100644
--- a/src/sysc/core_complex_if.h
+++ b/src/sysc/core_complex_if.h
@@ -33,6 +33,7 @@
 #ifndef _SYSC_CORE_COMPLEX__IF_H_
 #define _SYSC_CORE_COMPLEX__IF_H_
 
+#include <iss/vm_types.h>
 #include <scc/signal_opt_ports.h>
 
 namespace sysc {
@@ -41,13 +42,13 @@ struct core_complex_if {
 
     virtual ~core_complex_if() = default;
 
-    virtual bool read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) = 0;
+    virtual bool read_mem(iss::addr_t addr, unsigned length, uint8_t* const data) = 0;
 
-    virtual bool write_mem(uint64_t addr, unsigned length, const uint8_t* const data) = 0;
+    virtual bool write_mem(iss::addr_t addr, unsigned length, const uint8_t* const data) = 0;
 
-    virtual bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) = 0;
+    virtual bool read_mem_dbg(iss::addr_t addr, unsigned length, uint8_t* const data) = 0;
 
-    virtual bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) = 0;
+    virtual bool write_mem_dbg(iss::addr_t addr, unsigned length, const uint8_t* const data) = 0;
 
     virtual void disass_output(uint64_t pc, std::string const& instr) = 0;
 

From 264c48dd88397abf0059091da4c5cae03259596d Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Tue, 25 Nov 2025 16:31:30 +0100
Subject: [PATCH 48/77] removes deprecated cores

---
 CMakeLists.txt           |   1 -
 src/iss/arch/rv32imc.cpp |  70 -----------
 src/iss/arch/rv32imc.h   | 263 ---------------------------------------
 3 files changed, 334 deletions(-)
 delete mode 100644 src/iss/arch/rv32imc.cpp
 delete mode 100644 src/iss/arch/rv32imc.h

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 08f183e..dfd4462 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -49,7 +49,6 @@ add_subdirectory(softvector)
 set(LIB_SOURCES
     src/iss/plugin/instruction_count.cpp
     src/iss/arch/rv32i.cpp
-    src/iss/arch/rv32imc.cpp
     src/iss/arch/rv32imac.cpp
     src/iss/arch/rv32gc.cpp
     src/iss/arch/rv32gcv.cpp
diff --git a/src/iss/arch/rv32imc.cpp b/src/iss/arch/rv32imc.cpp
deleted file mode 100644
index 99aa057..0000000
--- a/src/iss/arch/rv32imc.cpp
+++ /dev/null
@@ -1,70 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017 - 2020 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-
-// clang-format off
-#include "rv32imc.h"
-#include "util/ities.h"
-#include <util/logging.h>
-#include <cstdio>
-#include <cstring>
-#include <fstream>
-
-using namespace iss::arch;
-
-constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::rv32imc>::reg_names;
-constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::rv32imc>::reg_aliases;
-constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::rv32imc>::reg_bit_widths;
-constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::rv32imc>::reg_byte_offsets;
-
-rv32imc::rv32imc()  = default;
-
-rv32imc::~rv32imc() = default;
-
-void rv32imc::reset(uint64_t address) {
-    auto base_ptr = reinterpret_cast<traits<rv32imc>::reg_t*>(get_regs_base_ptr());
-    for(size_t i=0; i<traits<rv32imc>::NUM_REGS; ++i)
-        *(base_ptr+i)=0;
-    reg.PC=address;
-    reg.NEXT_PC=reg.PC;
-    reg.PRIV=0x3;
-    reg.trap_state=0;
-    reg.icount=0;
-}
-
-uint8_t *rv32imc::get_regs_base_ptr() {
-	return reinterpret_cast<uint8_t*>(&reg);
-}
-
-rv32imc::phys_addr_t rv32imc::virt2phys(const iss::addr_t &addr) {
-    return phys_addr_t(addr.access, addr.space, addr.val&traits<rv32imc>::addr_mask);
-}
-// clang-format on
diff --git a/src/iss/arch/rv32imc.h b/src/iss/arch/rv32imc.h
deleted file mode 100644
index 488afb9..0000000
--- a/src/iss/arch/rv32imc.h
+++ /dev/null
@@ -1,263 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017 - 2021 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-
-#ifndef _rv32imc_H_
-#define _rv32imc_H_
-// clang-format off
-#include <array>
-#include <iss/arch/traits.h>
-#include <iss/arch_if.h>
-#include <iss/vm_if.h>
-
-namespace iss {
-namespace arch {
-
-struct rv32imc;
-
-template <> struct traits<rv32imc> {
-
-    constexpr static char const* const core_type = "rv32imc";
-    
-    static constexpr std::array<const char*, 36> reg_names{
-        {"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc", "next_pc", "priv", "dpc"}};
- 
-    static constexpr std::array<const char*, 36> reg_aliases{
-        {"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "next_pc", "priv", "dpc"}};
-
-    enum constants {MISA_VAL=1073746180ULL, MARCHID_VAL=2147483651ULL, CLIC_NUM_IRQ=0ULL, XLEN=32ULL, INSTR_ALIGNMENT=2ULL, RFS=32ULL, fence=0ULL, fencei=1ULL, fencevmal=2ULL, fencevmau=3ULL, CSR_SIZE=4096ULL, MUL_LEN=64ULL};
-
-    constexpr static unsigned FP_REGS_SIZE = 0;
-
-    enum reg_e {
-        X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
-    };
-
-    using reg_t = uint32_t;
-
-    using addr_t = uint32_t;
-
-    using code_word_t = uint32_t; //TODO: check removal
-
-    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
-
-    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
-
-    static constexpr std::array<const uint32_t, 43> reg_bit_widths{
-        {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,32,64,64,64,32,32}};
-
-    static constexpr std::array<const uint32_t, 43> reg_byte_offsets{
-        {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,149,157,165,173,177}};
-
-    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
-
-    enum sreg_flag_e { FLAGS };
-
-    enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = MEM };
-    
-    enum class opcode_e {
-        LUI = 0,
-        AUIPC = 1,
-        JAL = 2,
-        JALR = 3,
-        BEQ = 4,
-        BNE = 5,
-        BLT = 6,
-        BGE = 7,
-        BLTU = 8,
-        BGEU = 9,
-        LB = 10,
-        LH = 11,
-        LW = 12,
-        LBU = 13,
-        LHU = 14,
-        SB = 15,
-        SH = 16,
-        SW = 17,
-        ADDI = 18,
-        SLTI = 19,
-        SLTIU = 20,
-        XORI = 21,
-        ORI = 22,
-        ANDI = 23,
-        SLLI = 24,
-        SRLI = 25,
-        SRAI = 26,
-        ADD = 27,
-        SUB = 28,
-        SLL = 29,
-        SLT = 30,
-        SLTU = 31,
-        XOR = 32,
-        SRL = 33,
-        SRA = 34,
-        OR = 35,
-        AND = 36,
-        FENCE = 37,
-        ECALL = 38,
-        EBREAK = 39,
-        MRET = 40,
-        WFI = 41,
-        CSRRW = 42,
-        CSRRS = 43,
-        CSRRC = 44,
-        CSRRWI = 45,
-        CSRRSI = 46,
-        CSRRCI = 47,
-        FENCE_I = 48,
-        MUL = 49,
-        MULH = 50,
-        MULHSU = 51,
-        MULHU = 52,
-        DIV = 53,
-        DIVU = 54,
-        REM = 55,
-        REMU = 56,
-        C__ADDI4SPN = 57,
-        C__LW = 58,
-        C__SW = 59,
-        C__ADDI = 60,
-        C__NOP = 61,
-        C__JAL = 62,
-        C__LI = 63,
-        C__LUI = 64,
-        C__ADDI16SP = 65,
-        __reserved_clui = 66,
-        C__SRLI = 67,
-        C__SRAI = 68,
-        C__ANDI = 69,
-        C__SUB = 70,
-        C__XOR = 71,
-        C__OR = 72,
-        C__AND = 73,
-        C__J = 74,
-        C__BEQZ = 75,
-        C__BNEZ = 76,
-        C__SLLI = 77,
-        C__LWSP = 78,
-        C__MV = 79,
-        C__JR = 80,
-        __reserved_cmv = 81,
-        C__ADD = 82,
-        C__JALR = 83,
-        C__EBREAK = 84,
-        C__SWSP = 85,
-        DII = 86,
-        MAX_OPCODE
-    };
-};
-
-struct rv32imc: public arch_if {
-
-    using virt_addr_t = typename traits<rv32imc>::virt_addr_t;
-    using phys_addr_t = typename traits<rv32imc>::phys_addr_t;
-    using reg_t =  typename traits<rv32imc>::reg_t;
-    using addr_t = typename traits<rv32imc>::addr_t;
-
-    rv32imc();
-    ~rv32imc();
-
-    void reset(uint64_t address=0) override;
-
-    uint8_t* get_regs_base_ptr() override;
-
-    inline uint64_t get_icount() { return reg.icount; }
-
-    inline bool should_stop() { return interrupt_sim; }
-
-    inline uint64_t stop_code() { return interrupt_sim; }
-
-    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
-
-    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
-
-    inline uint32_t get_last_branch() { return reg.last_branch; }
-
-
-#pragma pack(push, 1)
-    struct rv32imc_regs { 
-        uint32_t X0 = 0; 
-        uint32_t X1 = 0; 
-        uint32_t X2 = 0; 
-        uint32_t X3 = 0; 
-        uint32_t X4 = 0; 
-        uint32_t X5 = 0; 
-        uint32_t X6 = 0; 
-        uint32_t X7 = 0; 
-        uint32_t X8 = 0; 
-        uint32_t X9 = 0; 
-        uint32_t X10 = 0; 
-        uint32_t X11 = 0; 
-        uint32_t X12 = 0; 
-        uint32_t X13 = 0; 
-        uint32_t X14 = 0; 
-        uint32_t X15 = 0; 
-        uint32_t X16 = 0; 
-        uint32_t X17 = 0; 
-        uint32_t X18 = 0; 
-        uint32_t X19 = 0; 
-        uint32_t X20 = 0; 
-        uint32_t X21 = 0; 
-        uint32_t X22 = 0; 
-        uint32_t X23 = 0; 
-        uint32_t X24 = 0; 
-        uint32_t X25 = 0; 
-        uint32_t X26 = 0; 
-        uint32_t X27 = 0; 
-        uint32_t X28 = 0; 
-        uint32_t X29 = 0; 
-        uint32_t X30 = 0; 
-        uint32_t X31 = 0; 
-        uint32_t PC = 0; 
-        uint32_t NEXT_PC = 0; 
-        uint8_t PRIV = 0; 
-        uint32_t DPC = 0;
-        uint32_t trap_state = 0, pending_trap = 0;
-        uint64_t icount = 0;
-        uint64_t cycle = 0;
-        uint64_t instret = 0;
-        uint32_t instruction = 0;
-        uint32_t last_branch = 0;
-    } reg;
-#pragma pack(pop)
-    std::array<address_type, 4> addr_mode;
-    
-    uint64_t interrupt_sim=0;
-
-    uint32_t get_fcsr(){return 0;}
-    void set_fcsr(uint32_t val){}
-
-};
-
-}
-}            
-#endif /* _rv32imc_H_ */
-// clang-format on

From 5d40b347fb660d75c6fcdacb72c5b1b01c0abd05 Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Tue, 25 Nov 2025 17:10:34 +0100
Subject: [PATCH 49/77] changes core_complex_if and dependent files to use
 addr_t as const ref

---
 src/sysc/core_complex.cpp  | 9 +++++----
 src/sysc/core_complex.h    | 8 ++++----
 src/sysc/core_complex_if.h | 8 ++++----
 3 files changed, 13 insertions(+), 12 deletions(-)

diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index de199b7..69c414b 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -397,7 +397,8 @@ template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::r
     }
 }
 
-template <unsigned int BUSWIDTH, typename QK> bool core_complex<BUSWIDTH, QK>::read_mem(addr_t addr, unsigned length, uint8_t* const data) {
+template <unsigned int BUSWIDTH, typename QK>
+bool core_complex<BUSWIDTH, QK>::read_mem(const addr_t& addr, unsigned length, uint8_t* const data) {
     bool is_fetch = addr.space == std::numeric_limits<decltype(addr.space)>::max() ? true : false;
     auto& dmi_lut = is_fetch ? fetch_lut : read_lut;
     auto lut_entry = dmi_lut.getEntry(addr.val);
@@ -456,7 +457,7 @@ template <unsigned int BUSWIDTH, typename QK> bool core_complex<BUSWIDTH, QK>::r
 }
 
 template <unsigned int BUSWIDTH, typename QK>
-bool core_complex<BUSWIDTH, QK>::write_mem(addr_t addr, unsigned length, const uint8_t* const data) {
+bool core_complex<BUSWIDTH, QK>::write_mem(const addr_t& addr, unsigned length, const uint8_t* const data) {
     auto lut_entry = write_lut.getEntry(addr.val);
     if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && (addr.val + length) <= (lut_entry.get_end_address() + 1)) {
         auto offset = addr.val - lut_entry.get_start_address();
@@ -508,7 +509,7 @@ bool core_complex<BUSWIDTH, QK>::write_mem(addr_t addr, unsigned length, const u
 }
 
 template <unsigned int BUSWIDTH, typename QK>
-bool core_complex<BUSWIDTH, QK>::read_mem_dbg(addr_t addr, unsigned length, uint8_t* const data) {
+bool core_complex<BUSWIDTH, QK>::read_mem_dbg(const addr_t& addr, unsigned length, uint8_t* const data) {
     tlm::tlm_generic_payload gp;
     gp.set_command(tlm::TLM_READ_COMMAND);
     gp.set_address(addr.val);
@@ -519,7 +520,7 @@ bool core_complex<BUSWIDTH, QK>::read_mem_dbg(addr_t addr, unsigned length, uint
 }
 
 template <unsigned int BUSWIDTH, typename QK>
-bool core_complex<BUSWIDTH, QK>::write_mem_dbg(addr_t addr, unsigned length, const uint8_t* const data) {
+bool core_complex<BUSWIDTH, QK>::write_mem_dbg(const addr_t& addr, unsigned length, const uint8_t* const data) {
     write_buf.resize(length);
     std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
     tlm::tlm_generic_payload gp;
diff --git a/src/sysc/core_complex.h b/src/sysc/core_complex.h
index 85c912e..49b07a9 100644
--- a/src/sysc/core_complex.h
+++ b/src/sysc/core_complex.h
@@ -197,13 +197,13 @@ class core_complex : public sc_core::sc_module, public scc::traceable, public co
         last_sync_cycle = cycle;
     }
 
-    bool read_mem(iss::addr_t a, unsigned length, uint8_t* const data) override;
+    bool read_mem(const iss::addr_t& a, unsigned length, uint8_t* const data) override;
 
-    bool write_mem(iss::addr_t a, unsigned length, const uint8_t* const data) override;
+    bool write_mem(const iss::addr_t& a, unsigned length, const uint8_t* const data) override;
 
-    bool read_mem_dbg(iss::addr_t a, unsigned length, uint8_t* const data) override;
+    bool read_mem_dbg(const iss::addr_t& a, unsigned length, uint8_t* const data) override;
 
-    bool write_mem_dbg(iss::addr_t a, unsigned length, const uint8_t* const data) override;
+    bool write_mem_dbg(const iss::addr_t& a, unsigned length, const uint8_t* const data) override;
 
     void trace(sc_core::sc_trace_file* trf) const override;
 
diff --git a/src/sysc/core_complex_if.h b/src/sysc/core_complex_if.h
index 6657c3e..5e57d30 100644
--- a/src/sysc/core_complex_if.h
+++ b/src/sysc/core_complex_if.h
@@ -42,13 +42,13 @@ struct core_complex_if {
 
     virtual ~core_complex_if() = default;
 
-    virtual bool read_mem(iss::addr_t addr, unsigned length, uint8_t* const data) = 0;
+    virtual bool read_mem(const iss::addr_t& addr, unsigned length, uint8_t* const data) = 0;
 
-    virtual bool write_mem(iss::addr_t addr, unsigned length, const uint8_t* const data) = 0;
+    virtual bool write_mem(const iss::addr_t& addr, unsigned length, const uint8_t* const data) = 0;
 
-    virtual bool read_mem_dbg(iss::addr_t addr, unsigned length, uint8_t* const data) = 0;
+    virtual bool read_mem_dbg(const iss::addr_t& addr, unsigned length, uint8_t* const data) = 0;
 
-    virtual bool write_mem_dbg(iss::addr_t addr, unsigned length, const uint8_t* const data) = 0;
+    virtual bool write_mem_dbg(const iss::addr_t& addr, unsigned length, const uint8_t* const data) = 0;
 
     virtual void disass_output(uint64_t pc, std::string const& instr) = 0;
 

From 87c29b353a4576d17387bd3b3c8361b0ecd996a8 Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Wed, 26 Nov 2025 16:38:14 +0100
Subject: [PATCH 50/77] adds memspace extension to hand off spaces into the
 systemc simulation

---
 src/sysc/core_complex.cpp      |   8 +++
 src/sysc/memspace_dispatcher.h | 106 +++++++++++++++++++++++++++++++++
 src/sysc/memspace_extension.h  |  60 +++++++++++++++++++
 3 files changed, 174 insertions(+)
 create mode 100644 src/sysc/memspace_dispatcher.h
 create mode 100644 src/sysc/memspace_extension.h

diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index 69c414b..e7f8051 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -40,6 +40,7 @@
 #include <iss/vm_types.h>
 #include "iss_factory.h"
 #include "tlm/scc/quantum_keeper.h"
+#include "sysc/memspace_extension.h"
 #include <memory>
 #include <sstream>
 #include <sysc/kernel/sc_simcontext.h>
@@ -399,6 +400,8 @@ template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::r
 
 template <unsigned int BUSWIDTH, typename QK>
 bool core_complex<BUSWIDTH, QK>::read_mem(const addr_t& addr, unsigned length, uint8_t* const data) {
+    // basically checking for mem_type_e in CORENAME.h
+
     bool is_fetch = addr.space == std::numeric_limits<decltype(addr.space)>::max() ? true : false;
     auto& dmi_lut = is_fetch ? fetch_lut : read_lut;
     auto lut_entry = dmi_lut.getEntry(addr.val);
@@ -425,6 +428,8 @@ bool core_complex<BUSWIDTH, QK>::read_mem(const addr_t& addr, unsigned length, u
         gp.set_data_length(length);
         gp.set_streaming_width(length);
         sc_time delay = quantum_keeper.get_local_time();
+        if(!is_fetch)
+            gp.set_extension(new sysc::memspace::tlm_memspace_extension<>(static_cast<memspace::common>(addr.space)));
         auto pre_delay = delay;
         exec_b_transport(gp, delay, is_fetch);
         if(pre_delay > delay) {
@@ -481,6 +486,7 @@ bool core_complex<BUSWIDTH, QK>::write_mem(const addr_t& addr, unsigned length,
         gp.set_data_length(length);
         gp.set_streaming_width(length);
         sc_time delay = quantum_keeper.get_local_time();
+        gp.set_extension(new sysc::memspace::tlm_memspace_extension<>(static_cast<memspace::common>(addr.space)));
         auto pre_delay = delay;
         exec_b_transport(gp, delay);
         if(pre_delay > delay)
@@ -516,6 +522,7 @@ bool core_complex<BUSWIDTH, QK>::read_mem_dbg(const addr_t& addr, unsigned lengt
     gp.set_data_ptr(data);
     gp.set_data_length(length);
     gp.set_streaming_width(length);
+    gp.set_extension(new sysc::memspace::tlm_memspace_extension<>(static_cast<memspace::common>(addr.space)));
     return dbus->transport_dbg(gp) == length;
 }
 
@@ -529,6 +536,7 @@ bool core_complex<BUSWIDTH, QK>::write_mem_dbg(const addr_t& addr, unsigned leng
     gp.set_data_ptr(write_buf.data());
     gp.set_data_length(length);
     gp.set_streaming_width(length);
+    gp.set_extension(new sysc::memspace::tlm_memspace_extension<>(static_cast<memspace::common>(addr.space)));
     return dbus->transport_dbg(gp) == length;
 }
 
diff --git a/src/sysc/memspace_dispatcher.h b/src/sysc/memspace_dispatcher.h
new file mode 100644
index 0000000..bd457e6
--- /dev/null
+++ b/src/sysc/memspace_dispatcher.h
@@ -0,0 +1,106 @@
+/*******************************************************************************
+ * Copyright (C) 2025 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+#ifndef _SYSC_MEMSPACE_DISPATCHER_H_
+#define _SYSC_MEMSPACE_DISPATCHER_H_
+#include "scc/report.h"
+#include "scc/utilities.h"
+#include "tlm/scc/initiator_mixin.h"
+#include "tlm/scc/target_mixin.h"
+#include <cstddef>
+#include <cstdint>
+
+#include <sysc/kernel/sc_module.h>
+#include <sysc/memspace_extension.h>
+#include <sysc/utils/sc_report.h>
+#include <tlm>
+#include <tlm_core/tlm_2/tlm_generic_payload/tlm_gp.h>
+#include <unordered_map>
+
+namespace sysc {
+namespace memspace {
+template <typename MEMSPACE = common, unsigned BUSWIDTH = scc::LT, typename TARGET_SOCKET_TYPE = tlm::tlm_target_socket<BUSWIDTH>>
+struct memspace_dispatcher : sc_core::sc_module {
+    using intor_sckt = tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<BUSWIDTH>>;
+    using target_sckt = tlm::scc::target_mixin<TARGET_SOCKET_TYPE>;
+
+    target_sckt target;
+    sc_core::sc_vector<intor_sckt> initiator;
+    memspace_dispatcher(const sc_core::sc_module_name& nm, size_t slave_cnt = 1)
+    : sc_module(nm)
+    , initiator("intor", slave_cnt) {
+        sc_assert(slave_cnt > 0 && "memspace_dispatcher requires at least a single downstream module");
+        target.register_b_transport(
+            [this](tlm::tlm_generic_payload& trans, sc_core::sc_time& delay) { mapped_intor(trans)->b_transport(trans, delay); });
+        target.register_get_direct_mem_ptr([this](tlm::tlm_generic_payload& trans, tlm::tlm_dmi& dmi_data) {
+            return mapped_intor(trans)->get_direct_mem_ptr(trans, dmi_data);
+        });
+        target.register_transport_dbg([this](tlm::tlm_generic_payload& trans) { return mapped_intor(trans)->transport_dbg(trans); });
+        for(size_t i = 0; i < initiator.size(); i++) {
+            initiator[i].register_invalidate_direct_mem_ptr([this](::sc_dt::uint64 start_range, ::sc_dt::uint64 end_range) {
+                target->invalidate_direct_mem_ptr(start_range, end_range);
+            });
+        }
+    };
+    template <typename TYPE> void bind_target(TYPE& socket, size_t port_idx) { initiator[port_idx].bind(socket); };
+    void map_space_to_port(MEMSPACE space_id, unsigned port_idx) {
+        sc_assert(port_idx < initiator.size() && "Targeted port index is higher than registered initiator sockets");
+        if(space_mapping.count(space_id))
+            SCCDEBUG(SCMOD) << "remapping of space_id " << static_cast<unsigned>(space_id);
+        space_mapping[space_id] = port_idx;
+    };
+    void set_default_port(unsigned port_idx) {
+        sc_assert(port_idx < initiator.size() && "Targeted port index is higher than registered initiator sockets");
+        default_port = port_idx;
+    };
+
+private:
+    std::unordered_map<MEMSPACE, size_t> space_mapping{};
+    size_t default_port = 0;
+    intor_sckt& mapped_intor(const tlm::tlm_generic_payload& trans) {
+        tlm_memspace_extension<MEMSPACE>* ext;
+        trans.get_extension(ext);
+        if(ext) {
+            auto it = space_mapping.find(ext->get_space());
+            if(it != space_mapping.end()) {
+                SCCTRACE(SCMOD) << "Sending transaction to initiator " << it->second;
+                return initiator[it->second];
+            }
+        }
+        SCCTRACE(SCMOD) << "Sending transaction to default initiator " << default_port;
+        return initiator[default_port];
+    }
+};
+} // namespace memspace
+} // namespace sysc
+
+#endif /*_SYSC_MEMSPACE_DISPATCHER_H_*/
\ No newline at end of file
diff --git a/src/sysc/memspace_extension.h b/src/sysc/memspace_extension.h
new file mode 100644
index 0000000..d62218c
--- /dev/null
+++ b/src/sysc/memspace_extension.h
@@ -0,0 +1,60 @@
+/*******************************************************************************
+ * Copyright (C) 2025 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+#ifndef _SYSC_MEMSPACE_EXTENSION_H_
+#define _SYSC_MEMSPACE_EXTENSION_H_
+#include <cstdint>
+#include <iss/vm_types.h>
+#include <limits>
+#include <tlm>
+namespace sysc {
+namespace memspace {
+// the same enum as the mem_type_e in CORENAME.h
+enum class common : uint32_t { MEM, FENCE, RES, CSR, IMEM = std::numeric_limits<decltype(iss::addr_t::space)>::max() };
+
+template <typename MEMSPACE = common> class tlm_memspace_extension : public tlm::tlm_extension<tlm_memspace_extension<MEMSPACE>> {
+public:
+    tlm_memspace_extension(MEMSPACE space)
+    : space(space) {}
+
+    tlm::tlm_extension_base* clone() const { return new tlm_memspace_extension(this->space); }
+
+    void copy_from(tlm::tlm_extension_base const& other) { *this = static_cast<const tlm_memspace_extension&>(other); }
+    MEMSPACE get_space() const { return space; }
+
+private:
+    MEMSPACE space;
+};
+} // namespace memspace
+} // namespace sysc
+
+#endif /*_SYSC_MEMSPACE_EXTENSION_H_*/
\ No newline at end of file

From 3a4d6c3c2f94a27244a025e18d4b8dcfce31db54 Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Fri, 28 Nov 2025 19:07:30 +0100
Subject: [PATCH 51/77] corrects sending of fetches via ibus

---
 src/sysc/core_complex.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/sysc/core_complex.h b/src/sysc/core_complex.h
index 49b07a9..c881a61 100644
--- a/src/sysc/core_complex.h
+++ b/src/sysc/core_complex.h
@@ -243,8 +243,9 @@ class core_complex : public sc_core::sc_module, public scc::traceable, public co
     typename std::enable_if<std::is_same<U, tlm::scc::quantumkeeper_mt>::value>::type
     exec_b_transport(tlm::tlm_generic_payload& gp, sc_core::sc_time& delay, bool is_fetch = false) {
         quantum_keeper.execute_on_sysc([this, &gp, &delay, is_fetch]() {
+            auto& sckt = is_fetch ? ibus : dbus;
             gp.set_extension(trc.get_recording_extension(is_fetch));
-            dbus->b_transport(gp, delay);
+            sckt->b_transport(gp, delay);
         });
     }
     template <typename U = QK>

From a9257ea822f37ea0ec4b28a3f3106a230a594c41 Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Sun, 30 Nov 2025 12:55:55 +0100
Subject: [PATCH 52/77] increases verbosity for memspace_dispatcher

---
 src/sysc/memspace_dispatcher.h | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/src/sysc/memspace_dispatcher.h b/src/sysc/memspace_dispatcher.h
index bd457e6..6c42ebe 100644
--- a/src/sysc/memspace_dispatcher.h
+++ b/src/sysc/memspace_dispatcher.h
@@ -62,7 +62,7 @@ struct memspace_dispatcher : sc_core::sc_module {
         target.register_b_transport(
             [this](tlm::tlm_generic_payload& trans, sc_core::sc_time& delay) { mapped_intor(trans)->b_transport(trans, delay); });
         target.register_get_direct_mem_ptr([this](tlm::tlm_generic_payload& trans, tlm::tlm_dmi& dmi_data) {
-            return mapped_intor(trans)->get_direct_mem_ptr(trans, dmi_data);
+            return mapped_intor(trans, true)->get_direct_mem_ptr(trans, dmi_data);
         });
         target.register_transport_dbg([this](tlm::tlm_generic_payload& trans) { return mapped_intor(trans)->transport_dbg(trans); });
         for(size_t i = 0; i < initiator.size(); i++) {
@@ -86,17 +86,22 @@ struct memspace_dispatcher : sc_core::sc_module {
 private:
     std::unordered_map<MEMSPACE, size_t> space_mapping{};
     size_t default_port = 0;
-    intor_sckt& mapped_intor(const tlm::tlm_generic_payload& trans) {
+    intor_sckt& mapped_intor(const tlm::tlm_generic_payload& trans, bool dmi = false) {
+        auto prefix = dmi ? "DMI " : "";
         tlm_memspace_extension<MEMSPACE>* ext;
         trans.get_extension(ext);
         if(ext) {
             auto it = space_mapping.find(ext->get_space());
             if(it != space_mapping.end()) {
-                SCCTRACE(SCMOD) << "Sending transaction to initiator " << it->second;
+#ifndef NDEBUG
+                SCCTRACE(SCMOD) << "Sending " << prefix << "transaction to initiator " << it->second;
+#endif
                 return initiator[it->second];
             }
         }
-        SCCTRACE(SCMOD) << "Sending transaction to default initiator " << default_port;
+#ifndef NDEBUG
+        SCCTRACE(SCMOD) << "Sending " << prefix << "transaction to default initiator " << default_port;
+#endif
         return initiator[default_port];
     }
 };

From d4659ec77557785d236c542dc1405ba17da4c34a Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Sun, 30 Nov 2025 12:57:11 +0100
Subject: [PATCH 53/77] corrects DMI wrt spaces

---
 src/sysc/core_complex.cpp | 47 ++++++++++++++++++++++++++-------------
 src/sysc/core_complex.h   | 11 ++++++++-
 2 files changed, 42 insertions(+), 16 deletions(-)

diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index e7f8051..2014e7b 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -41,6 +41,7 @@
 #include "iss_factory.h"
 #include "tlm/scc/quantum_keeper.h"
 #include "sysc/memspace_extension.h"
+#include "util/range_lut.h"
 #include <memory>
 #include <sstream>
 #include <sysc/kernel/sc_simcontext.h>
@@ -179,10 +180,7 @@ void core_complex<BUSWIDTH, QK>::create_cpu(std::string const& type, std::string
 #ifndef CWR_SYSTEMC
 template <unsigned int BUSWIDTH, typename QK>
 core_complex<BUSWIDTH, QK>::core_complex(sc_module_name const& name)
-: sc_module(name)
-, fetch_lut(tlm_dmi_ext())
-, read_lut(tlm_dmi_ext())
-, write_lut(tlm_dmi_ext()) {
+: sc_module(name) {
     init();
 }
 #endif
@@ -195,13 +193,17 @@ template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::i
         }
     });
     dbus.register_invalidate_direct_mem_ptr([this](uint64_t start, uint64_t end) -> void {
-        auto lut_entry = read_lut.getEntry(start);
-        if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
-            read_lut.removeEntry(lut_entry);
+        for(auto& read_lut : dmi_read_luts) {
+            auto lut_entry = read_lut.getEntry(start);
+            if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
+                read_lut.removeEntry(lut_entry);
+            }
         }
-        lut_entry = write_lut.getEntry(start);
-        if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
-            write_lut.removeEntry(lut_entry);
+        for(auto& write_lut : dmi_write_luts) {
+            auto lut_entry = write_lut.getEntry(start);
+            if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
+                write_lut.removeEntry(lut_entry);
+            }
         }
     });
 
@@ -401,9 +403,8 @@ template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::r
 template <unsigned int BUSWIDTH, typename QK>
 bool core_complex<BUSWIDTH, QK>::read_mem(const addr_t& addr, unsigned length, uint8_t* const data) {
     // basically checking for mem_type_e in CORENAME.h
-
     bool is_fetch = addr.space == std::numeric_limits<decltype(addr.space)>::max() ? true : false;
-    auto& dmi_lut = is_fetch ? fetch_lut : read_lut;
+    auto& dmi_lut = is_fetch ? fetch_lut : get_read_lut(addr.space);
     auto lut_entry = dmi_lut.getEntry(addr.val);
     if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && (addr.val + length) <= (lut_entry.get_end_address() + 1)) {
         auto offset = addr.val - lut_entry.get_start_address();
@@ -463,7 +464,7 @@ bool core_complex<BUSWIDTH, QK>::read_mem(const addr_t& addr, unsigned length, u
 
 template <unsigned int BUSWIDTH, typename QK>
 bool core_complex<BUSWIDTH, QK>::write_mem(const addr_t& addr, unsigned length, const uint8_t* const data) {
-    auto lut_entry = write_lut.getEntry(addr.val);
+    auto lut_entry = get_write_lut(addr.space).getEntry(addr.val);
     if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && (addr.val + length) <= (lut_entry.get_end_address() + 1)) {
         auto offset = addr.val - lut_entry.get_start_address();
         std::copy(data, data + length, lut_entry.get_dmi_ptr() + offset);
@@ -506,8 +507,8 @@ bool core_complex<BUSWIDTH, QK>::write_mem(const addr_t& addr, unsigned length,
             tlm_dmi_ext dmi_data;
             if(exec_get_direct_mem_ptr(gp, dmi_data)) {
                 if(dmi_data.is_write_allowed() && (addr.val + length - 1) <= dmi_data.get_end_address())
-                    write_lut.addEntry(dmi_data, dmi_data.get_start_address(),
-                                       dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
+                    get_write_lut(addr.space)
+                        .addEntry(dmi_data, dmi_data.get_start_address(), dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
             }
         }
         return true;
@@ -539,6 +540,22 @@ bool core_complex<BUSWIDTH, QK>::write_mem_dbg(const addr_t& addr, unsigned leng
     gp.set_extension(new sysc::memspace::tlm_memspace_extension<>(static_cast<memspace::common>(addr.space)));
     return dbus->transport_dbg(gp) == length;
 }
+template <unsigned int BUSWIDTH, typename QK> util::range_lut<tlm_dmi_ext>& core_complex<BUSWIDTH, QK>::get_read_lut(unsigned space) {
+    return get_lut(dmi_read_luts, space);
+};
+template <unsigned int BUSWIDTH, typename QK> util::range_lut<tlm_dmi_ext>& core_complex<BUSWIDTH, QK>::get_write_lut(unsigned space) {
+    return get_lut(dmi_write_luts, space);
+};
+template <unsigned int BUSWIDTH, typename QK>
+util::range_lut<tlm_dmi_ext>& core_complex<BUSWIDTH, QK>::get_lut(lut_vec_t& luts, unsigned space) {
+    if(space >= luts.size()) {
+        luts.reserve(space + 1);
+        // cannot use resize as assignment and move assignment operator are not supported by range_luts with tlm_dmi_ext as defaults
+        while(space >= luts.size())
+            luts.emplace_back(tlm_dmi_ext());
+    }
+    return luts[space];
+};
 
 template class core_complex<scc::LT>;
 template class core_complex<32>;
diff --git a/src/sysc/core_complex.h b/src/sysc/core_complex.h
index c881a61..440853d 100644
--- a/src/sysc/core_complex.h
+++ b/src/sysc/core_complex.h
@@ -47,6 +47,7 @@
 #include <tlm/scc/initiator_mixin.h>
 #include <tlm/scc/quantum_keeper.h>
 #include <tlm/scc/scv/tlm_rec_initiator_socket.h>
+#include <vector>
 #ifdef CWR_SYSTEMC
 #include <scmlinc/scml_property.h>
 #else
@@ -285,7 +286,10 @@ class core_complex : public sc_core::sc_module, public scc::traceable, public co
     //
     ///////////////////////////////////////////////////////////////////////////////
     uint64_t last_sync_cycle = 0;
-    util::range_lut<tlm_dmi_ext> fetch_lut, read_lut, write_lut;
+    util::range_lut<tlm_dmi_ext> fetch_lut{tlm_dmi_ext()};
+    inline util::range_lut<tlm_dmi_ext>& get_read_lut(unsigned space);
+    inline util::range_lut<tlm_dmi_ext>& get_write_lut(unsigned space);
+
     QK quantum_keeper;
     std::vector<uint8_t> write_buf;
     sc_core::sc_signal<sc_core::sc_time> curr_clk;
@@ -300,6 +304,11 @@ class core_complex : public sc_core::sc_module, public scc::traceable, public co
 
 private:
     void init();
+    // we reserve for 8 memory spaces
+    using lut_vec_t = std::vector<util::range_lut<tlm_dmi_ext>>;
+    lut_vec_t dmi_read_luts{8, util::range_lut<tlm_dmi_ext>(tlm_dmi_ext())};
+    lut_vec_t dmi_write_luts{8, util::range_lut<tlm_dmi_ext>(tlm_dmi_ext())};
+    util::range_lut<tlm_dmi_ext>& get_lut(lut_vec_t& luts, unsigned space);
     std::vector<iss::vm_plugin*> plugin_list;
 };
 } // namespace riscv

From 36780673209c7db9928f4e1b9d03dd530d7083bc Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Fri, 5 Dec 2025 13:37:10 +0100
Subject: [PATCH 54/77] limits instantiated memory in ISS to 16GB

---
 src/iss/mem/memory_with_htif.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/iss/mem/memory_with_htif.h b/src/iss/mem/memory_with_htif.h
index 663180b..e78d718 100644
--- a/src/iss/mem/memory_with_htif.h
+++ b/src/iss/mem/memory_with_htif.h
@@ -112,7 +112,8 @@ template <typename PLAT> struct neumann_memory_with_htif : public memory_elem {
     // Currently no type erasure for the sparse_array is available, so all memories
     // have the largest possible size. Memory footprint should still be small as it
     // a sparse array
-    using mem_type = util::sparse_array<uint8_t, arch::traits<PLAT>::max_mem_size>;
+    using mem_type = util::sparse_array < uint8_t,
+          arch::traits<PLAT>::max_mem_size<1ull << 36 ? arch::traits<PLAT>::max_mem_size : (1ull << 36)>;
     std::array<mem_type, arch::traits<PLAT>::mem_sizes.size()> memories{};
     arch::priv_if<reg_t> hart_if;
 };

From 3ff92f78c514a8da543d41ef31b2c74e08bfc3e8 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Sat, 6 Dec 2025 18:09:57 +0100
Subject: [PATCH 55/77] fixes initialization of RISC-V cores by calling reset
 early

---
 src/sysc/core_complex.cpp | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index 2014e7b..f328135 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -232,13 +232,17 @@ template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::i
 #else
     SC_METHOD(sw_irq_cb);
     sensitive << sw_irq_i;
+    dont_initialize();
     SC_METHOD(timer_irq_cb);
     sensitive << timer_irq_i;
+    dont_initialize();
     SC_METHOD(ext_irq_cb);
     sensitive << ext_irq_i;
+    dont_initialize();
     SC_METHOD(local_irq_cb);
     for(auto pin : local_irq_i)
         sensitive << pin;
+    dont_initialize();
 #endif
 
     SC_METHOD(forward);
@@ -378,6 +382,7 @@ template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::l
 #endif
 
 template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::run() {
+    reset(GET_PROP_VALUE(reset_address));
     wait(SC_ZERO_TIME); // separate from elaboration phase
     do {
         wait(SC_ZERO_TIME);

From 5b4d297288e76e019943b289e99204271757efc5 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Sat, 6 Dec 2025 18:22:38 +0100
Subject: [PATCH 56/77] changes invocation of clint interrupts

---
 src/sysc/core_complex.cpp | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index f328135..3c503e9 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -232,17 +232,13 @@ template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::i
 #else
     SC_METHOD(sw_irq_cb);
     sensitive << sw_irq_i;
-    dont_initialize();
     SC_METHOD(timer_irq_cb);
     sensitive << timer_irq_i;
-    dont_initialize();
     SC_METHOD(ext_irq_cb);
     sensitive << ext_irq_i;
-    dont_initialize();
     SC_METHOD(local_irq_cb);
     for(auto pin : local_irq_i)
         sensitive << pin;
-    dont_initialize();
 #endif
 
     SC_METHOD(forward);
@@ -366,11 +362,20 @@ template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::r
 }
 
 #ifndef USE_TLM_SIGNAL
-template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::sw_irq_cb() { core->local_irq(3, sw_irq_i.read()); }
+template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::sw_irq_cb() {
+    if(!rst_i->read() && sc_core::sc_time_stamp().value())
+        core->local_irq(3, sw_irq_i.read());
+}
 
-template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::timer_irq_cb() { core->local_irq(7, timer_irq_i.read()); }
+template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::timer_irq_cb() {
+    if(!rst_i->read() && sc_core::sc_time_stamp().value())
+        core->local_irq(7, timer_irq_i.read());
+}
 
-template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::ext_irq_cb() { core->local_irq(11, ext_irq_i.read()); }
+template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::ext_irq_cb() {
+    if(!rst_i->read() && sc_core::sc_time_stamp().value())
+        core->local_irq(11, ext_irq_i.read());
+}
 
 template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::local_irq_cb() {
     for(auto i = 0U; i < local_irq_i.size(); ++i) {

From 703bfc6bcb6f2d21e15327a75b90188cf3c10ed4 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Sat, 6 Dec 2025 19:33:13 +0100
Subject: [PATCH 57/77] renames local_irq to clint_irq

---
 src/sysc/core_complex.cpp | 10 +++++-----
 src/sysc/core_complex.h   |  4 ++--
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index 3c503e9..7ca53fd 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -237,7 +237,7 @@ template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::i
     SC_METHOD(ext_irq_cb);
     sensitive << ext_irq_i;
     SC_METHOD(local_irq_cb);
-    for(auto pin : local_irq_i)
+    for(auto pin : clint_irq_i)
         sensitive << pin;
 #endif
 
@@ -377,10 +377,10 @@ template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::e
         core->local_irq(11, ext_irq_i.read());
 }
 
-template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::local_irq_cb() {
-    for(auto i = 0U; i < local_irq_i.size(); ++i) {
-        if(local_irq_i[i].event()) {
-            core->local_irq(16 + i, local_irq_i[i].read());
+template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::clint_irq_cb() {
+    for(auto i = 0U; i < clint_irq_i.size(); ++i) {
+        if(clint_irq_i[i].event()) {
+            core->local_irq(16 + i, clint_irq_i[i].read());
         }
     }
 }
diff --git a/src/sysc/core_complex.h b/src/sysc/core_complex.h
index 440853d..474be22 100644
--- a/src/sysc/core_complex.h
+++ b/src/sysc/core_complex.h
@@ -101,7 +101,7 @@ class core_complex : public sc_core::sc_module, public scc::traceable, public co
 
     irq_signal_t sw_irq_i{"sw_irq_i"};
 
-    sc_core::sc_vector<irq_signal_t> local_irq_i{"local_irq_i", 16};
+    sc_core::sc_vector<irq_signal_t> clint_irq_i{"local_irq_i", 16};
 
 #ifndef CWR_SYSTEMC
     sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
@@ -235,7 +235,7 @@ class core_complex : public sc_core::sc_module, public scc::traceable, public co
     void sw_irq_cb();
     void timer_irq_cb();
     void ext_irq_cb();
-    void local_irq_cb();
+    void clint_irq_cb();
 #endif
     ///////////////////////////////////////////////////////////////////////////////
     // multi-threaded function implementations

From 4990d15a355fc5209bd5d7ced6c46dea726fa523 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Sat, 6 Dec 2025 20:48:33 +0100
Subject: [PATCH 58/77] simplifies clint_irq signal interface

---
 src/sysc/core_complex.cpp | 23 +----------------------
 src/sysc/core_complex.h   | 11 ++---------
 2 files changed, 3 insertions(+), 31 deletions(-)

diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index 7ca53fd..22e1cf7 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -230,13 +230,7 @@ template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::i
             return tlm::TLM_COMPLETED;
         });
 #else
-    SC_METHOD(sw_irq_cb);
-    sensitive << sw_irq_i;
-    SC_METHOD(timer_irq_cb);
-    sensitive << timer_irq_i;
-    SC_METHOD(ext_irq_cb);
-    sensitive << ext_irq_i;
-    SC_METHOD(local_irq_cb);
+    SC_METHOD(clint_irq_cb);
     for(auto pin : clint_irq_i)
         sensitive << pin;
 #endif
@@ -362,21 +356,6 @@ template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::r
 }
 
 #ifndef USE_TLM_SIGNAL
-template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::sw_irq_cb() {
-    if(!rst_i->read() && sc_core::sc_time_stamp().value())
-        core->local_irq(3, sw_irq_i.read());
-}
-
-template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::timer_irq_cb() {
-    if(!rst_i->read() && sc_core::sc_time_stamp().value())
-        core->local_irq(7, timer_irq_i.read());
-}
-
-template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::ext_irq_cb() {
-    if(!rst_i->read() && sc_core::sc_time_stamp().value())
-        core->local_irq(11, ext_irq_i.read());
-}
-
 template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::clint_irq_cb() {
     for(auto i = 0U; i < clint_irq_i.size(); ++i) {
         if(clint_irq_i[i].event()) {
diff --git a/src/sysc/core_complex.h b/src/sysc/core_complex.h
index 474be22..f371057 100644
--- a/src/sysc/core_complex.h
+++ b/src/sysc/core_complex.h
@@ -84,6 +84,8 @@ using irq_signal_t = tlm::scc::tlm_signal_bool_opt_in;
 using irq_signal_t = sc_core::sc_in<bool>;
 #endif
 
+enum { SW_IRQ = 3, TIMER_IRQ = 7, EXT_IRQ = 11 };
+
 template <unsigned int BUSWIDTH = scc::LT, typename QK = tlm::scc::quantumkeeper>
 class core_complex : public sc_core::sc_module, public scc::traceable, public core_complex_if {
 public:
@@ -95,12 +97,6 @@ class core_complex : public sc_core::sc_module, public scc::traceable, public co
 
     sc_core::sc_in<bool> rst_i{"rst_i"};
 
-    irq_signal_t ext_irq_i{"ext_irq_i"};
-
-    irq_signal_t timer_irq_i{"timer_irq_i"};
-
-    irq_signal_t sw_irq_i{"sw_irq_i"};
-
     sc_core::sc_vector<irq_signal_t> clint_irq_i{"local_irq_i", 16};
 
 #ifndef CWR_SYSTEMC
@@ -232,9 +228,6 @@ class core_complex : public sc_core::sc_module, public scc::traceable, public co
     void run();
     void rst_cb();
 #ifndef USE_TLM_SIGNAL
-    void sw_irq_cb();
-    void timer_irq_cb();
-    void ext_irq_cb();
     void clint_irq_cb();
 #endif
     ///////////////////////////////////////////////////////////////////////////////

From 5dc8a9dc615d5bbc5c3d152903a064154473c4a2 Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Sun, 14 Dec 2025 10:02:19 +0100
Subject: [PATCH 59/77] removes shadowing of the state there was an error only
 in these two wrappers that shadowed the state and with that the mstatus. This
 was only relevant for dissass output as far as I can see

---
 src/iss/arch/riscv_hart_m_p.h  |  4 +---
 src/iss/arch/riscv_hart_mu_p.h | 37 ++++++++++++++++------------------
 2 files changed, 18 insertions(+), 23 deletions(-)

diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h
index bea226b..3e74d3b 100644
--- a/src/iss/arch/riscv_hart_m_p.h
+++ b/src/iss/arch/riscv_hart_m_p.h
@@ -122,8 +122,6 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_m_p : pub
     void set_csr(unsigned addr, reg_t val) { this->csr[addr & this->csr.page_addr_mask] = val; }
 
 protected:
-    hart_state<reg_t> state;
-
     std::unordered_map<uint64_t, uint8_t> atomic_reservation;
 
     iss::status read_status(unsigned addr, reg_t& val);
@@ -375,7 +373,7 @@ template <typename BASE, features_e FEAT> void riscv_hart_m_p<BASE, FEAT>::check
     // any synchronous traps.
     auto ena_irq = this->csr[mip] & this->csr[mie];
 
-    bool mstatus_mie = state.mstatus.MIE;
+    bool mstatus_mie = this->state.mstatus.MIE;
     auto m_enabled = this->reg.PRIV < PRIV_M || mstatus_mie;
     auto enabled_interrupts = m_enabled ? ena_irq : 0;
 
diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h
index a48753e..525eeb1 100644
--- a/src/iss/arch/riscv_hart_mu_p.h
+++ b/src/iss/arch/riscv_hart_mu_p.h
@@ -146,8 +146,6 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_mu_p : pu
     using mem_read_f = iss::status(iss::phys_addr_t addr, unsigned, uint8_t* const);
     using mem_write_f = iss::status(iss::phys_addr_t addr, unsigned, uint8_t const* const);
 
-    hart_state<reg_t> state;
-
     std::unordered_map<uint64_t, uint8_t> atomic_reservation;
 
     iss::status read_status(unsigned addr, reg_t& val);
@@ -162,8 +160,7 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_mu_p : pu
 
 template <typename BASE, features_e FEAT>
 riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
-: state()
-, default_mem(base::get_priv_if()) {
+: default_mem(base::get_priv_if()) {
     this->csr_rd_cb[mstatus] = MK_CSR_RD_CB(read_status);
     this->csr_wr_cb[mstatus] = MK_CSR_WR_CB(write_status);
     this->csr_rd_cb[mip] = MK_CSR_RD_CB(read_ip);
@@ -381,7 +378,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const addr_t& a, const unsigned l
 }
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_status(unsigned addr, reg_t& val) {
-    val = state.mstatus & get_mstatus_mask((addr >> 8) & 0x3);
+    val = this->state.mstatus & get_mstatus_mask((addr >> 8) & 0x3);
     return iss::Ok;
 }
 
@@ -412,7 +409,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
 
 template <typename BASE, features_e FEAT> inline void riscv_hart_mu_p<BASE, FEAT>::reset(uint64_t address) {
     BASE::reset(address);
-    state.mstatus = hart_state<reg_t>::mstatus_reset_val;
+    this->state.mstatus = hart_state<reg_t>::mstatus_reset_val;
 }
 
 template <typename BASE, features_e FEAT> void riscv_hart_mu_p<BASE, FEAT>::check_interrupt() {
@@ -423,7 +420,7 @@ template <typename BASE, features_e FEAT> void riscv_hart_mu_p<BASE, FEAT>::chec
     // any synchronous traps.
     auto ena_irq = this->csr[mip] & this->csr[mie];
 
-    bool mstatus_mie = state.mstatus.MIE;
+    bool mstatus_mie = this->state.mstatus.MIE;
     auto m_enabled = this->reg.PRIV < PRIV_M || mstatus_mie;
     auto enabled_interrupts = m_enabled ? ena_irq : 0;
 
@@ -527,13 +524,13 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
     // store the actual privilege level in yPP and store interrupt enable flags
     switch(new_priv) {
     case PRIV_M:
-        state.mstatus.MPP = this->reg.PRIV;
-        state.mstatus.MPIE = state.mstatus.MIE;
-        state.mstatus.MIE = false;
+        this->state.mstatus.MPP = this->reg.PRIV;
+        this->state.mstatus.MPIE = this->state.mstatus.MIE;
+        this->state.mstatus.MIE = false;
         break;
     case PRIV_U:
-        state.mstatus.UPIE = state.mstatus.UIE;
-        state.mstatus.UIE = false;
+        this->state.mstatus.UPIE = this->state.mstatus.UIE;
+        this->state.mstatus.UIE = false;
         break;
     default:
         break;
@@ -583,20 +580,20 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
         this->reg.trap_state = 0x80ULL << 24 | traits<BASE>::RV_CAUSE_ILLEGAL_INSTRUCTION << 16;
         this->reg.NEXT_PC = std::numeric_limits<uint32_t>::max();
     } else {
-        auto status = state.mstatus;
+        auto status = this->state.mstatus;
         // pop the relevant lower-privilege interrupt enable and privilege mode stack
         // clear respective yIE
         switch(inst_priv) {
         case PRIV_M:
-            this->reg.PRIV = state.mstatus.MPP;
-            state.mstatus.MPP = 0; // clear mpp to U mode
-            state.mstatus.MIE = state.mstatus.MPIE;
-            state.mstatus.MPIE = 1;
+            this->reg.PRIV = this->state.mstatus.MPP;
+            this->state.mstatus.MPP = 0; // clear mpp to U mode
+            this->state.mstatus.MIE = this->state.mstatus.MPIE;
+            this->state.mstatus.MPIE = 1;
             break;
         case PRIV_U:
             this->reg.PRIV = 0;
-            state.mstatus.UIE = state.mstatus.UPIE;
-            state.mstatus.UPIE = 1;
+            this->state.mstatus.UIE = this->state.mstatus.UPIE;
+            this->state.mstatus.UPIE = 1;
             break;
         }
         // sets the pc to the value stored in the x epc register.
@@ -610,7 +607,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
 }
 
 template <typename BASE, features_e FEAT> void riscv_hart_mu_p<BASE, FEAT>::wait_until(uint64_t flags) {
-    auto status = state.mstatus;
+    auto status = this->state.mstatus;
     auto tw = status.TW;
     if(this->reg.PRIV == PRIV_S && tw != 0) {
         this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_ILLEGAL_INSTRUCTION << 16;

From b4284ff992475e419c5e8390704e5e8a9b4645b9 Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Sun, 14 Dec 2025 11:31:43 +0100
Subject: [PATCH 60/77] makes disass shorter status is now hex and reduces
 default width for 64 bit addrs

---
 src/iss/arch/riscv_hart_common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/iss/arch/riscv_hart_common.h b/src/iss/arch/riscv_hart_common.h
index b480cfc..0e74270 100644
--- a/src/iss/arch/riscv_hart_common.h
+++ b/src/iss/arch/riscv_hart_common.h
@@ -548,7 +548,7 @@ template <typename BASE = logging::disass> struct riscv_hart_common : public BAS
 
     void disass_output(uint64_t pc, std::string const& instr) override {
         static CONSTEXPR char const* fmt_str =
-            sizeof(reg_t) == 4 ? "0x{:08x}    {:40} [p:{};s:{:08};i:{};c:{}]" : "0x{:016x}    {:40} [p:{};s:{:016};i:{};c:{}]";
+            sizeof(reg_t) == 4 ? "0x{:08x}    {:40} [p:{};s:0x{:02x};i:{};c:{}]" : "0x{:012x}    {:40} [p:{};s:0x{:04x};i:{};c:{}]";
         if(::logging::DEBUG <= disasslogger.get_log_level())
             ILOG(disasslogger, ::logging::DEBUG,
                  fmt::format(fmt_str, pc, instr, lvl[this->reg.PRIV], (reg_t)this->state.mstatus, this->reg.icount,

From 4b854a58cce3087e6404c80d0602ee310b33222e Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Sun, 14 Dec 2025 15:31:51 +0100
Subject: [PATCH 61/77] reworks mstatus handling, this introduces a
 hierarchical approach to the masking of the lower priv level status views

---
 src/iss/arch/riscv_hart_common.h |  5 ++
 src/iss/arch/riscv_hart_m_p.h    | 87 +++++++++++++++++++-------------
 src/iss/arch/riscv_hart_msu_vp.h | 61 +++++++++++++---------
 src/iss/arch/riscv_hart_mu_p.h   | 86 ++++++++++++-------------------
 4 files changed, 127 insertions(+), 112 deletions(-)

diff --git a/src/iss/arch/riscv_hart_common.h b/src/iss/arch/riscv_hart_common.h
index 0e74270..a61804c 100644
--- a/src/iss/arch/riscv_hart_common.h
+++ b/src/iss/arch/riscv_hart_common.h
@@ -308,6 +308,11 @@ template <typename WORD_TYPE> struct priv_if {
 };
 
 template <typename BASE = logging::disass> struct riscv_hart_common : public BASE, public mem::memory_elem {
+    // Extension status bits (SD needs to be set when writing FS / VS / XS):
+    // TODO implement XS
+    static constexpr uint32_t extension_status_mask =
+        (traits<BASE>::FP_REGS_SIZE ? (0b11u << 13) : 0u) | (traits<BASE>::V_REGS_SIZE ? (0b11u << 9) : 0u);
+
     const std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
     const std::array<const char*, 16> trap_str = {{""
                                                    "Instruction address misaligned", // 0
diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h
index 3e74d3b..e144505 100644
--- a/src/iss/arch/riscv_hart_m_p.h
+++ b/src/iss/arch/riscv_hart_m_p.h
@@ -63,46 +63,65 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_m_p : pub
     using reg_t = typename core::reg_t;
     using phys_addr_t = typename core::phys_addr_t;
 
+    // Notation for differing fields is: 32 bits / 64 bits
+    static constexpr uint32_t lower_half = 0b00000000000000000001100010001000;
+    //                                       ||||||||||||||||/|/|/|/|||||||||
+    //                                       |||||||||||||||| | | | ||||||||+-- UIE
+    //                                       |||||||||||||||| | | | |||||||+--- SIE
+    //                                       |||||||||||||||| | | | ||||||+---- WPRI
+    //                                       |||||||||||||||| | | | |||||+----- MIE
+    //                                       |||||||||||||||| | | | ||||+------ UPIE
+    //                                       |||||||||||||||| | | | |||+------- SPIE
+    //                                       |||||||||||||||| | | | ||+-------- UBE
+    //                                       |||||||||||||||| | | | |+--------- MPIE
+    //                                       |||||||||||||||| | | | +---------- SPP
+    //                                       |||||||||||||||| | | +------------ VS
+    //                                       |||||||||||||||| | +-------------- MPP
+    //                                       |||||||||||||||| +---------------- FS
+    //                                       |||||||||||||||+------------------ XS
+    //                                       ||||||||||||||+------------------- MPRV
+    //                                       |||||||||||||+-------------------- SUM
+    //                                       ||||||||||||+--------------------- MXR
+    //                                       |||||||||||+---------------------- TVM
+    //                                       ||||||||||+----------------------- TW
+    //                                       |||||||||+------------------------ TSR
+    //                                       ||||||||+------------------------- SPELP
+    //                                       |||||||+-------------------------- SDT
+    //                                       ||||||+--------------------------- WPRI
+    //                                       +--------------------------------- SD / WPRI
+
+    // upper half corresponds to mstatush bit meanings
+    static constexpr uint32_t upper_half = 0b00000000000000000000000000000000;
+    //                                       |||||||||||||||||||||||||||||/|/
+    //                                       ||||||||||||||||||||||||||||| +--- WPRI / UXL
+    //                                       ||||||||||||||||||||||||||||+----- WPRI / SXL
+    //                                       |||||||||||||||||||||||||||+------ SBE
+    //                                       |||||||||||||||||||||||||+-------- MBE
+    //                                       ||||||||||||||||||||||||+--------- GVA
+    //                                       |||||||||||||||||||||||+---------- MPV
+    //                                       ||||||||||||||||||||||+----------- WPRI
+    //                                       |||||||||||||||||||||+------------ MPELP
+    //                                       ||||||||||||||||||||+------------- MDT
+    //                                       +--------------------------------- WPRI / SD
+
     static constexpr reg_t get_mstatus_mask() {
-        if(sizeof(reg_t) == 4)
-            // return 0x807ff988UL; // 0b1000 0000 0111 1111 1111 1000 1000 1000  // only machine mode is supported
-            //       +-SD
-            //       |        +-TSR
-            //       |        |+-TW
-            //       |        ||+-TVM
-            //       |        |||+-MXR
-            //       |        ||||+-SUM
-            //       |        |||||+-MPRV
-            //       |        |||||| +-XS
-            //       |        |||||| | +-FS
-            //       |        |||||| | | +-MPP
-            //       |        |||||| | | |  +-SPP
-            //       |        |||||| | | |  |+-MPIE
-            //       |        ||||||/|/|/|  ||   +-MIE
-            return 0b00000000000000000001100010001000;
-        else if(sizeof(reg_t) == 8)
-            // return 0x8000000f007ff9ddULL; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011
-            //
-            //                +-TSR
-            //                |+-TW
-            //                ||+-TVM
-            //                |||+-MXR
-            //                ||||+-SUM
-            //                |||||+-MPRV
-            //                |||||| +-XS
-            //                |||||| | +-FS
-            //                |||||| | | +-MPP
-            //                |||||| | | |  +-SPP
-            //                |||||| | | |  |+-MPIE
-            //                ||||||/|/|/|  ||   +-MIE
-            return 0b00000000000000000001100010001000;
+        if constexpr(sizeof(reg_t) == 4)
+            return lower_half | riscv_hart_common<BASE>::extension_status_mask;
+        else if constexpr(sizeof(reg_t) == 8)
+            return static_cast<reg_t>(upper_half) << 32 | lower_half | riscv_hart_common<BASE>::extension_status_mask;
         else
-            assert(false && "Unsupported XLEN value");
+            static_assert("Unsupported XLEN value");
     }
 
     void write_mstatus(reg_t val) {
-        auto mask = get_mstatus_mask() & 0xff; // MPP is hardcoded as 0x3
+        constexpr auto mask = get_mstatus_mask();
         auto new_val = (this->state.mstatus() & ~mask) | (val & mask);
+        if constexpr(riscv_hart_common<BASE>::extension_status_mask)
+            // set SD bit if any of FS or VS are dirty
+            // FIXME: this wont work if XS is 01 and FS is 10
+            if(reg_t masked = new_val & riscv_hart_common<BASE>::extension_status_mask; masked & (masked >> 1))
+                new_val |= reg_t(1) << (sizeof(reg_t) * 8 - 1);
+
         this->state.mstatus = new_val;
     }
 
diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h
index f5cdab2..0a48108 100644
--- a/src/iss/arch/riscv_hart_msu_vp.h
+++ b/src/iss/arch/riscv_hart_msu_vp.h
@@ -35,6 +35,7 @@
 #ifndef _RISCV_HART_MSU_VP_H
 #define _RISCV_HART_MSU_VP_H
 
+#include "iss/arch/riscv_hart_mu_p.h"
 #include "iss/arch/traits.h"
 #include "iss/vm_if.h"
 #include "iss/vm_types.h"
@@ -66,32 +67,33 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_msu_vp :
     using this_class = riscv_hart_msu_vp<BASE>;
     using reg_t = typename core::reg_t;
     using phys_addr_t = typename core::phys_addr_t;
-
+    static constexpr uint32_t s_mask_lower = 0b00000000011111100000000100100010;
+    //                                         ||||||||||||||||/|/|/|/|||||||||
+    //                                         |||||||||||||||| | | | ||||||||+-- UIE
+    //                                         |||||||||||||||| | | | |||||||+--- SIE
+    //                                         |||||||||||||||| | | | ||||||+---- WPRI
+    //                                         |||||||||||||||| | | | |||||+----- MIE
+    //                                         |||||||||||||||| | | | ||||+------ UPIE
+    //                                         |||||||||||||||| | | | |||+------- SPIE
+    //                                         |||||||||||||||| | | | ||+-------- UBE
+    //                                         |||||||||||||||| | | | |+--------- MPIE
+    //                                         |||||||||||||||| | | | +---------- SPP
+    //                                         |||||||||||||||| | | +------------ VS
+    //                                         |||||||||||||||| | +-------------- MPP
+    //                                         |||||||||||||||| +---------------- FS
+    //                                         |||||||||||||||+------------------ XS
+    //                                         ||||||||||||||+------------------- MPRV
+    //                                         |||||||||||||+-------------------- SUM
+    //                                         ||||||||||||+--------------------- MXR
+    //                                         |||||||||||+---------------------- TVM
+    //                                         ||||||||||+----------------------- TW
+    //                                         |||||||||+------------------------ TSR
+    //                                         ||||||||+------------------------- SPELP
+    //                                         |||||||+-------------------------- SDT
+    //                                         ||||||+--------------------------- WPRI
+    //                                         +--------------------------------- SD / WPRI
     static constexpr reg_t get_mstatus_mask(unsigned priv_lvl) {
-        if(sizeof(reg_t) == 4) {
-#if __cplusplus < 201402L
-            return priv_lvl == PRIV_U ? 0x80000011UL : priv_lvl == PRIV_S ? 0x800de133UL : 0x807ff9ddUL;
-#else
-            switch(priv_lvl) {
-            case PRIV_U:
-                return 0x80000000UL; // 0b1000 0000 0000 0000 0000 0000 0001 0001
-            case PRIV_S:
-                return 0x800de762UL; // 0b1000 0000 0000 1101 1110 0001 0011 0011
-            default:
-                return 0x801fffeaUL; // 0b1000 0000 0111 1111 1111 1001 1011 1011
-            }
-#endif
-        } else if(sizeof(reg_t) == 8) {
-            switch(priv_lvl) {
-            case PRIV_U:
-                return 0x8000000f00000000ULL; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011
-            case PRIV_S:
-                return 0x80000003000de762ULL; // 0b1...0 0011 0000 0000 0000 1101 1110 0111 0110 0010
-            default:
-                return 0x80000030001fffeaULL; // 0b1...0 0000 0000 0000 0001 1111 1111 1111 1110 1010
-            }
-        } else
-            assert(false && "Unsupported XLEN value");
+        return riscv_hart_mu_p<BASE>::get_mstatus_mask(priv_lvl) | ((priv_lvl >= PRIV_S) ? s_mask_lower : 0);
     }
     static constexpr reg_t get_mstatus_rd_mask(unsigned priv_lvl) {
         if(sizeof(reg_t) == 4) {
@@ -115,6 +117,11 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_msu_vp :
         reg_t old_val = this->state.mstatus;
         auto mask = get_mstatus_mask(priv_lvl);
         auto new_val = (old_val & ~mask) | (val & mask);
+        if constexpr(riscv_hart_common<BASE>::extension_status_mask)
+            // set SD bit if any of FS or VS are dirty
+            // FIXME: this wont work if XS is 01 and FS is 10
+            if(reg_t masked = new_val & riscv_hart_common<BASE>::extension_status_mask && masked & (masked >> 1))
+                new_val |= reg_t(1) << (sizeof(reg_t) * 8 - 1);
         this->state.mstatus = new_val;
     }
 
@@ -129,6 +136,10 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_msu_vp :
         if((new_val & this->state.mstatus.UXL.Mask) == 0) {
             new_val |= old_val & this->state.mstatus.UXL.Mask;
         }
+        if constexpr(riscv_hart_common<BASE>::extension_status_mask)
+            if(new_val && riscv_hart_common<BASE>::extension_status_mask)
+                // set SD bit if any of FS, VS and XS are set
+                new_val |= reg_t(1) << (sizeof(reg_t) * 8 - 1);
         this->state.mstatus = new_val;
     }
 
diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h
index 525eeb1..cf0c4d5 100644
--- a/src/iss/arch/riscv_hart_mu_p.h
+++ b/src/iss/arch/riscv_hart_mu_p.h
@@ -35,6 +35,7 @@
 #ifndef _RISCV_HART_MU_P_H
 #define _RISCV_HART_MU_P_H
 
+#include "iss/arch/riscv_hart_m_p.h"
 #include "iss/arch/traits.h"
 #include "iss/vm_if.h"
 #include "iss/vm_types.h"
@@ -42,6 +43,7 @@
 #include "util/logging.h"
 #include <algorithm>
 #include <array>
+#include <cassert>
 #include <cstdint>
 #include <elfio/elf_types.hpp>
 #include <elfio/elfio.hpp>
@@ -64,65 +66,43 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_mu_p : pu
     using reg_t = typename core::reg_t;
     using phys_addr_t = typename core::phys_addr_t;
 
+    static constexpr uint32_t u_mask_lower = 0b00000000000000000000000000010001;
+    //                                         ||||||||||||||||/|/|/|/|||||||||
+    //                                         |||||||||||||||| | | | ||||||||+-- UIE
+    //                                         |||||||||||||||| | | | |||||||+--- SIE
+    //                                         |||||||||||||||| | | | ||||||+---- WPRI
+    //                                         |||||||||||||||| | | | |||||+----- MIE
+    //                                         |||||||||||||||| | | | ||||+------ UPIE
+    //                                         |||||||||||||||| | | | |||+------- SPIE
+    //                                         |||||||||||||||| | | | ||+-------- UBE
+    //                                         |||||||||||||||| | | | |+--------- MPIE
+    //                                         |||||||||||||||| | | | +---------- SPP
+    //                                         |||||||||||||||| | | +------------ VS
+    //                                         |||||||||||||||| | +-------------- MPP
+    //                                         |||||||||||||||| +---------------- FS
+    //                                         |||||||||||||||+------------------ XS
+    //                                         ||||||||||||||+------------------- MPRV
+    //                                         |||||||||||||+-------------------- SUM
+    //                                         ||||||||||||+--------------------- MXR
+    //                                         |||||||||||+---------------------- TVM
+    //                                         ||||||||||+----------------------- TW
+    //                                         |||||||||+------------------------ TSR
+    //                                         ||||||||+------------------------- SPELP
+    //                                         |||||||+-------------------------- SDT
+    //                                         ||||||+--------------------------- WPRI
+    //                                         +--------------------------------- SD / WPRI
     static constexpr reg_t get_mstatus_mask(unsigned priv_lvl) {
-        if(sizeof(reg_t) == 4) {
-#if __cplusplus < 201402L
-            return priv_lvl == PRIV_U ? 0x80000011UL : priv_lvl == PRIV_S ? 0x800de133UL : 0x807ff9ddUL;
-#else
-            switch(priv_lvl) {
-            case PRIV_U:
-                return FEAT & features_e::FEAT_EXT_N ? 0x00000011UL : 0UL; // 0b1...0 0001 0001
-            default:
-                //       +-SD
-                //       |        +-TSR
-                //       |        |+-TW
-                //       |        ||+-TVM
-                //       |        |||+-MXR
-                //       |        ||||+-SUM
-                //       |        |||||+-MPRV
-                //       |        |||||| +-XS
-                //       |        |||||| | +-FS
-                //       |        |||||| | | +-MPP
-                //       |        |||||| | | |  +-SPP
-                //       |        |||||| | | |  |+-MPIE
-                //       |        |||||| | | |  ||  +-UPIE
-                //       |        ||||||/|/|/|  ||  |+-MIE
-                //       |        ||||||/|/|/|  ||  ||  +-UIE
-                return 0b10000000001000000001100010011001;
-            }
-#endif
-        } else if(sizeof(reg_t) == 8) {
-#if __cplusplus < 201402L
-            return priv_lvl == PRIV_U ? 0x011ULL : priv_lvl == PRIV_S ? 0x000de133ULL : 0x007ff9ddULL;
-#else
-            switch(priv_lvl) {
-            case PRIV_U:
-                return FEAT & features_e::FEAT_EXT_N ? 0x8000000000000011ULL : 0ULL; // 0b1...0 0001 0001
-            default:
-                //                +-TSR
-                //                |+-TW
-                //                ||+-TVM
-                //                |||+-MXR
-                //                ||||+-SUM
-                //                |||||+-MPRV
-                //                |||||| +-XS
-                //                |||||| | +-FS
-                //                |||||| | | +-MPP
-                //                |||||| | | |  +-SPP
-                //                |||||| | | |  |+-MPIE
-                //                |||||| | | |  ||  +-UPIE
-                //                ||||||/|/|/|  ||  |+-MIE
-                //                ||||||/|/|/|  ||  ||  +-UIE
-                return 0b00000000001000000001100010011001 | 0x8000000000000000ULL;
-            }
-#endif
-        } else
-            assert(false && "Unsupported XLEN value");
+        return u_mask_lower | (priv_lvl >= PRIV_M ? riscv_hart_m_p<BASE>::get_mstatus_mask() : 0);
     }
 
     void write_mstatus(reg_t val, unsigned priv_lvl) {
         auto mask = get_mstatus_mask(priv_lvl);
         auto new_val = (this->state.mstatus() & ~mask) | (val & mask);
+        if constexpr(riscv_hart_common<BASE>::extension_status_mask)
+            // set SD bit if any of FS or VS are dirty
+            // FIXME: this wont work if XS is 01 and FS is 10
+            if(reg_t masked = new_val & riscv_hart_common<BASE>::extension_status_mask && masked & (masked >> 1))
+                new_val |= reg_t(1) << (sizeof(reg_t) * 8 - 1);
         this->state.mstatus = new_val;
     }
 

From 6c83288ae060b3a6060d5f677e55d9fb2b246bf4 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Sun, 14 Dec 2025 17:06:49 +0100
Subject: [PATCH 62/77] fixes CLINT interrupt handling

---
 src/sysc/core2sc_adapter.h | 23 +++++------------------
 src/sysc/core_complex.cpp  |  6 +++---
 src/sysc/core_complex.h    |  7 +------
 3 files changed, 9 insertions(+), 27 deletions(-)

diff --git a/src/sysc/core2sc_adapter.h b/src/sysc/core2sc_adapter.h
index 754cc21..32b3fd7 100644
--- a/src/sysc/core2sc_adapter.h
+++ b/src/sysc/core2sc_adapter.h
@@ -35,8 +35,6 @@
 #ifndef _SYSC_CORE2SC_ADAPTER_H_
 #define _SYSC_CORE2SC_ADAPTER_H_
 
-#include "core_complex.h"
-#include "iss/log_categories.h"
 #include "sc2core_if.h"
 #include "util/delegate.h"
 #include "util/logging.h"
@@ -48,6 +46,7 @@
 #include <scc/async_event.h>
 #include <scc/report.h>
 #include <shared_mutex>
+#include <sysc/kernel/sc_time.h>
 #include <util/instance_logger.h>
 #include <util/ities.h>
 
@@ -245,7 +244,7 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
     void wait_until(uint64_t flags) {
         SCCDEBUG(owner->hier_name()) << "Sleeping until interrupt";
         PLAT::wait_until(flags);
-        while(this->reg.pending_trap == 0 && (this->csr[iss::arch::mip] & this->csr[iss::arch::mie]) == 0) {
+        while((this->csr[iss::arch::mip] & this->csr[iss::arch::mie]) == 0) {
             sc_core::wait(wfi_evt);
         }
     }
@@ -289,21 +288,8 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
 
     void _local_irq(short id, bool value) {
         reg_t mask = 0;
-        switch(id) {
-        case 3: // SW
-            mask = 1 << 3;
-            break;
-        case 7: // timer
-            mask = 1 << 7;
-            break;
-        case 11: // external
-            mask = 1 << 11;
-            break;
-        default:
-            if(id > 15)
-                mask = 1 << id;
-            break;
-        }
+        assert(id < 32 && "CLINT cannot handle more tahn 32 irq");
+        mask = 1 << id;
         if(value) {
             this->csr[iss::arch::mip] |= mask;
             wfi_evt.notify();
@@ -313,6 +299,7 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
         if(value)
             SCCTRACE(owner->hier_name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap;
     }
+
     void _local_irq_mt(short id, bool value) {
         std::unique_lock<mutex_t> lock(sync_mtx);
         _local_irq(id, value);
diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index 22e1cf7..1f38c7e 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -231,8 +231,8 @@ template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::i
         });
 #else
     SC_METHOD(clint_irq_cb);
-    for(auto pin : clint_irq_i)
-        sensitive << pin;
+    dont_initialize();
+    sensitive << clint_irq_i;
 #endif
 
     SC_METHOD(forward);
@@ -359,7 +359,7 @@ template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::r
 template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::clint_irq_cb() {
     for(auto i = 0U; i < clint_irq_i.size(); ++i) {
         if(clint_irq_i[i].event()) {
-            core->local_irq(16 + i, clint_irq_i[i].read());
+            core->local_irq(i, clint_irq_i[i].read());
         }
     }
 }
diff --git a/src/sysc/core_complex.h b/src/sysc/core_complex.h
index f371057..e0e884c 100644
--- a/src/sysc/core_complex.h
+++ b/src/sysc/core_complex.h
@@ -97,7 +97,7 @@ class core_complex : public sc_core::sc_module, public scc::traceable, public co
 
     sc_core::sc_in<bool> rst_i{"rst_i"};
 
-    sc_core::sc_vector<irq_signal_t> clint_irq_i{"local_irq_i", 16};
+    sc_core::sc_vector<irq_signal_t> clint_irq_i{"clint_irq_i", 32};
 
 #ifndef CWR_SYSTEMC
     sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
@@ -186,11 +186,6 @@ class core_complex : public sc_core::sc_module, public scc::traceable, public co
     void sync(uint64_t cycle) override {
         auto core_inc = curr_clk * (cycle - last_sync_cycle);
         quantum_keeper.check_and_sync(core_inc);
-        // quantum_keeper.inc(core_inc);
-        // if(quantum_keeper.need_sync()) {
-        //     wait(quantum_keeper.get_local_time());
-        //     quantum_keeper.reset();
-        // }
         last_sync_cycle = cycle;
     }
 

From 7d93b4ff1f681e576027678fa5df547ab1187c62 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Mon, 15 Dec 2025 11:25:11 +0100
Subject: [PATCH 63/77] adds initiator id for bus accesses

---
 src/sysc/core_complex.cpp | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index 1f38c7e..46984fa 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -41,6 +41,7 @@
 #include "iss_factory.h"
 #include "tlm/scc/quantum_keeper.h"
 #include "sysc/memspace_extension.h"
+#include "tlm/scc/tlm_id.h"
 #include "util/range_lut.h"
 #include <memory>
 #include <sstream>
@@ -418,8 +419,11 @@ bool core_complex<BUSWIDTH, QK>::read_mem(const addr_t& addr, unsigned length, u
         gp.set_data_length(length);
         gp.set_streaming_width(length);
         sc_time delay = quantum_keeper.get_local_time();
+        sysc::memspace::tlm_memspace_extension<> mem_spc(static_cast<memspace::common>(addr.space));
         if(!is_fetch)
-            gp.set_extension(new sysc::memspace::tlm_memspace_extension<>(static_cast<memspace::common>(addr.space)));
+            gp.set_extension(&mem_spc);
+        tlm::scc::initiator_id_extension id_ext{mhartid.get_value()};
+        gp.set_extension(&id_ext);
         auto pre_delay = delay;
         exec_b_transport(gp, delay, is_fetch);
         if(pre_delay > delay) {
@@ -447,6 +451,8 @@ bool core_complex<BUSWIDTH, QK>::read_mem(const addr_t& addr, unsigned length, u
                     dmi_lut.addEntry(dmi_data, dmi_data.get_start_address(), dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
             }
         }
+        gp.set_extension<tlm::scc::initiator_id_extension>(nullptr);
+        gp.set_extension<sysc::memspace::tlm_memspace_extension<>>(nullptr);
         return true;
     }
 }
@@ -476,7 +482,10 @@ bool core_complex<BUSWIDTH, QK>::write_mem(const addr_t& addr, unsigned length,
         gp.set_data_length(length);
         gp.set_streaming_width(length);
         sc_time delay = quantum_keeper.get_local_time();
-        gp.set_extension(new sysc::memspace::tlm_memspace_extension<>(static_cast<memspace::common>(addr.space)));
+        sysc::memspace::tlm_memspace_extension<> mem_spc(static_cast<memspace::common>(addr.space));
+        gp.set_extension(&mem_spc);
+        tlm::scc::initiator_id_extension id_ext{mhartid.get_value()};
+        gp.set_extension(&id_ext);
         auto pre_delay = delay;
         exec_b_transport(gp, delay);
         if(pre_delay > delay)
@@ -500,6 +509,8 @@ bool core_complex<BUSWIDTH, QK>::write_mem(const addr_t& addr, unsigned length,
                         .addEntry(dmi_data, dmi_data.get_start_address(), dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
             }
         }
+        gp.set_extension<tlm::scc::initiator_id_extension>(nullptr);
+        gp.set_extension<sysc::memspace::tlm_memspace_extension<>>(nullptr);
         return true;
     }
 }

From 020f3b7210476595dc4df2d705a21f53063ceefc Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Sun, 14 Dec 2025 15:31:51 +0100
Subject: [PATCH 64/77] reworks mstatus handling, this introduces a
 hierarchical approach to the masking of the lower priv level status views

---
 src/iss/arch/riscv_hart_common.h |  5 ++
 src/iss/arch/riscv_hart_m_p.h    | 87 +++++++++++++++++++-------------
 src/iss/arch/riscv_hart_msu_vp.h | 61 +++++++++++++---------
 src/iss/arch/riscv_hart_mu_p.h   | 86 ++++++++++++-------------------
 4 files changed, 127 insertions(+), 112 deletions(-)

diff --git a/src/iss/arch/riscv_hart_common.h b/src/iss/arch/riscv_hart_common.h
index 0e74270..a61804c 100644
--- a/src/iss/arch/riscv_hart_common.h
+++ b/src/iss/arch/riscv_hart_common.h
@@ -308,6 +308,11 @@ template <typename WORD_TYPE> struct priv_if {
 };
 
 template <typename BASE = logging::disass> struct riscv_hart_common : public BASE, public mem::memory_elem {
+    // Extension status bits (SD needs to be set when writing FS / VS / XS):
+    // TODO implement XS
+    static constexpr uint32_t extension_status_mask =
+        (traits<BASE>::FP_REGS_SIZE ? (0b11u << 13) : 0u) | (traits<BASE>::V_REGS_SIZE ? (0b11u << 9) : 0u);
+
     const std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
     const std::array<const char*, 16> trap_str = {{""
                                                    "Instruction address misaligned", // 0
diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h
index 3e74d3b..e144505 100644
--- a/src/iss/arch/riscv_hart_m_p.h
+++ b/src/iss/arch/riscv_hart_m_p.h
@@ -63,46 +63,65 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_m_p : pub
     using reg_t = typename core::reg_t;
     using phys_addr_t = typename core::phys_addr_t;
 
+    // Notation for differing fields is: 32 bits / 64 bits
+    static constexpr uint32_t lower_half = 0b00000000000000000001100010001000;
+    //                                       ||||||||||||||||/|/|/|/|||||||||
+    //                                       |||||||||||||||| | | | ||||||||+-- UIE
+    //                                       |||||||||||||||| | | | |||||||+--- SIE
+    //                                       |||||||||||||||| | | | ||||||+---- WPRI
+    //                                       |||||||||||||||| | | | |||||+----- MIE
+    //                                       |||||||||||||||| | | | ||||+------ UPIE
+    //                                       |||||||||||||||| | | | |||+------- SPIE
+    //                                       |||||||||||||||| | | | ||+-------- UBE
+    //                                       |||||||||||||||| | | | |+--------- MPIE
+    //                                       |||||||||||||||| | | | +---------- SPP
+    //                                       |||||||||||||||| | | +------------ VS
+    //                                       |||||||||||||||| | +-------------- MPP
+    //                                       |||||||||||||||| +---------------- FS
+    //                                       |||||||||||||||+------------------ XS
+    //                                       ||||||||||||||+------------------- MPRV
+    //                                       |||||||||||||+-------------------- SUM
+    //                                       ||||||||||||+--------------------- MXR
+    //                                       |||||||||||+---------------------- TVM
+    //                                       ||||||||||+----------------------- TW
+    //                                       |||||||||+------------------------ TSR
+    //                                       ||||||||+------------------------- SPELP
+    //                                       |||||||+-------------------------- SDT
+    //                                       ||||||+--------------------------- WPRI
+    //                                       +--------------------------------- SD / WPRI
+
+    // upper half corresponds to mstatush bit meanings
+    static constexpr uint32_t upper_half = 0b00000000000000000000000000000000;
+    //                                       |||||||||||||||||||||||||||||/|/
+    //                                       ||||||||||||||||||||||||||||| +--- WPRI / UXL
+    //                                       ||||||||||||||||||||||||||||+----- WPRI / SXL
+    //                                       |||||||||||||||||||||||||||+------ SBE
+    //                                       |||||||||||||||||||||||||+-------- MBE
+    //                                       ||||||||||||||||||||||||+--------- GVA
+    //                                       |||||||||||||||||||||||+---------- MPV
+    //                                       ||||||||||||||||||||||+----------- WPRI
+    //                                       |||||||||||||||||||||+------------ MPELP
+    //                                       ||||||||||||||||||||+------------- MDT
+    //                                       +--------------------------------- WPRI / SD
+
     static constexpr reg_t get_mstatus_mask() {
-        if(sizeof(reg_t) == 4)
-            // return 0x807ff988UL; // 0b1000 0000 0111 1111 1111 1000 1000 1000  // only machine mode is supported
-            //       +-SD
-            //       |        +-TSR
-            //       |        |+-TW
-            //       |        ||+-TVM
-            //       |        |||+-MXR
-            //       |        ||||+-SUM
-            //       |        |||||+-MPRV
-            //       |        |||||| +-XS
-            //       |        |||||| | +-FS
-            //       |        |||||| | | +-MPP
-            //       |        |||||| | | |  +-SPP
-            //       |        |||||| | | |  |+-MPIE
-            //       |        ||||||/|/|/|  ||   +-MIE
-            return 0b00000000000000000001100010001000;
-        else if(sizeof(reg_t) == 8)
-            // return 0x8000000f007ff9ddULL; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011
-            //
-            //                +-TSR
-            //                |+-TW
-            //                ||+-TVM
-            //                |||+-MXR
-            //                ||||+-SUM
-            //                |||||+-MPRV
-            //                |||||| +-XS
-            //                |||||| | +-FS
-            //                |||||| | | +-MPP
-            //                |||||| | | |  +-SPP
-            //                |||||| | | |  |+-MPIE
-            //                ||||||/|/|/|  ||   +-MIE
-            return 0b00000000000000000001100010001000;
+        if constexpr(sizeof(reg_t) == 4)
+            return lower_half | riscv_hart_common<BASE>::extension_status_mask;
+        else if constexpr(sizeof(reg_t) == 8)
+            return static_cast<reg_t>(upper_half) << 32 | lower_half | riscv_hart_common<BASE>::extension_status_mask;
         else
-            assert(false && "Unsupported XLEN value");
+            static_assert("Unsupported XLEN value");
     }
 
     void write_mstatus(reg_t val) {
-        auto mask = get_mstatus_mask() & 0xff; // MPP is hardcoded as 0x3
+        constexpr auto mask = get_mstatus_mask();
         auto new_val = (this->state.mstatus() & ~mask) | (val & mask);
+        if constexpr(riscv_hart_common<BASE>::extension_status_mask)
+            // set SD bit if any of FS or VS are dirty
+            // FIXME: this wont work if XS is 01 and FS is 10
+            if(reg_t masked = new_val & riscv_hart_common<BASE>::extension_status_mask; masked & (masked >> 1))
+                new_val |= reg_t(1) << (sizeof(reg_t) * 8 - 1);
+
         this->state.mstatus = new_val;
     }
 
diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h
index f5cdab2..0a48108 100644
--- a/src/iss/arch/riscv_hart_msu_vp.h
+++ b/src/iss/arch/riscv_hart_msu_vp.h
@@ -35,6 +35,7 @@
 #ifndef _RISCV_HART_MSU_VP_H
 #define _RISCV_HART_MSU_VP_H
 
+#include "iss/arch/riscv_hart_mu_p.h"
 #include "iss/arch/traits.h"
 #include "iss/vm_if.h"
 #include "iss/vm_types.h"
@@ -66,32 +67,33 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_msu_vp :
     using this_class = riscv_hart_msu_vp<BASE>;
     using reg_t = typename core::reg_t;
     using phys_addr_t = typename core::phys_addr_t;
-
+    static constexpr uint32_t s_mask_lower = 0b00000000011111100000000100100010;
+    //                                         ||||||||||||||||/|/|/|/|||||||||
+    //                                         |||||||||||||||| | | | ||||||||+-- UIE
+    //                                         |||||||||||||||| | | | |||||||+--- SIE
+    //                                         |||||||||||||||| | | | ||||||+---- WPRI
+    //                                         |||||||||||||||| | | | |||||+----- MIE
+    //                                         |||||||||||||||| | | | ||||+------ UPIE
+    //                                         |||||||||||||||| | | | |||+------- SPIE
+    //                                         |||||||||||||||| | | | ||+-------- UBE
+    //                                         |||||||||||||||| | | | |+--------- MPIE
+    //                                         |||||||||||||||| | | | +---------- SPP
+    //                                         |||||||||||||||| | | +------------ VS
+    //                                         |||||||||||||||| | +-------------- MPP
+    //                                         |||||||||||||||| +---------------- FS
+    //                                         |||||||||||||||+------------------ XS
+    //                                         ||||||||||||||+------------------- MPRV
+    //                                         |||||||||||||+-------------------- SUM
+    //                                         ||||||||||||+--------------------- MXR
+    //                                         |||||||||||+---------------------- TVM
+    //                                         ||||||||||+----------------------- TW
+    //                                         |||||||||+------------------------ TSR
+    //                                         ||||||||+------------------------- SPELP
+    //                                         |||||||+-------------------------- SDT
+    //                                         ||||||+--------------------------- WPRI
+    //                                         +--------------------------------- SD / WPRI
     static constexpr reg_t get_mstatus_mask(unsigned priv_lvl) {
-        if(sizeof(reg_t) == 4) {
-#if __cplusplus < 201402L
-            return priv_lvl == PRIV_U ? 0x80000011UL : priv_lvl == PRIV_S ? 0x800de133UL : 0x807ff9ddUL;
-#else
-            switch(priv_lvl) {
-            case PRIV_U:
-                return 0x80000000UL; // 0b1000 0000 0000 0000 0000 0000 0001 0001
-            case PRIV_S:
-                return 0x800de762UL; // 0b1000 0000 0000 1101 1110 0001 0011 0011
-            default:
-                return 0x801fffeaUL; // 0b1000 0000 0111 1111 1111 1001 1011 1011
-            }
-#endif
-        } else if(sizeof(reg_t) == 8) {
-            switch(priv_lvl) {
-            case PRIV_U:
-                return 0x8000000f00000000ULL; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011
-            case PRIV_S:
-                return 0x80000003000de762ULL; // 0b1...0 0011 0000 0000 0000 1101 1110 0111 0110 0010
-            default:
-                return 0x80000030001fffeaULL; // 0b1...0 0000 0000 0000 0001 1111 1111 1111 1110 1010
-            }
-        } else
-            assert(false && "Unsupported XLEN value");
+        return riscv_hart_mu_p<BASE>::get_mstatus_mask(priv_lvl) | ((priv_lvl >= PRIV_S) ? s_mask_lower : 0);
     }
     static constexpr reg_t get_mstatus_rd_mask(unsigned priv_lvl) {
         if(sizeof(reg_t) == 4) {
@@ -115,6 +117,11 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_msu_vp :
         reg_t old_val = this->state.mstatus;
         auto mask = get_mstatus_mask(priv_lvl);
         auto new_val = (old_val & ~mask) | (val & mask);
+        if constexpr(riscv_hart_common<BASE>::extension_status_mask)
+            // set SD bit if any of FS or VS are dirty
+            // FIXME: this wont work if XS is 01 and FS is 10
+            if(reg_t masked = new_val & riscv_hart_common<BASE>::extension_status_mask && masked & (masked >> 1))
+                new_val |= reg_t(1) << (sizeof(reg_t) * 8 - 1);
         this->state.mstatus = new_val;
     }
 
@@ -129,6 +136,10 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_msu_vp :
         if((new_val & this->state.mstatus.UXL.Mask) == 0) {
             new_val |= old_val & this->state.mstatus.UXL.Mask;
         }
+        if constexpr(riscv_hart_common<BASE>::extension_status_mask)
+            if(new_val && riscv_hart_common<BASE>::extension_status_mask)
+                // set SD bit if any of FS, VS and XS are set
+                new_val |= reg_t(1) << (sizeof(reg_t) * 8 - 1);
         this->state.mstatus = new_val;
     }
 
diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h
index 525eeb1..cf0c4d5 100644
--- a/src/iss/arch/riscv_hart_mu_p.h
+++ b/src/iss/arch/riscv_hart_mu_p.h
@@ -35,6 +35,7 @@
 #ifndef _RISCV_HART_MU_P_H
 #define _RISCV_HART_MU_P_H
 
+#include "iss/arch/riscv_hart_m_p.h"
 #include "iss/arch/traits.h"
 #include "iss/vm_if.h"
 #include "iss/vm_types.h"
@@ -42,6 +43,7 @@
 #include "util/logging.h"
 #include <algorithm>
 #include <array>
+#include <cassert>
 #include <cstdint>
 #include <elfio/elf_types.hpp>
 #include <elfio/elfio.hpp>
@@ -64,65 +66,43 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_mu_p : pu
     using reg_t = typename core::reg_t;
     using phys_addr_t = typename core::phys_addr_t;
 
+    static constexpr uint32_t u_mask_lower = 0b00000000000000000000000000010001;
+    //                                         ||||||||||||||||/|/|/|/|||||||||
+    //                                         |||||||||||||||| | | | ||||||||+-- UIE
+    //                                         |||||||||||||||| | | | |||||||+--- SIE
+    //                                         |||||||||||||||| | | | ||||||+---- WPRI
+    //                                         |||||||||||||||| | | | |||||+----- MIE
+    //                                         |||||||||||||||| | | | ||||+------ UPIE
+    //                                         |||||||||||||||| | | | |||+------- SPIE
+    //                                         |||||||||||||||| | | | ||+-------- UBE
+    //                                         |||||||||||||||| | | | |+--------- MPIE
+    //                                         |||||||||||||||| | | | +---------- SPP
+    //                                         |||||||||||||||| | | +------------ VS
+    //                                         |||||||||||||||| | +-------------- MPP
+    //                                         |||||||||||||||| +---------------- FS
+    //                                         |||||||||||||||+------------------ XS
+    //                                         ||||||||||||||+------------------- MPRV
+    //                                         |||||||||||||+-------------------- SUM
+    //                                         ||||||||||||+--------------------- MXR
+    //                                         |||||||||||+---------------------- TVM
+    //                                         ||||||||||+----------------------- TW
+    //                                         |||||||||+------------------------ TSR
+    //                                         ||||||||+------------------------- SPELP
+    //                                         |||||||+-------------------------- SDT
+    //                                         ||||||+--------------------------- WPRI
+    //                                         +--------------------------------- SD / WPRI
     static constexpr reg_t get_mstatus_mask(unsigned priv_lvl) {
-        if(sizeof(reg_t) == 4) {
-#if __cplusplus < 201402L
-            return priv_lvl == PRIV_U ? 0x80000011UL : priv_lvl == PRIV_S ? 0x800de133UL : 0x807ff9ddUL;
-#else
-            switch(priv_lvl) {
-            case PRIV_U:
-                return FEAT & features_e::FEAT_EXT_N ? 0x00000011UL : 0UL; // 0b1...0 0001 0001
-            default:
-                //       +-SD
-                //       |        +-TSR
-                //       |        |+-TW
-                //       |        ||+-TVM
-                //       |        |||+-MXR
-                //       |        ||||+-SUM
-                //       |        |||||+-MPRV
-                //       |        |||||| +-XS
-                //       |        |||||| | +-FS
-                //       |        |||||| | | +-MPP
-                //       |        |||||| | | |  +-SPP
-                //       |        |||||| | | |  |+-MPIE
-                //       |        |||||| | | |  ||  +-UPIE
-                //       |        ||||||/|/|/|  ||  |+-MIE
-                //       |        ||||||/|/|/|  ||  ||  +-UIE
-                return 0b10000000001000000001100010011001;
-            }
-#endif
-        } else if(sizeof(reg_t) == 8) {
-#if __cplusplus < 201402L
-            return priv_lvl == PRIV_U ? 0x011ULL : priv_lvl == PRIV_S ? 0x000de133ULL : 0x007ff9ddULL;
-#else
-            switch(priv_lvl) {
-            case PRIV_U:
-                return FEAT & features_e::FEAT_EXT_N ? 0x8000000000000011ULL : 0ULL; // 0b1...0 0001 0001
-            default:
-                //                +-TSR
-                //                |+-TW
-                //                ||+-TVM
-                //                |||+-MXR
-                //                ||||+-SUM
-                //                |||||+-MPRV
-                //                |||||| +-XS
-                //                |||||| | +-FS
-                //                |||||| | | +-MPP
-                //                |||||| | | |  +-SPP
-                //                |||||| | | |  |+-MPIE
-                //                |||||| | | |  ||  +-UPIE
-                //                ||||||/|/|/|  ||  |+-MIE
-                //                ||||||/|/|/|  ||  ||  +-UIE
-                return 0b00000000001000000001100010011001 | 0x8000000000000000ULL;
-            }
-#endif
-        } else
-            assert(false && "Unsupported XLEN value");
+        return u_mask_lower | (priv_lvl >= PRIV_M ? riscv_hart_m_p<BASE>::get_mstatus_mask() : 0);
     }
 
     void write_mstatus(reg_t val, unsigned priv_lvl) {
         auto mask = get_mstatus_mask(priv_lvl);
         auto new_val = (this->state.mstatus() & ~mask) | (val & mask);
+        if constexpr(riscv_hart_common<BASE>::extension_status_mask)
+            // set SD bit if any of FS or VS are dirty
+            // FIXME: this wont work if XS is 01 and FS is 10
+            if(reg_t masked = new_val & riscv_hart_common<BASE>::extension_status_mask && masked & (masked >> 1))
+                new_val |= reg_t(1) << (sizeof(reg_t) * 8 - 1);
         this->state.mstatus = new_val;
     }
 

From b80ec1eaa1cd8b96400a042a0c0d7f32600885e9 Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Tue, 16 Dec 2025 09:04:54 +0100
Subject: [PATCH 65/77] changes mstatus default value for 64 bits to implement
 UXL and SXL reads

---
 src/iss/arch/mstatus.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/iss/arch/mstatus.h b/src/iss/arch/mstatus.h
index 1795f0c..0a67596 100644
--- a/src/iss/arch/mstatus.h
+++ b/src/iss/arch/mstatus.h
@@ -238,7 +238,7 @@ template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T
 
     mstatus_t mstatus;
 
-    static const T mstatus_reset_val = 0x1800;
+    static const T mstatus_reset_val = 0x500001800;
 };
 } // namespace arch
 } // namespace iss

From c48722e3f7a76eedb09185460e27884c5ce166ad Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Tue, 16 Dec 2025 09:23:03 +0100
Subject: [PATCH 66/77] moves mask generation for mstatus into common,

---
 src/iss/arch/riscv_hart_common.h | 77 ++++++++++++++++++++++++++++----
 src/iss/arch/riscv_hart_m_p.h    | 62 ++-----------------------
 src/iss/arch/riscv_hart_msu_vp.h | 77 ++++----------------------------
 src/iss/arch/riscv_hart_mu_p.h   | 40 ++---------------
 4 files changed, 85 insertions(+), 171 deletions(-)

diff --git a/src/iss/arch/riscv_hart_common.h b/src/iss/arch/riscv_hart_common.h
index a61804c..9a76d3e 100644
--- a/src/iss/arch/riscv_hart_common.h
+++ b/src/iss/arch/riscv_hart_common.h
@@ -308,11 +308,78 @@ template <typename WORD_TYPE> struct priv_if {
 };
 
 template <typename BASE = logging::disass> struct riscv_hart_common : public BASE, public mem::memory_elem {
-    // Extension status bits (SD needs to be set when writing FS / VS / XS):
+
+    constexpr static unsigned MEM = traits<BASE>::MEM;
+
+    using core = BASE;
+    using this_class = riscv_hart_common<BASE>;
+    using reg_t = typename core::reg_t;
+
+    using rd_csr_f = std::function<iss::status(unsigned addr, reg_t&)>;
+    using wr_csr_f = std::function<iss::status(unsigned addr, reg_t)>;
+
+    // Extension status bits (SD needs to be set when any of  FS / VS / XS are dirty [0b11]):
     // TODO implement XS
     static constexpr uint32_t extension_status_mask =
         (traits<BASE>::FP_REGS_SIZE ? (0b11u << 13) : 0u) | (traits<BASE>::V_REGS_SIZE ? (0b11u << 9) : 0u);
 
+    // Notation for differing fields is: 32 bits / 64 bits
+    static constexpr uint32_t mstatus_lower = 0b00000000000000000001100010001000;
+    static constexpr uint32_t sstatus_lower = 0b00000000011111100000000100100010;
+    static constexpr uint32_t ustatus_lower = 0b00000000000000000000000000010001;
+    //                                          ||||||/|||||||||/|/|/|/|||||||||
+    //                                          |||||/ ||||||||| | | | ||||||||+-- UIE
+    //                                          ||||/||||||||||| | | | |||||||+--- SIE
+    //                                          |||/|||||||||||| | | | ||||||+---- WPRI
+    //                                          ||/||||||||||||| | | | |||||+----- MIE
+    //                                          |||||||||||||||| | | | ||||+------ UPIE
+    //                                          |||||||||||||||| | | | |||+------- SPIE
+    //                                          |||||||||||||||| | | | ||+-------- UBE
+    //                                          |||||||||||||||| | | | |+--------- MPIE
+    //                                          |||||||||||||||| | | | +---------- SPP
+    //                                          |||||||||||||||| | | +------------ VS
+    //                                          |||||||||||||||| | +-------------- MPP
+    //                                          |||||||||||||||| +---------------- FS
+    //                                          |||||||||||||||+------------------ XS
+    //                                          ||||||||||||||+------------------- MPRV
+    //                                          |||||||||||||+-------------------- SUM
+    //                                          ||||||||||||+--------------------- MXR
+    //                                          |||||||||||+---------------------- TVM
+    //                                          ||||||||||+----------------------- TW
+    //                                          |||||||||+------------------------ TSR
+    //                                          ||||||||+------------------------- SPELP
+    //                                          |||||||+-------------------------- SDT
+    //                                          |++++++--------------------------- WPRI
+    //                                          +--------------------------------- SD / WPRI
+
+    // upper half does not correspond to mstatush bit meanings (UXL and SXL)
+    static constexpr uint32_t mstatus_upper = 0b00000000000000000000000000001111;
+    static constexpr uint32_t sstatus_upper = 0b00000000000000000000000000000011;
+    //                                          |||||||||||||||||||||||||||||/|/
+    //                                          ||||||||||||||||||||||||||||| +--- WPRI / UXL
+    //                                          ||||||||||||||||||||||||||||+----- WPRI / SXL
+    //                                          |||||||||||||||||||||||||||+------ SBE
+    //                                          |||||||||||||||||||||||||+-------- MBE
+    //                                          ||||||||||||||||||||||||+--------- GVA
+    //                                          |||||||||||||||||||||||+---------- MPV
+    //                                          ||||||||||||||||||||||+----------- WPRI
+    //                                          |||||||||||||||||||||+------------ MPELP
+    //                                          ||||||||||||||||||||+------------- MDT
+    //                                          |+++++++++++++++++++-------------- WPRI
+    //                                          +--------------------------------- WPRI / SD
+
+    static constexpr reg_t get_mstatus_mask() {
+        if constexpr(sizeof(reg_t) == 4)
+            return mstatus_lower | riscv_hart_common<BASE>::extension_status_mask;
+        else if constexpr(sizeof(reg_t) == 8)
+            return static_cast<reg_t>(mstatus_upper) << 32 | mstatus_lower | riscv_hart_common<BASE>::extension_status_mask;
+        else
+            static_assert("Unsupported XLEN value");
+    }
+    static constexpr reg_t get_mu_status_mask(unsigned priv_lvl) { return ustatus_lower | (priv_lvl >= PRIV_M ? get_mstatus_mask() : 0); }
+    static constexpr reg_t get_msu_status_mask(unsigned priv_lvl) {
+        return get_mu_status_mask(priv_lvl) | ((priv_lvl >= PRIV_S) ? sstatus_lower : 0);
+    }
     const std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
     const std::array<const char*, 16> trap_str = {{""
                                                    "Instruction address misaligned", // 0
@@ -335,14 +402,6 @@ template <typename BASE = logging::disass> struct riscv_hart_common : public BAS
                                                   "Machine software interrupt", "User timer interrupt", "Supervisor timer interrupt",
                                                   "Reserved", "Machine timer interrupt", "User external interrupt",
                                                   "Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
-    constexpr static unsigned MEM = traits<BASE>::MEM;
-
-    using core = BASE;
-    using this_class = riscv_hart_common<BASE>;
-    using reg_t = typename core::reg_t;
-
-    using rd_csr_f = std::function<iss::status(unsigned addr, reg_t&)>;
-    using wr_csr_f = std::function<iss::status(unsigned addr, reg_t)>;
 
 #define MK_CSR_RD_CB(FCT) [this](unsigned a, reg_t& r) -> iss::status { return this->FCT(a, r); };
 #define MK_CSR_WR_CB(FCT) [this](unsigned a, reg_t r) -> iss::status { return this->FCT(a, r); };
diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h
index e144505..7e40196 100644
--- a/src/iss/arch/riscv_hart_m_p.h
+++ b/src/iss/arch/riscv_hart_m_p.h
@@ -38,7 +38,6 @@
 #include "iss/arch/traits.h"
 #include "iss/vm_if.h"
 #include "iss/vm_types.h"
-#include "riscv_hart_common.h"
 #include "util/logging.h"
 #include <algorithm>
 #include <cstdint>
@@ -63,65 +62,12 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_m_p : pub
     using reg_t = typename core::reg_t;
     using phys_addr_t = typename core::phys_addr_t;
 
-    // Notation for differing fields is: 32 bits / 64 bits
-    static constexpr uint32_t lower_half = 0b00000000000000000001100010001000;
-    //                                       ||||||||||||||||/|/|/|/|||||||||
-    //                                       |||||||||||||||| | | | ||||||||+-- UIE
-    //                                       |||||||||||||||| | | | |||||||+--- SIE
-    //                                       |||||||||||||||| | | | ||||||+---- WPRI
-    //                                       |||||||||||||||| | | | |||||+----- MIE
-    //                                       |||||||||||||||| | | | ||||+------ UPIE
-    //                                       |||||||||||||||| | | | |||+------- SPIE
-    //                                       |||||||||||||||| | | | ||+-------- UBE
-    //                                       |||||||||||||||| | | | |+--------- MPIE
-    //                                       |||||||||||||||| | | | +---------- SPP
-    //                                       |||||||||||||||| | | +------------ VS
-    //                                       |||||||||||||||| | +-------------- MPP
-    //                                       |||||||||||||||| +---------------- FS
-    //                                       |||||||||||||||+------------------ XS
-    //                                       ||||||||||||||+------------------- MPRV
-    //                                       |||||||||||||+-------------------- SUM
-    //                                       ||||||||||||+--------------------- MXR
-    //                                       |||||||||||+---------------------- TVM
-    //                                       ||||||||||+----------------------- TW
-    //                                       |||||||||+------------------------ TSR
-    //                                       ||||||||+------------------------- SPELP
-    //                                       |||||||+-------------------------- SDT
-    //                                       ||||||+--------------------------- WPRI
-    //                                       +--------------------------------- SD / WPRI
-
-    // upper half corresponds to mstatush bit meanings
-    static constexpr uint32_t upper_half = 0b00000000000000000000000000000000;
-    //                                       |||||||||||||||||||||||||||||/|/
-    //                                       ||||||||||||||||||||||||||||| +--- WPRI / UXL
-    //                                       ||||||||||||||||||||||||||||+----- WPRI / SXL
-    //                                       |||||||||||||||||||||||||||+------ SBE
-    //                                       |||||||||||||||||||||||||+-------- MBE
-    //                                       ||||||||||||||||||||||||+--------- GVA
-    //                                       |||||||||||||||||||||||+---------- MPV
-    //                                       ||||||||||||||||||||||+----------- WPRI
-    //                                       |||||||||||||||||||||+------------ MPELP
-    //                                       ||||||||||||||||||||+------------- MDT
-    //                                       +--------------------------------- WPRI / SD
-
-    static constexpr reg_t get_mstatus_mask() {
-        if constexpr(sizeof(reg_t) == 4)
-            return lower_half | riscv_hart_common<BASE>::extension_status_mask;
-        else if constexpr(sizeof(reg_t) == 8)
-            return static_cast<reg_t>(upper_half) << 32 | lower_half | riscv_hart_common<BASE>::extension_status_mask;
-        else
-            static_assert("Unsupported XLEN value");
-    }
-
     void write_mstatus(reg_t val) {
-        constexpr auto mask = get_mstatus_mask();
+        constexpr auto mask = base::get_mstatus_mask();
         auto new_val = (this->state.mstatus() & ~mask) | (val & mask);
-        if constexpr(riscv_hart_common<BASE>::extension_status_mask)
-            // set SD bit if any of FS or VS are dirty
-            // FIXME: this wont work if XS is 01 and FS is 10
-            if(reg_t masked = new_val & riscv_hart_common<BASE>::extension_status_mask; masked & (masked >> 1))
+        if constexpr(base::extension_status_mask)
+            if((new_val & base::extension_status_mask) == base::extension_status_mask)
                 new_val |= reg_t(1) << (sizeof(reg_t) * 8 - 1);
-
         this->state.mstatus = new_val;
     }
 
@@ -351,7 +297,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const addr_t& a, const unsigned le
 }
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_status(unsigned addr, reg_t& val) {
-    val = this->state.mstatus & get_mstatus_mask();
+    val = this->state.mstatus & base::get_mstatus_mask();
     return iss::Ok;
 }
 
diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h
index 0a48108..9edb2e4 100644
--- a/src/iss/arch/riscv_hart_msu_vp.h
+++ b/src/iss/arch/riscv_hart_msu_vp.h
@@ -35,7 +35,6 @@
 #ifndef _RISCV_HART_MSU_VP_H
 #define _RISCV_HART_MSU_VP_H
 
-#include "iss/arch/riscv_hart_mu_p.h"
 #include "iss/arch/traits.h"
 #include "iss/vm_if.h"
 #include "iss/vm_types.h"
@@ -67,78 +66,20 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_msu_vp :
     using this_class = riscv_hart_msu_vp<BASE>;
     using reg_t = typename core::reg_t;
     using phys_addr_t = typename core::phys_addr_t;
-    static constexpr uint32_t s_mask_lower = 0b00000000011111100000000100100010;
-    //                                         ||||||||||||||||/|/|/|/|||||||||
-    //                                         |||||||||||||||| | | | ||||||||+-- UIE
-    //                                         |||||||||||||||| | | | |||||||+--- SIE
-    //                                         |||||||||||||||| | | | ||||||+---- WPRI
-    //                                         |||||||||||||||| | | | |||||+----- MIE
-    //                                         |||||||||||||||| | | | ||||+------ UPIE
-    //                                         |||||||||||||||| | | | |||+------- SPIE
-    //                                         |||||||||||||||| | | | ||+-------- UBE
-    //                                         |||||||||||||||| | | | |+--------- MPIE
-    //                                         |||||||||||||||| | | | +---------- SPP
-    //                                         |||||||||||||||| | | +------------ VS
-    //                                         |||||||||||||||| | +-------------- MPP
-    //                                         |||||||||||||||| +---------------- FS
-    //                                         |||||||||||||||+------------------ XS
-    //                                         ||||||||||||||+------------------- MPRV
-    //                                         |||||||||||||+-------------------- SUM
-    //                                         ||||||||||||+--------------------- MXR
-    //                                         |||||||||||+---------------------- TVM
-    //                                         ||||||||||+----------------------- TW
-    //                                         |||||||||+------------------------ TSR
-    //                                         ||||||||+------------------------- SPELP
-    //                                         |||||||+-------------------------- SDT
-    //                                         ||||||+--------------------------- WPRI
-    //                                         +--------------------------------- SD / WPRI
-    static constexpr reg_t get_mstatus_mask(unsigned priv_lvl) {
-        return riscv_hart_mu_p<BASE>::get_mstatus_mask(priv_lvl) | ((priv_lvl >= PRIV_S) ? s_mask_lower : 0);
-    }
-    static constexpr reg_t get_mstatus_rd_mask(unsigned priv_lvl) {
-        if(sizeof(reg_t) == 4) {
-            return get_mstatus_mask(priv_lvl);
-        } else if(sizeof(reg_t) == 8) {
-            auto wr_mask = get_mstatus_mask(priv_lvl);
-            switch(priv_lvl) {
-            case PRIV_U:
-                return wr_mask;
-            case PRIV_S:
-                return wr_mask |= 0x300000000;
-            default:
-                return wr_mask |= 0xf00000000;
-            }
-        } else
-            assert(false && "Unsupported XLEN value");
-    }
 
-    template <typename T_ = reg_t, std::enable_if_t<std::is_same<T_, uint32_t>::value>* = nullptr>
-    void write_mstatus(T_ val, unsigned priv_lvl) {
+    void write_mstatus(reg_t val, unsigned priv_lvl) {
         reg_t old_val = this->state.mstatus;
-        auto mask = get_mstatus_mask(priv_lvl);
+        auto mask = base::get_msu_status_mask(priv_lvl);
         auto new_val = (old_val & ~mask) | (val & mask);
-        if constexpr(riscv_hart_common<BASE>::extension_status_mask)
-            // set SD bit if any of FS or VS are dirty
-            // FIXME: this wont work if XS is 01 and FS is 10
-            if(reg_t masked = new_val & riscv_hart_common<BASE>::extension_status_mask && masked & (masked >> 1))
-                new_val |= reg_t(1) << (sizeof(reg_t) * 8 - 1);
-        this->state.mstatus = new_val;
-    }
-
-    template <typename T_ = reg_t, std::enable_if_t<std::is_same<T_, uint64_t>::value>* = nullptr>
-    void write_mstatus(T_ val, unsigned priv_lvl) {
-        reg_t old_val = this->state.mstatus;
-        auto mask = get_mstatus_mask(priv_lvl);
-        auto new_val = (old_val & ~mask) | (val & mask);
-        if((new_val & this->state.mstatus.SXL.Mask) == 0) {
+        if constexpr(sizeof(reg_t) == 8) {
+            // Retain previous SXL and UXL value
             new_val |= old_val & this->state.mstatus.SXL.Mask;
-        }
-        if((new_val & this->state.mstatus.UXL.Mask) == 0) {
+
             new_val |= old_val & this->state.mstatus.UXL.Mask;
         }
-        if constexpr(riscv_hart_common<BASE>::extension_status_mask)
-            if(new_val && riscv_hart_common<BASE>::extension_status_mask)
-                // set SD bit if any of FS, VS and XS are set
+
+        if constexpr(base::extension_status_mask)
+            if((new_val & base::extension_status_mask) == base::extension_status_mask)
                 new_val |= reg_t(1) << (sizeof(reg_t) * 8 - 1);
         this->state.mstatus = new_val;
     }
@@ -439,7 +380,7 @@ iss::status riscv_hart_msu_vp<BASE, FEAT>::write(const addr_t& a, const unsigned
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_msu_vp<BASE, FEAT>::read_status(unsigned addr, reg_t& val) {
     auto req_priv_lvl = (addr >> 8) & 0x3;
-    val = this->state.mstatus & get_mstatus_rd_mask(req_priv_lvl);
+    val = this->state.mstatus & base::get_msu_status_mask(req_priv_lvl);
     return iss::Ok;
 }
 
diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h
index cf0c4d5..032ff17 100644
--- a/src/iss/arch/riscv_hart_mu_p.h
+++ b/src/iss/arch/riscv_hart_mu_p.h
@@ -35,7 +35,6 @@
 #ifndef _RISCV_HART_MU_P_H
 #define _RISCV_HART_MU_P_H
 
-#include "iss/arch/riscv_hart_m_p.h"
 #include "iss/arch/traits.h"
 #include "iss/vm_if.h"
 #include "iss/vm_types.h"
@@ -66,42 +65,11 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_mu_p : pu
     using reg_t = typename core::reg_t;
     using phys_addr_t = typename core::phys_addr_t;
 
-    static constexpr uint32_t u_mask_lower = 0b00000000000000000000000000010001;
-    //                                         ||||||||||||||||/|/|/|/|||||||||
-    //                                         |||||||||||||||| | | | ||||||||+-- UIE
-    //                                         |||||||||||||||| | | | |||||||+--- SIE
-    //                                         |||||||||||||||| | | | ||||||+---- WPRI
-    //                                         |||||||||||||||| | | | |||||+----- MIE
-    //                                         |||||||||||||||| | | | ||||+------ UPIE
-    //                                         |||||||||||||||| | | | |||+------- SPIE
-    //                                         |||||||||||||||| | | | ||+-------- UBE
-    //                                         |||||||||||||||| | | | |+--------- MPIE
-    //                                         |||||||||||||||| | | | +---------- SPP
-    //                                         |||||||||||||||| | | +------------ VS
-    //                                         |||||||||||||||| | +-------------- MPP
-    //                                         |||||||||||||||| +---------------- FS
-    //                                         |||||||||||||||+------------------ XS
-    //                                         ||||||||||||||+------------------- MPRV
-    //                                         |||||||||||||+-------------------- SUM
-    //                                         ||||||||||||+--------------------- MXR
-    //                                         |||||||||||+---------------------- TVM
-    //                                         ||||||||||+----------------------- TW
-    //                                         |||||||||+------------------------ TSR
-    //                                         ||||||||+------------------------- SPELP
-    //                                         |||||||+-------------------------- SDT
-    //                                         ||||||+--------------------------- WPRI
-    //                                         +--------------------------------- SD / WPRI
-    static constexpr reg_t get_mstatus_mask(unsigned priv_lvl) {
-        return u_mask_lower | (priv_lvl >= PRIV_M ? riscv_hart_m_p<BASE>::get_mstatus_mask() : 0);
-    }
-
     void write_mstatus(reg_t val, unsigned priv_lvl) {
-        auto mask = get_mstatus_mask(priv_lvl);
+        auto mask = base::get_mu_status_mask(priv_lvl);
         auto new_val = (this->state.mstatus() & ~mask) | (val & mask);
-        if constexpr(riscv_hart_common<BASE>::extension_status_mask)
-            // set SD bit if any of FS or VS are dirty
-            // FIXME: this wont work if XS is 01 and FS is 10
-            if(reg_t masked = new_val & riscv_hart_common<BASE>::extension_status_mask && masked & (masked >> 1))
+        if constexpr(base::extension_status_mask)
+            if((new_val & base::extension_status_mask) == base::extension_status_mask)
                 new_val |= reg_t(1) << (sizeof(reg_t) * 8 - 1);
         this->state.mstatus = new_val;
     }
@@ -358,7 +326,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const addr_t& a, const unsigned l
 }
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_status(unsigned addr, reg_t& val) {
-    val = this->state.mstatus & get_mstatus_mask((addr >> 8) & 0x3);
+    val = this->state.mstatus & base::get_mu_status_mask((addr >> 8) & 0x3);
     return iss::Ok;
 }
 

From cf5f0815e03c03069789a91c7021c6da471e50f2 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Sun, 14 Dec 2025 17:06:49 +0100
Subject: [PATCH 67/77] fixes CLINT interrupt handling

---
 src/sysc/core2sc_adapter.h | 23 +++++------------------
 src/sysc/core_complex.cpp  |  6 +++---
 src/sysc/core_complex.h    |  7 +------
 3 files changed, 9 insertions(+), 27 deletions(-)

diff --git a/src/sysc/core2sc_adapter.h b/src/sysc/core2sc_adapter.h
index 754cc21..32b3fd7 100644
--- a/src/sysc/core2sc_adapter.h
+++ b/src/sysc/core2sc_adapter.h
@@ -35,8 +35,6 @@
 #ifndef _SYSC_CORE2SC_ADAPTER_H_
 #define _SYSC_CORE2SC_ADAPTER_H_
 
-#include "core_complex.h"
-#include "iss/log_categories.h"
 #include "sc2core_if.h"
 #include "util/delegate.h"
 #include "util/logging.h"
@@ -48,6 +46,7 @@
 #include <scc/async_event.h>
 #include <scc/report.h>
 #include <shared_mutex>
+#include <sysc/kernel/sc_time.h>
 #include <util/instance_logger.h>
 #include <util/ities.h>
 
@@ -245,7 +244,7 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
     void wait_until(uint64_t flags) {
         SCCDEBUG(owner->hier_name()) << "Sleeping until interrupt";
         PLAT::wait_until(flags);
-        while(this->reg.pending_trap == 0 && (this->csr[iss::arch::mip] & this->csr[iss::arch::mie]) == 0) {
+        while((this->csr[iss::arch::mip] & this->csr[iss::arch::mie]) == 0) {
             sc_core::wait(wfi_evt);
         }
     }
@@ -289,21 +288,8 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
 
     void _local_irq(short id, bool value) {
         reg_t mask = 0;
-        switch(id) {
-        case 3: // SW
-            mask = 1 << 3;
-            break;
-        case 7: // timer
-            mask = 1 << 7;
-            break;
-        case 11: // external
-            mask = 1 << 11;
-            break;
-        default:
-            if(id > 15)
-                mask = 1 << id;
-            break;
-        }
+        assert(id < 32 && "CLINT cannot handle more tahn 32 irq");
+        mask = 1 << id;
         if(value) {
             this->csr[iss::arch::mip] |= mask;
             wfi_evt.notify();
@@ -313,6 +299,7 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
         if(value)
             SCCTRACE(owner->hier_name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap;
     }
+
     void _local_irq_mt(short id, bool value) {
         std::unique_lock<mutex_t> lock(sync_mtx);
         _local_irq(id, value);
diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index 22e1cf7..1f38c7e 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -231,8 +231,8 @@ template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::i
         });
 #else
     SC_METHOD(clint_irq_cb);
-    for(auto pin : clint_irq_i)
-        sensitive << pin;
+    dont_initialize();
+    sensitive << clint_irq_i;
 #endif
 
     SC_METHOD(forward);
@@ -359,7 +359,7 @@ template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::r
 template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::clint_irq_cb() {
     for(auto i = 0U; i < clint_irq_i.size(); ++i) {
         if(clint_irq_i[i].event()) {
-            core->local_irq(16 + i, clint_irq_i[i].read());
+            core->local_irq(i, clint_irq_i[i].read());
         }
     }
 }
diff --git a/src/sysc/core_complex.h b/src/sysc/core_complex.h
index f371057..e0e884c 100644
--- a/src/sysc/core_complex.h
+++ b/src/sysc/core_complex.h
@@ -97,7 +97,7 @@ class core_complex : public sc_core::sc_module, public scc::traceable, public co
 
     sc_core::sc_in<bool> rst_i{"rst_i"};
 
-    sc_core::sc_vector<irq_signal_t> clint_irq_i{"local_irq_i", 16};
+    sc_core::sc_vector<irq_signal_t> clint_irq_i{"clint_irq_i", 32};
 
 #ifndef CWR_SYSTEMC
     sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
@@ -186,11 +186,6 @@ class core_complex : public sc_core::sc_module, public scc::traceable, public co
     void sync(uint64_t cycle) override {
         auto core_inc = curr_clk * (cycle - last_sync_cycle);
         quantum_keeper.check_and_sync(core_inc);
-        // quantum_keeper.inc(core_inc);
-        // if(quantum_keeper.need_sync()) {
-        //     wait(quantum_keeper.get_local_time());
-        //     quantum_keeper.reset();
-        // }
         last_sync_cycle = cycle;
     }
 

From 0f4bb16b1aac26f3b2686419821b033de335c83c Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Mon, 15 Dec 2025 11:25:11 +0100
Subject: [PATCH 68/77] adds initiator id for bus accesses

---
 src/sysc/core_complex.cpp | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index 1f38c7e..46984fa 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -41,6 +41,7 @@
 #include "iss_factory.h"
 #include "tlm/scc/quantum_keeper.h"
 #include "sysc/memspace_extension.h"
+#include "tlm/scc/tlm_id.h"
 #include "util/range_lut.h"
 #include <memory>
 #include <sstream>
@@ -418,8 +419,11 @@ bool core_complex<BUSWIDTH, QK>::read_mem(const addr_t& addr, unsigned length, u
         gp.set_data_length(length);
         gp.set_streaming_width(length);
         sc_time delay = quantum_keeper.get_local_time();
+        sysc::memspace::tlm_memspace_extension<> mem_spc(static_cast<memspace::common>(addr.space));
         if(!is_fetch)
-            gp.set_extension(new sysc::memspace::tlm_memspace_extension<>(static_cast<memspace::common>(addr.space)));
+            gp.set_extension(&mem_spc);
+        tlm::scc::initiator_id_extension id_ext{mhartid.get_value()};
+        gp.set_extension(&id_ext);
         auto pre_delay = delay;
         exec_b_transport(gp, delay, is_fetch);
         if(pre_delay > delay) {
@@ -447,6 +451,8 @@ bool core_complex<BUSWIDTH, QK>::read_mem(const addr_t& addr, unsigned length, u
                     dmi_lut.addEntry(dmi_data, dmi_data.get_start_address(), dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
             }
         }
+        gp.set_extension<tlm::scc::initiator_id_extension>(nullptr);
+        gp.set_extension<sysc::memspace::tlm_memspace_extension<>>(nullptr);
         return true;
     }
 }
@@ -476,7 +482,10 @@ bool core_complex<BUSWIDTH, QK>::write_mem(const addr_t& addr, unsigned length,
         gp.set_data_length(length);
         gp.set_streaming_width(length);
         sc_time delay = quantum_keeper.get_local_time();
-        gp.set_extension(new sysc::memspace::tlm_memspace_extension<>(static_cast<memspace::common>(addr.space)));
+        sysc::memspace::tlm_memspace_extension<> mem_spc(static_cast<memspace::common>(addr.space));
+        gp.set_extension(&mem_spc);
+        tlm::scc::initiator_id_extension id_ext{mhartid.get_value()};
+        gp.set_extension(&id_ext);
         auto pre_delay = delay;
         exec_b_transport(gp, delay);
         if(pre_delay > delay)
@@ -500,6 +509,8 @@ bool core_complex<BUSWIDTH, QK>::write_mem(const addr_t& addr, unsigned length,
                         .addEntry(dmi_data, dmi_data.get_start_address(), dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
             }
         }
+        gp.set_extension<tlm::scc::initiator_id_extension>(nullptr);
+        gp.set_extension<sysc::memspace::tlm_memspace_extension<>>(nullptr);
         return true;
     }
 }

From 605c236f0366c9740edf2f51c322cb4078ece79f Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Tue, 16 Dec 2025 09:04:54 +0100
Subject: [PATCH 69/77] changes mstatus default value for 64 bits to implement
 UXL and SXL reads

---
 src/iss/arch/mstatus.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/iss/arch/mstatus.h b/src/iss/arch/mstatus.h
index 1795f0c..0a67596 100644
--- a/src/iss/arch/mstatus.h
+++ b/src/iss/arch/mstatus.h
@@ -238,7 +238,7 @@ template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T
 
     mstatus_t mstatus;
 
-    static const T mstatus_reset_val = 0x1800;
+    static const T mstatus_reset_val = 0x500001800;
 };
 } // namespace arch
 } // namespace iss

From cedc4911ca72bac3dfb895bda551c080aff7456e Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Tue, 16 Dec 2025 09:23:03 +0100
Subject: [PATCH 70/77] moves mask generation for mstatus into common,

---
 src/iss/arch/riscv_hart_common.h | 77 ++++++++++++++++++++++++++++----
 src/iss/arch/riscv_hart_m_p.h    | 62 ++-----------------------
 src/iss/arch/riscv_hart_msu_vp.h | 77 ++++----------------------------
 src/iss/arch/riscv_hart_mu_p.h   | 40 ++---------------
 4 files changed, 85 insertions(+), 171 deletions(-)

diff --git a/src/iss/arch/riscv_hart_common.h b/src/iss/arch/riscv_hart_common.h
index a61804c..9a76d3e 100644
--- a/src/iss/arch/riscv_hart_common.h
+++ b/src/iss/arch/riscv_hart_common.h
@@ -308,11 +308,78 @@ template <typename WORD_TYPE> struct priv_if {
 };
 
 template <typename BASE = logging::disass> struct riscv_hart_common : public BASE, public mem::memory_elem {
-    // Extension status bits (SD needs to be set when writing FS / VS / XS):
+
+    constexpr static unsigned MEM = traits<BASE>::MEM;
+
+    using core = BASE;
+    using this_class = riscv_hart_common<BASE>;
+    using reg_t = typename core::reg_t;
+
+    using rd_csr_f = std::function<iss::status(unsigned addr, reg_t&)>;
+    using wr_csr_f = std::function<iss::status(unsigned addr, reg_t)>;
+
+    // Extension status bits (SD needs to be set when any of  FS / VS / XS are dirty [0b11]):
     // TODO implement XS
     static constexpr uint32_t extension_status_mask =
         (traits<BASE>::FP_REGS_SIZE ? (0b11u << 13) : 0u) | (traits<BASE>::V_REGS_SIZE ? (0b11u << 9) : 0u);
 
+    // Notation for differing fields is: 32 bits / 64 bits
+    static constexpr uint32_t mstatus_lower = 0b00000000000000000001100010001000;
+    static constexpr uint32_t sstatus_lower = 0b00000000011111100000000100100010;
+    static constexpr uint32_t ustatus_lower = 0b00000000000000000000000000010001;
+    //                                          ||||||/|||||||||/|/|/|/|||||||||
+    //                                          |||||/ ||||||||| | | | ||||||||+-- UIE
+    //                                          ||||/||||||||||| | | | |||||||+--- SIE
+    //                                          |||/|||||||||||| | | | ||||||+---- WPRI
+    //                                          ||/||||||||||||| | | | |||||+----- MIE
+    //                                          |||||||||||||||| | | | ||||+------ UPIE
+    //                                          |||||||||||||||| | | | |||+------- SPIE
+    //                                          |||||||||||||||| | | | ||+-------- UBE
+    //                                          |||||||||||||||| | | | |+--------- MPIE
+    //                                          |||||||||||||||| | | | +---------- SPP
+    //                                          |||||||||||||||| | | +------------ VS
+    //                                          |||||||||||||||| | +-------------- MPP
+    //                                          |||||||||||||||| +---------------- FS
+    //                                          |||||||||||||||+------------------ XS
+    //                                          ||||||||||||||+------------------- MPRV
+    //                                          |||||||||||||+-------------------- SUM
+    //                                          ||||||||||||+--------------------- MXR
+    //                                          |||||||||||+---------------------- TVM
+    //                                          ||||||||||+----------------------- TW
+    //                                          |||||||||+------------------------ TSR
+    //                                          ||||||||+------------------------- SPELP
+    //                                          |||||||+-------------------------- SDT
+    //                                          |++++++--------------------------- WPRI
+    //                                          +--------------------------------- SD / WPRI
+
+    // upper half does not correspond to mstatush bit meanings (UXL and SXL)
+    static constexpr uint32_t mstatus_upper = 0b00000000000000000000000000001111;
+    static constexpr uint32_t sstatus_upper = 0b00000000000000000000000000000011;
+    //                                          |||||||||||||||||||||||||||||/|/
+    //                                          ||||||||||||||||||||||||||||| +--- WPRI / UXL
+    //                                          ||||||||||||||||||||||||||||+----- WPRI / SXL
+    //                                          |||||||||||||||||||||||||||+------ SBE
+    //                                          |||||||||||||||||||||||||+-------- MBE
+    //                                          ||||||||||||||||||||||||+--------- GVA
+    //                                          |||||||||||||||||||||||+---------- MPV
+    //                                          ||||||||||||||||||||||+----------- WPRI
+    //                                          |||||||||||||||||||||+------------ MPELP
+    //                                          ||||||||||||||||||||+------------- MDT
+    //                                          |+++++++++++++++++++-------------- WPRI
+    //                                          +--------------------------------- WPRI / SD
+
+    static constexpr reg_t get_mstatus_mask() {
+        if constexpr(sizeof(reg_t) == 4)
+            return mstatus_lower | riscv_hart_common<BASE>::extension_status_mask;
+        else if constexpr(sizeof(reg_t) == 8)
+            return static_cast<reg_t>(mstatus_upper) << 32 | mstatus_lower | riscv_hart_common<BASE>::extension_status_mask;
+        else
+            static_assert("Unsupported XLEN value");
+    }
+    static constexpr reg_t get_mu_status_mask(unsigned priv_lvl) { return ustatus_lower | (priv_lvl >= PRIV_M ? get_mstatus_mask() : 0); }
+    static constexpr reg_t get_msu_status_mask(unsigned priv_lvl) {
+        return get_mu_status_mask(priv_lvl) | ((priv_lvl >= PRIV_S) ? sstatus_lower : 0);
+    }
     const std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
     const std::array<const char*, 16> trap_str = {{""
                                                    "Instruction address misaligned", // 0
@@ -335,14 +402,6 @@ template <typename BASE = logging::disass> struct riscv_hart_common : public BAS
                                                   "Machine software interrupt", "User timer interrupt", "Supervisor timer interrupt",
                                                   "Reserved", "Machine timer interrupt", "User external interrupt",
                                                   "Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
-    constexpr static unsigned MEM = traits<BASE>::MEM;
-
-    using core = BASE;
-    using this_class = riscv_hart_common<BASE>;
-    using reg_t = typename core::reg_t;
-
-    using rd_csr_f = std::function<iss::status(unsigned addr, reg_t&)>;
-    using wr_csr_f = std::function<iss::status(unsigned addr, reg_t)>;
 
 #define MK_CSR_RD_CB(FCT) [this](unsigned a, reg_t& r) -> iss::status { return this->FCT(a, r); };
 #define MK_CSR_WR_CB(FCT) [this](unsigned a, reg_t r) -> iss::status { return this->FCT(a, r); };
diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h
index e144505..7e40196 100644
--- a/src/iss/arch/riscv_hart_m_p.h
+++ b/src/iss/arch/riscv_hart_m_p.h
@@ -38,7 +38,6 @@
 #include "iss/arch/traits.h"
 #include "iss/vm_if.h"
 #include "iss/vm_types.h"
-#include "riscv_hart_common.h"
 #include "util/logging.h"
 #include <algorithm>
 #include <cstdint>
@@ -63,65 +62,12 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_m_p : pub
     using reg_t = typename core::reg_t;
     using phys_addr_t = typename core::phys_addr_t;
 
-    // Notation for differing fields is: 32 bits / 64 bits
-    static constexpr uint32_t lower_half = 0b00000000000000000001100010001000;
-    //                                       ||||||||||||||||/|/|/|/|||||||||
-    //                                       |||||||||||||||| | | | ||||||||+-- UIE
-    //                                       |||||||||||||||| | | | |||||||+--- SIE
-    //                                       |||||||||||||||| | | | ||||||+---- WPRI
-    //                                       |||||||||||||||| | | | |||||+----- MIE
-    //                                       |||||||||||||||| | | | ||||+------ UPIE
-    //                                       |||||||||||||||| | | | |||+------- SPIE
-    //                                       |||||||||||||||| | | | ||+-------- UBE
-    //                                       |||||||||||||||| | | | |+--------- MPIE
-    //                                       |||||||||||||||| | | | +---------- SPP
-    //                                       |||||||||||||||| | | +------------ VS
-    //                                       |||||||||||||||| | +-------------- MPP
-    //                                       |||||||||||||||| +---------------- FS
-    //                                       |||||||||||||||+------------------ XS
-    //                                       ||||||||||||||+------------------- MPRV
-    //                                       |||||||||||||+-------------------- SUM
-    //                                       ||||||||||||+--------------------- MXR
-    //                                       |||||||||||+---------------------- TVM
-    //                                       ||||||||||+----------------------- TW
-    //                                       |||||||||+------------------------ TSR
-    //                                       ||||||||+------------------------- SPELP
-    //                                       |||||||+-------------------------- SDT
-    //                                       ||||||+--------------------------- WPRI
-    //                                       +--------------------------------- SD / WPRI
-
-    // upper half corresponds to mstatush bit meanings
-    static constexpr uint32_t upper_half = 0b00000000000000000000000000000000;
-    //                                       |||||||||||||||||||||||||||||/|/
-    //                                       ||||||||||||||||||||||||||||| +--- WPRI / UXL
-    //                                       ||||||||||||||||||||||||||||+----- WPRI / SXL
-    //                                       |||||||||||||||||||||||||||+------ SBE
-    //                                       |||||||||||||||||||||||||+-------- MBE
-    //                                       ||||||||||||||||||||||||+--------- GVA
-    //                                       |||||||||||||||||||||||+---------- MPV
-    //                                       ||||||||||||||||||||||+----------- WPRI
-    //                                       |||||||||||||||||||||+------------ MPELP
-    //                                       ||||||||||||||||||||+------------- MDT
-    //                                       +--------------------------------- WPRI / SD
-
-    static constexpr reg_t get_mstatus_mask() {
-        if constexpr(sizeof(reg_t) == 4)
-            return lower_half | riscv_hart_common<BASE>::extension_status_mask;
-        else if constexpr(sizeof(reg_t) == 8)
-            return static_cast<reg_t>(upper_half) << 32 | lower_half | riscv_hart_common<BASE>::extension_status_mask;
-        else
-            static_assert("Unsupported XLEN value");
-    }
-
     void write_mstatus(reg_t val) {
-        constexpr auto mask = get_mstatus_mask();
+        constexpr auto mask = base::get_mstatus_mask();
         auto new_val = (this->state.mstatus() & ~mask) | (val & mask);
-        if constexpr(riscv_hart_common<BASE>::extension_status_mask)
-            // set SD bit if any of FS or VS are dirty
-            // FIXME: this wont work if XS is 01 and FS is 10
-            if(reg_t masked = new_val & riscv_hart_common<BASE>::extension_status_mask; masked & (masked >> 1))
+        if constexpr(base::extension_status_mask)
+            if((new_val & base::extension_status_mask) == base::extension_status_mask)
                 new_val |= reg_t(1) << (sizeof(reg_t) * 8 - 1);
-
         this->state.mstatus = new_val;
     }
 
@@ -351,7 +297,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const addr_t& a, const unsigned le
 }
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_status(unsigned addr, reg_t& val) {
-    val = this->state.mstatus & get_mstatus_mask();
+    val = this->state.mstatus & base::get_mstatus_mask();
     return iss::Ok;
 }
 
diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h
index 0a48108..9edb2e4 100644
--- a/src/iss/arch/riscv_hart_msu_vp.h
+++ b/src/iss/arch/riscv_hart_msu_vp.h
@@ -35,7 +35,6 @@
 #ifndef _RISCV_HART_MSU_VP_H
 #define _RISCV_HART_MSU_VP_H
 
-#include "iss/arch/riscv_hart_mu_p.h"
 #include "iss/arch/traits.h"
 #include "iss/vm_if.h"
 #include "iss/vm_types.h"
@@ -67,78 +66,20 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_msu_vp :
     using this_class = riscv_hart_msu_vp<BASE>;
     using reg_t = typename core::reg_t;
     using phys_addr_t = typename core::phys_addr_t;
-    static constexpr uint32_t s_mask_lower = 0b00000000011111100000000100100010;
-    //                                         ||||||||||||||||/|/|/|/|||||||||
-    //                                         |||||||||||||||| | | | ||||||||+-- UIE
-    //                                         |||||||||||||||| | | | |||||||+--- SIE
-    //                                         |||||||||||||||| | | | ||||||+---- WPRI
-    //                                         |||||||||||||||| | | | |||||+----- MIE
-    //                                         |||||||||||||||| | | | ||||+------ UPIE
-    //                                         |||||||||||||||| | | | |||+------- SPIE
-    //                                         |||||||||||||||| | | | ||+-------- UBE
-    //                                         |||||||||||||||| | | | |+--------- MPIE
-    //                                         |||||||||||||||| | | | +---------- SPP
-    //                                         |||||||||||||||| | | +------------ VS
-    //                                         |||||||||||||||| | +-------------- MPP
-    //                                         |||||||||||||||| +---------------- FS
-    //                                         |||||||||||||||+------------------ XS
-    //                                         ||||||||||||||+------------------- MPRV
-    //                                         |||||||||||||+-------------------- SUM
-    //                                         ||||||||||||+--------------------- MXR
-    //                                         |||||||||||+---------------------- TVM
-    //                                         ||||||||||+----------------------- TW
-    //                                         |||||||||+------------------------ TSR
-    //                                         ||||||||+------------------------- SPELP
-    //                                         |||||||+-------------------------- SDT
-    //                                         ||||||+--------------------------- WPRI
-    //                                         +--------------------------------- SD / WPRI
-    static constexpr reg_t get_mstatus_mask(unsigned priv_lvl) {
-        return riscv_hart_mu_p<BASE>::get_mstatus_mask(priv_lvl) | ((priv_lvl >= PRIV_S) ? s_mask_lower : 0);
-    }
-    static constexpr reg_t get_mstatus_rd_mask(unsigned priv_lvl) {
-        if(sizeof(reg_t) == 4) {
-            return get_mstatus_mask(priv_lvl);
-        } else if(sizeof(reg_t) == 8) {
-            auto wr_mask = get_mstatus_mask(priv_lvl);
-            switch(priv_lvl) {
-            case PRIV_U:
-                return wr_mask;
-            case PRIV_S:
-                return wr_mask |= 0x300000000;
-            default:
-                return wr_mask |= 0xf00000000;
-            }
-        } else
-            assert(false && "Unsupported XLEN value");
-    }
 
-    template <typename T_ = reg_t, std::enable_if_t<std::is_same<T_, uint32_t>::value>* = nullptr>
-    void write_mstatus(T_ val, unsigned priv_lvl) {
+    void write_mstatus(reg_t val, unsigned priv_lvl) {
         reg_t old_val = this->state.mstatus;
-        auto mask = get_mstatus_mask(priv_lvl);
+        auto mask = base::get_msu_status_mask(priv_lvl);
         auto new_val = (old_val & ~mask) | (val & mask);
-        if constexpr(riscv_hart_common<BASE>::extension_status_mask)
-            // set SD bit if any of FS or VS are dirty
-            // FIXME: this wont work if XS is 01 and FS is 10
-            if(reg_t masked = new_val & riscv_hart_common<BASE>::extension_status_mask && masked & (masked >> 1))
-                new_val |= reg_t(1) << (sizeof(reg_t) * 8 - 1);
-        this->state.mstatus = new_val;
-    }
-
-    template <typename T_ = reg_t, std::enable_if_t<std::is_same<T_, uint64_t>::value>* = nullptr>
-    void write_mstatus(T_ val, unsigned priv_lvl) {
-        reg_t old_val = this->state.mstatus;
-        auto mask = get_mstatus_mask(priv_lvl);
-        auto new_val = (old_val & ~mask) | (val & mask);
-        if((new_val & this->state.mstatus.SXL.Mask) == 0) {
+        if constexpr(sizeof(reg_t) == 8) {
+            // Retain previous SXL and UXL value
             new_val |= old_val & this->state.mstatus.SXL.Mask;
-        }
-        if((new_val & this->state.mstatus.UXL.Mask) == 0) {
+
             new_val |= old_val & this->state.mstatus.UXL.Mask;
         }
-        if constexpr(riscv_hart_common<BASE>::extension_status_mask)
-            if(new_val && riscv_hart_common<BASE>::extension_status_mask)
-                // set SD bit if any of FS, VS and XS are set
+
+        if constexpr(base::extension_status_mask)
+            if((new_val & base::extension_status_mask) == base::extension_status_mask)
                 new_val |= reg_t(1) << (sizeof(reg_t) * 8 - 1);
         this->state.mstatus = new_val;
     }
@@ -439,7 +380,7 @@ iss::status riscv_hart_msu_vp<BASE, FEAT>::write(const addr_t& a, const unsigned
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_msu_vp<BASE, FEAT>::read_status(unsigned addr, reg_t& val) {
     auto req_priv_lvl = (addr >> 8) & 0x3;
-    val = this->state.mstatus & get_mstatus_rd_mask(req_priv_lvl);
+    val = this->state.mstatus & base::get_msu_status_mask(req_priv_lvl);
     return iss::Ok;
 }
 
diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h
index cf0c4d5..032ff17 100644
--- a/src/iss/arch/riscv_hart_mu_p.h
+++ b/src/iss/arch/riscv_hart_mu_p.h
@@ -35,7 +35,6 @@
 #ifndef _RISCV_HART_MU_P_H
 #define _RISCV_HART_MU_P_H
 
-#include "iss/arch/riscv_hart_m_p.h"
 #include "iss/arch/traits.h"
 #include "iss/vm_if.h"
 #include "iss/vm_types.h"
@@ -66,42 +65,11 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_mu_p : pu
     using reg_t = typename core::reg_t;
     using phys_addr_t = typename core::phys_addr_t;
 
-    static constexpr uint32_t u_mask_lower = 0b00000000000000000000000000010001;
-    //                                         ||||||||||||||||/|/|/|/|||||||||
-    //                                         |||||||||||||||| | | | ||||||||+-- UIE
-    //                                         |||||||||||||||| | | | |||||||+--- SIE
-    //                                         |||||||||||||||| | | | ||||||+---- WPRI
-    //                                         |||||||||||||||| | | | |||||+----- MIE
-    //                                         |||||||||||||||| | | | ||||+------ UPIE
-    //                                         |||||||||||||||| | | | |||+------- SPIE
-    //                                         |||||||||||||||| | | | ||+-------- UBE
-    //                                         |||||||||||||||| | | | |+--------- MPIE
-    //                                         |||||||||||||||| | | | +---------- SPP
-    //                                         |||||||||||||||| | | +------------ VS
-    //                                         |||||||||||||||| | +-------------- MPP
-    //                                         |||||||||||||||| +---------------- FS
-    //                                         |||||||||||||||+------------------ XS
-    //                                         ||||||||||||||+------------------- MPRV
-    //                                         |||||||||||||+-------------------- SUM
-    //                                         ||||||||||||+--------------------- MXR
-    //                                         |||||||||||+---------------------- TVM
-    //                                         ||||||||||+----------------------- TW
-    //                                         |||||||||+------------------------ TSR
-    //                                         ||||||||+------------------------- SPELP
-    //                                         |||||||+-------------------------- SDT
-    //                                         ||||||+--------------------------- WPRI
-    //                                         +--------------------------------- SD / WPRI
-    static constexpr reg_t get_mstatus_mask(unsigned priv_lvl) {
-        return u_mask_lower | (priv_lvl >= PRIV_M ? riscv_hart_m_p<BASE>::get_mstatus_mask() : 0);
-    }
-
     void write_mstatus(reg_t val, unsigned priv_lvl) {
-        auto mask = get_mstatus_mask(priv_lvl);
+        auto mask = base::get_mu_status_mask(priv_lvl);
         auto new_val = (this->state.mstatus() & ~mask) | (val & mask);
-        if constexpr(riscv_hart_common<BASE>::extension_status_mask)
-            // set SD bit if any of FS or VS are dirty
-            // FIXME: this wont work if XS is 01 and FS is 10
-            if(reg_t masked = new_val & riscv_hart_common<BASE>::extension_status_mask && masked & (masked >> 1))
+        if constexpr(base::extension_status_mask)
+            if((new_val & base::extension_status_mask) == base::extension_status_mask)
                 new_val |= reg_t(1) << (sizeof(reg_t) * 8 - 1);
         this->state.mstatus = new_val;
     }
@@ -358,7 +326,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const addr_t& a, const unsigned l
 }
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_status(unsigned addr, reg_t& val) {
-    val = this->state.mstatus & get_mstatus_mask((addr >> 8) & 0x3);
+    val = this->state.mstatus & base::get_mu_status_mask((addr >> 8) & 0x3);
     return iss::Ok;
 }
 

From 31cedb776f61a3d4b2e593186407b0b782209f9f Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Tue, 16 Dec 2025 07:30:28 +0100
Subject: [PATCH 71/77] corrects typo

---
 src/sysc/core2sc_adapter.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/sysc/core2sc_adapter.h b/src/sysc/core2sc_adapter.h
index 32b3fd7..668ed57 100644
--- a/src/sysc/core2sc_adapter.h
+++ b/src/sysc/core2sc_adapter.h
@@ -288,7 +288,7 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
 
     void _local_irq(short id, bool value) {
         reg_t mask = 0;
-        assert(id < 32 && "CLINT cannot handle more tahn 32 irq");
+        assert(id < 32 && "CLINT cannot handle more than 32 irq");
         mask = 1 << id;
         if(value) {
             this->csr[iss::arch::mip] |= mask;

From 84017d2f3f93f4e24a50e611fdb68d80b9d87cb1 Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Tue, 16 Dec 2025 11:27:24 +0100
Subject: [PATCH 72/77] introduces bandaid fix for mstatus rst val

---
 src/iss/arch/mstatus.h           | 10 +++++++++-
 src/iss/arch/riscv_hart_msu_vp.h |  4 ++++
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/src/iss/arch/mstatus.h b/src/iss/arch/mstatus.h
index 0a67596..2ea36d3 100644
--- a/src/iss/arch/mstatus.h
+++ b/src/iss/arch/mstatus.h
@@ -73,6 +73,8 @@ template <typename T> struct status<T, typename std::enable_if<std::is_same<T, u
     static inline unsigned FS(T v) { return bit_sub<13, 2>(v); };
     // machine previous privilege
     static inline unsigned MPP(T v) { return bit_sub<11, 2>(v); };
+    // vector unit status Off/Initial/Clean/Dirty
+    static inline unsigned VS(T v) { return bit_sub<9, 2>(v); };
     // supervisor previous privilege
     static inline unsigned SPP(T v) { return bit_sub<8, 1>(v); };
     // previous machine interrupt-enable
@@ -121,6 +123,8 @@ template <typename T> struct status<T, typename std::enable_if<std::is_same<T, u
     static inline unsigned FS(T v) { return bit_sub<13, 2>(v); };
     // machine previous privilege
     static inline unsigned MPP(T v) { return bit_sub<11, 2>(v); };
+    // vector unit status Off/Initial/Clean/Dirty
+    static inline unsigned VS(T v) { return bit_sub<9, 2>(v); };
     // supervisor previous privilege
     static inline unsigned SPP(T v) { return bit_sub<8, 1>(v); };
     // previous machine interrupt-enable
@@ -165,6 +169,8 @@ template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T
     BF_FIELD(FS, 13, 2);
     // machine previous privilege
     BF_FIELD(MPP, 11, 2);
+    // vector unit status Off/Initial/Clean/Dirty
+    BF_FIELD(VS, 9, 2);
     // supervisor previous privilege
     BF_FIELD(SPP, 8, 1);
     // previous machine interrupt-enable
@@ -220,6 +226,8 @@ template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T
     BF_FIELD(FS, 13, 2);
     // machine previous privilege
     BF_FIELD(MPP, 11, 2);
+    // vector unit status Off/Initial/Clean/Dirty
+    BF_FIELD(VS, 9, 2);
     // supervisor previous privilege
     BF_FIELD(SPP, 8, 1);
     // previous machine interrupt-enable
@@ -238,7 +246,7 @@ template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T
 
     mstatus_t mstatus;
 
-    static const T mstatus_reset_val = 0x500001800;
+    static const T mstatus_reset_val = 0x1800;
 };
 } // namespace arch
 } // namespace iss
diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h
index 9edb2e4..89ca0f4 100644
--- a/src/iss/arch/riscv_hart_msu_vp.h
+++ b/src/iss/arch/riscv_hart_msu_vp.h
@@ -127,6 +127,10 @@ template <typename BASE, features_e FEAT>
 riscv_hart_msu_vp<BASE, FEAT>::riscv_hart_msu_vp()
 : mmu(base::get_priv_if())
 , default_mem(base::get_priv_if()) {
+    if constexpr(sizeof(reg_t) == 8)
+        // set UXL and SXL to indicate 64 bits
+        // FIXME: this value is not preserved in resets
+        this->state.mstatus.backing.val |= 0x500000000;
     // common regs
     const std::array<unsigned, 16> rwaddrs{
         {mepc, mtvec, mscratch, mcause, mtval, sepc, stvec, sscratch, scause, stval, sscratch, uepc, utvec, uscratch, ucause, utval}};

From 2ca7c803813ec9d0145956e62c640eaa30a66d55 Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Tue, 16 Dec 2025 11:27:48 +0100
Subject: [PATCH 73/77] caches conan dependencies in github action

---
 .github/workflows/ci-compile.yml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/.github/workflows/ci-compile.yml b/.github/workflows/ci-compile.yml
index b053839..97c9fe6 100644
--- a/.github/workflows/ci-compile.yml
+++ b/.github/workflows/ci-compile.yml
@@ -31,6 +31,12 @@ jobs:
 
       - name: Update submodules
         run: git submodule update --init --recursive
+        
+      - name: Cache Conan
+        uses: actions/cache@v4
+        with:
+          path: ~/.conan2
+          key: conan-${{ runner.os }}-unit-cpp${{ matrix.cpp_std }}-${{ hashFiles('conanfile.py') }}
 
       - name: Install dependencies
         run: |

From 812d7623e0e1438797c45a579e7cf09fa4041ec4 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Tue, 30 Dec 2025 11:35:34 +0100
Subject: [PATCH 74/77] adds executing code in systemc context

---
 src/sysc/core2sc_adapter.h | 10 +++++++---
 src/sysc/core_complex.cpp  |  3 ++-
 src/sysc/core_complex.h    |  8 ++++++++
 src/sysc/core_complex_if.h |  3 +++
 4 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/src/sysc/core2sc_adapter.h b/src/sysc/core2sc_adapter.h
index 668ed57..3118495 100644
--- a/src/sysc/core2sc_adapter.h
+++ b/src/sysc/core2sc_adapter.h
@@ -244,9 +244,13 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
     void wait_until(uint64_t flags) {
         SCCDEBUG(owner->hier_name()) << "Sleeping until interrupt";
         PLAT::wait_until(flags);
-        while((this->csr[iss::arch::mip] & this->csr[iss::arch::mie]) == 0) {
-            sc_core::wait(wfi_evt);
-        }
+        std::function<void(void)> f = [this]() {
+            while((this->csr[iss::arch::mip] & this->csr[iss::arch::mie]) == 0) {
+                sc_core::wait(this->wfi_evt);
+            }
+            SCCINFO(this->owner->hier_name()) << "Got WFI event";
+        };
+        owner->exec_on_sysc(f);
     }
 
 private:
diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index 46984fa..5c8e341 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -187,6 +187,7 @@ core_complex<BUSWIDTH, QK>::core_complex(sc_module_name const& name)
 #endif
 
 template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::init() {
+    core_complex_if::exec_on_sysc = util::delegate<void(std::function<void(void)>&)>::from<this_class, &this_class::exec_on_sysc<QK>>(this);
     ibus.register_invalidate_direct_mem_ptr([this](uint64_t start, uint64_t end) -> void {
         auto lut_entry = fetch_lut.getEntry(start);
         if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
@@ -378,7 +379,7 @@ template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::r
         while(curr_clk.read() == SC_ZERO_TIME) {
             wait(curr_clk.value_changed_event());
         }
-        quantum_keeper.reset();
+        quantum_keeper.reset(sc_core::sc_time_stamp());
         core->set_interrupt_execution(false);
         run_iss();
     } while(!core->get_interrupt_execution());
diff --git a/src/sysc/core_complex.h b/src/sysc/core_complex.h
index e0e884c..2c4c097 100644
--- a/src/sysc/core_complex.h
+++ b/src/sysc/core_complex.h
@@ -242,6 +242,10 @@ class core_complex : public sc_core::sc_module, public scc::traceable, public co
     exec_get_direct_mem_ptr(tlm::tlm_generic_payload& gp, tlm::tlm_dmi& dmi_data) {
         return dbus->get_direct_mem_ptr(gp, dmi_data);
     }
+    template <typename U = QK>
+    typename std::enable_if<std::is_same<U, tlm::scc::quantumkeeper_mt>::value>::type exec_on_sysc(std::function<void(void)>& f) {
+        quantum_keeper.execute_on_sysc(f);
+    }
     template <typename U = QK> typename std::enable_if<std::is_same<U, tlm::scc::quantumkeeper_mt>::value>::type run_iss() {
         core->setup_mt();
         quantum_keeper.check_and_sync(sc_core::SC_ZERO_TIME);
@@ -267,6 +271,10 @@ class core_complex : public sc_core::sc_module, public scc::traceable, public co
         quantum_keeper.execute_on_sysc([this, &gp, &dmi_data, &result]() { result = dbus->get_direct_mem_ptr(gp, dmi_data); });
         return result;
     }
+    template <typename U = QK>
+    typename std::enable_if<std::is_same<U, tlm::scc::quantumkeeper>::value>::type exec_on_sysc(std::function<void(void)>& f) {
+        f();
+    }
     template <typename U = QK> typename std::enable_if<std::is_same<U, tlm::scc::quantumkeeper>::value>::type run_iss() {
         vm->start(std::numeric_limits<uint64_t>::max(), dump_ir);
     }
diff --git a/src/sysc/core_complex_if.h b/src/sysc/core_complex_if.h
index 5e57d30..5e45a33 100644
--- a/src/sysc/core_complex_if.h
+++ b/src/sysc/core_complex_if.h
@@ -35,6 +35,7 @@
 
 #include <iss/vm_types.h>
 #include <scc/signal_opt_ports.h>
+#include <util/delegate.h>
 
 namespace sysc {
 namespace riscv {
@@ -57,6 +58,8 @@ struct core_complex_if {
     //! Allow quantum keeper handling
     virtual void sync(uint64_t) = 0;
 
+    util::delegate<void(std::function<void(void)>&)> exec_on_sysc;
+
     virtual char const* hier_name() = 0;
 
     scc::sc_in_opt<uint64_t> mtime_i{"mtime_i"};

From 8b1f2df3a373a28085bea6b626d4e9f83f9a40ac Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Tue, 30 Dec 2025 11:35:56 +0100
Subject: [PATCH 75/77] adds conan caching to gh action

---
 .github/workflows/ci-compile.yml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/.github/workflows/ci-compile.yml b/.github/workflows/ci-compile.yml
index 97c9fe6..03723ea 100644
--- a/.github/workflows/ci-compile.yml
+++ b/.github/workflows/ci-compile.yml
@@ -38,6 +38,12 @@ jobs:
           path: ~/.conan2
           key: conan-${{ runner.os }}-unit-cpp${{ matrix.cpp_std }}-${{ hashFiles('conanfile.py') }}
 
+      - name: Cache Conan
+        uses: actions/cache@v4
+        with:
+          path: ~/.conan2
+          key: conan-${{ runner.os }}-unit-cpp${{ matrix.cpp_std }}-${{ hashFiles('conanfile.py') }}
+
       - name: Install dependencies
         run: |
           sudo apt-get update

From 7c59338d343c4be74422c4de583fec132286980d Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Fri, 2 Jan 2026 11:44:00 +0100
Subject: [PATCH 76/77] adds automatic removal of extensions in core_complex
 read/write

---
 src/sysc/core_complex.cpp      | 32 +++++++++++++++++---------------
 src/sysc/memspace_dispatcher.h |  7 +++----
 2 files changed, 20 insertions(+), 19 deletions(-)

diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index 5c8e341..3eddff3 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -39,7 +39,6 @@
 #include <iss/iss.h>
 #include <iss/vm_types.h>
 #include "iss_factory.h"
-#include "tlm/scc/quantum_keeper.h"
 #include "sysc/memspace_extension.h"
 #include "tlm/scc/tlm_id.h"
 #include "util/range_lut.h"
@@ -56,6 +55,7 @@
 #include <iss/plugin/cycle_estimate.h>
 #include <iss/plugin/instruction_count.h>
 #include <util/ities.h>
+#include <util/defer.h>
 // clang-format on
 
 #ifdef HAS_SCV
@@ -405,8 +405,8 @@ bool core_complex<BUSWIDTH, QK>::read_mem(const addr_t& addr, unsigned length, u
         else
             dbus_inc += lut_entry.get_read_latency() / curr_clk;
 #ifndef NDEBUG
-        SCCTRACE(this->name()) << "[local time: " << quantum_keeper.get_local_time() << "]: finish dmi_read_mem(0x" << std::hex << addr.val
-                               << ") : 0x"
+        SCCTRACE(this->name()) << "[local offset: +" << quantum_keeper.get_local_time() << "]: finish dmi_read_mem(0x" << std::hex
+                               << addr.val << ") : 0x"
                                << (length == 4   ? *(uint32_t*)data
                                    : length == 2 ? *(uint16_t*)data
                                                  : (unsigned)*data);
@@ -425,6 +425,10 @@ bool core_complex<BUSWIDTH, QK>::read_mem(const addr_t& addr, unsigned length, u
             gp.set_extension(&mem_spc);
         tlm::scc::initiator_id_extension id_ext{mhartid.get_value()};
         gp.set_extension(&id_ext);
+        DEFER {
+            gp.set_extension<tlm::scc::initiator_id_extension>(nullptr);
+            gp.set_extension<sysc::memspace::tlm_memspace_extension<>>(nullptr);
+        };
         auto pre_delay = delay;
         exec_b_transport(gp, delay, is_fetch);
         if(pre_delay > delay) {
@@ -436,13 +440,12 @@ bool core_complex<BUSWIDTH, QK>::read_mem(const addr_t& addr, unsigned length, u
             else
                 dbus_inc += incr;
         }
-        SCCTRACE(this->name()) << "[local time: " << delay << "]: finish read_mem(0x" << std::hex << addr.val << ") : 0x"
+        SCCTRACE(this->name()) << "[local offset: +" << delay << "]: finish read_mem(0x" << std::hex << addr.val << ") : 0x"
                                << (length == 4   ? *(uint32_t*)data
                                    : length == 2 ? *(uint16_t*)data
                                                  : (unsigned)*data);
-        if(gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
+        if(gp.get_response_status() != tlm::TLM_OK_RESPONSE)
             return false;
-        }
         if(gp.is_dmi_allowed() && !GET_PROP_VALUE(disable_dmi)) {
             gp.set_command(tlm::TLM_READ_COMMAND);
             gp.set_address(addr.val);
@@ -452,8 +455,6 @@ bool core_complex<BUSWIDTH, QK>::read_mem(const addr_t& addr, unsigned length, u
                     dmi_lut.addEntry(dmi_data, dmi_data.get_start_address(), dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
             }
         }
-        gp.set_extension<tlm::scc::initiator_id_extension>(nullptr);
-        gp.set_extension<sysc::memspace::tlm_memspace_extension<>>(nullptr);
         return true;
     }
 }
@@ -466,8 +467,8 @@ bool core_complex<BUSWIDTH, QK>::write_mem(const addr_t& addr, unsigned length,
         std::copy(data, data + length, lut_entry.get_dmi_ptr() + offset);
         dbus_inc += lut_entry.get_write_latency() / curr_clk;
 #ifndef NDEBUG
-        SCCTRACE(this->name()) << "[local time: " << quantum_keeper.get_local_time() << "]: finish dmi_write_mem(0x" << std::hex << addr.val
-                               << ") : 0x"
+        SCCTRACE(this->name()) << "[local offset: +" << quantum_keeper.get_local_time() << "]: finish dmi_write_mem(0x" << std::hex
+                               << addr.val << ") : 0x"
                                << (length == 4   ? *(uint32_t*)data
                                    : length == 2 ? *(uint16_t*)data
                                                  : (unsigned)*data);
@@ -487,19 +488,22 @@ bool core_complex<BUSWIDTH, QK>::write_mem(const addr_t& addr, unsigned length,
         gp.set_extension(&mem_spc);
         tlm::scc::initiator_id_extension id_ext{mhartid.get_value()};
         gp.set_extension(&id_ext);
+        DEFER {
+            gp.set_extension<tlm::scc::initiator_id_extension>(nullptr);
+            gp.set_extension<sysc::memspace::tlm_memspace_extension<>>(nullptr);
+        };
         auto pre_delay = delay;
         exec_b_transport(gp, delay);
         if(pre_delay > delay)
             quantum_keeper.reset();
         else
             dbus_inc += (delay - quantum_keeper.get_local_time()) / curr_clk;
-        SCCTRACE(this->name()) << "[local time: " << delay << "]: finish write_mem(0x" << std::hex << addr.val << ") : 0x"
+        SCCTRACE(this->name()) << "[local offset: +" << delay << "]: finish write_mem(0x" << std::hex << addr.val << ") : 0x"
                                << (length == 4   ? *(uint32_t*)data
                                    : length == 2 ? *(uint16_t*)data
                                                  : (unsigned)*data);
-        if(gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
+        if(gp.get_response_status() != tlm::TLM_OK_RESPONSE)
             return false;
-        }
         if(gp.is_dmi_allowed() && !GET_PROP_VALUE(disable_dmi)) {
             gp.set_command(tlm::TLM_READ_COMMAND);
             gp.set_address(addr.val);
@@ -510,8 +514,6 @@ bool core_complex<BUSWIDTH, QK>::write_mem(const addr_t& addr, unsigned length,
                         .addEntry(dmi_data, dmi_data.get_start_address(), dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
             }
         }
-        gp.set_extension<tlm::scc::initiator_id_extension>(nullptr);
-        gp.set_extension<sysc::memspace::tlm_memspace_extension<>>(nullptr);
         return true;
     }
 }
diff --git a/src/sysc/memspace_dispatcher.h b/src/sysc/memspace_dispatcher.h
index 6c42ebe..d5b2209 100644
--- a/src/sysc/memspace_dispatcher.h
+++ b/src/sysc/memspace_dispatcher.h
@@ -87,19 +87,18 @@ struct memspace_dispatcher : sc_core::sc_module {
     std::unordered_map<MEMSPACE, size_t> space_mapping{};
     size_t default_port = 0;
     intor_sckt& mapped_intor(const tlm::tlm_generic_payload& trans, bool dmi = false) {
-        auto prefix = dmi ? "DMI " : "";
-        tlm_memspace_extension<MEMSPACE>* ext;
-        trans.get_extension(ext);
-        if(ext) {
+        if(auto* ext = trans.get_extension<tlm_memspace_extension<MEMSPACE>>()) {
             auto it = space_mapping.find(ext->get_space());
             if(it != space_mapping.end()) {
 #ifndef NDEBUG
+                auto prefix = dmi ? "DMI " : "";
                 SCCTRACE(SCMOD) << "Sending " << prefix << "transaction to initiator " << it->second;
 #endif
                 return initiator[it->second];
             }
         }
 #ifndef NDEBUG
+        auto prefix = dmi ? "DMI " : "";
         SCCTRACE(SCMOD) << "Sending " << prefix << "transaction to default initiator " << default_port;
 #endif
         return initiator[default_port];

From 209217e90db2f58411d0f74cecfcf4111061a5fd Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Tue, 6 Jan 2026 10:08:06 +0100
Subject: [PATCH 77/77] fixes missing irq refactoring for tlm_signal use

---
 CMakeLists.txt            | 46 +++++++++++++++++++++++++++++++--------
 src/sysc/core_complex.cpp | 18 +++------------
 2 files changed, 40 insertions(+), 24 deletions(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index dfd4462..4b1d03d 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -127,9 +127,6 @@ if(IS_DIRECTORY "${PROJECT_SOURCE_DIR}/../dbt-rise-custom")
 endif()
 # Define the library
 add_library(${PROJECT_NAME} SHARED ${LIB_SOURCES})
-if(USE_SC_SIGNAL4IRQ)
-    target_compile_definitions(${PROJECT_NAME} PUBLIC SC_SIGNAL_IF)
-endif()
 if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
     target_compile_options(${PROJECT_NAME} PRIVATE -Wno-shift-count-overflow)
 elseif("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC")
@@ -242,6 +239,8 @@ endif()
 ###############################################################################
 if(TARGET scc-sysc)
     project(dbt-rise-riscv_sc VERSION 1.0.0)
+    set(USE_SC_SIGNAL4IRQ OFF CACHE BOOL "Enable the use of ssc_signals for interrupt delivery")
+
     set(LIB_SOURCES
         src/sysc/core_complex.cpp
         src/sysc/register_cores.cpp
@@ -253,20 +252,22 @@ if(TARGET scc-sysc)
         FILE(GLOB GEN_SC_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/../dbt-rise-custom/src/sysc/register_*.cpp)
         list(APPEND LIB_SOURCES ${GEN_SC_SOURCES})
     endif()
-    add_library(${PROJECT_NAME} ${LIB_SOURCES})
-    target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_SYSTEMC)
-    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-riscv scc-sysc)
+    set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/src/sysc/core_complex.h)
+
+    add_library(${PROJECT_NAME}_sig ${LIB_SOURCES})
+    target_compile_definitions(${PROJECT_NAME}_sig PUBLIC SC_SIGNAL_IF)
+    target_compile_definitions(${PROJECT_NAME}_sig PUBLIC WITH_SYSTEMC SC_SIGNAL_IF)
+    target_link_libraries(${PROJECT_NAME}_sig PUBLIC dbt-rise-riscv scc-sysc)
 
     # if(WITH_LLVM)
     # target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
     # endif()
-    set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/src/sysc/core_complex.h)
-    set_target_properties(${PROJECT_NAME} PROPERTIES
+    set_target_properties(${PROJECT_NAME}_sig PROPERTIES
         VERSION ${PROJECT_VERSION}
         FRAMEWORK FALSE
         PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
     )
-    install(TARGETS ${PROJECT_NAME} COMPONENT ${PROJECT_NAME}
+    install(TARGETS ${PROJECT_NAME}_sig COMPONENT ${PROJECT_NAME}
         EXPORT ${PROJECT_NAME}Targets # for downstream dependencies
         ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} # static lib
         RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} # binaries
@@ -275,6 +276,33 @@ if(TARGET scc-sysc)
         PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/sysc # headers for mac (note the different component -> different package)
         INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers
     )
+
+    add_library(${PROJECT_NAME}_tlm ${LIB_SOURCES})
+    target_compile_definitions(${PROJECT_NAME}_tlm PUBLIC WITH_SYSTEMC)
+    target_link_libraries(${PROJECT_NAME}_tlm PUBLIC dbt-rise-riscv scc-sysc)
+
+    # if(WITH_LLVM)
+    # target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
+    # endif()
+    set_target_properties(${PROJECT_NAME}_tlm PROPERTIES
+        VERSION ${PROJECT_VERSION}
+        FRAMEWORK FALSE
+        PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
+    )
+    install(TARGETS ${PROJECT_NAME}_tlm COMPONENT ${PROJECT_NAME}
+        EXPORT ${PROJECT_NAME}Targets # for downstream dependencies
+        ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} # static lib
+        RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} # binaries
+        LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} # shared lib
+        FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
+        PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/sysc # headers for mac (note the different component -> different package)
+        INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers
+    )
+    if(USE_SC_SIGNAL4IRQ)
+        add_library(${PROJECT_NAME} ALIAS ${PROJECT_NAME}_sig)
+    else()
+        add_library(${PROJECT_NAME} ALIAS ${PROJECT_NAME}_tlm)
+    endif()
 endif()
 
 project(elfio-test)
diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index 3eddff3..3b48794 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -214,21 +214,9 @@ template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::i
     SC_METHOD(rst_cb);
     sensitive << rst_i;
 #ifdef USE_TLM_SIGNAL
-    sw_irq_i.register_nb_transport([this](tlm::scc::tlm_signal_gp<bool>& gp, tlm::tlm_phase& p, sc_core::sc_time& t) {
-        cpu->local_irq(3, gp.get_value());
-        return tlm::TLM_COMPLETED;
-    });
-    timer_irq_i.register_nb_transport([this](tlm::scc::tlm_signal_gp<bool>& gp, tlm::tlm_phase& p, sc_core::sc_time& t) {
-        cpu->local_irq(7, gp.get_value());
-        return tlm::TLM_COMPLETED;
-    });
-    ext_irq_i.register_nb_transport([this](tlm::scc::tlm_signal_gp<bool>& gp, tlm::tlm_phase& p, sc_core::sc_time& t) {
-        cpu->local_irq(11, gp.get_value());
-        return tlm::TLM_COMPLETED;
-    });
-    for(auto i = 0U; i < local_irq_i.size(); ++i)
-        local_irq_i[i].register_nb_transport([this, i](tlm::scc::tlm_signal_gp<bool>& gp, tlm::tlm_phase& p, sc_core::sc_time& t) {
-            cpu->local_irq(16 + i, gp.get_value());
+    for(auto i = 0U; i < clint_irq_i.size(); ++i)
+        clint_irq_i[i].register_nb_transport([this, i](tlm::scc::tlm_signal_gp<bool>& gp, tlm::tlm_phase& p, sc_core::sc_time& t) {
+            core->local_irq(i, gp.get_value());
             return tlm::TLM_COMPLETED;
         });
 #else